JPH04344959A - Power supply device for memory - Google Patents

Abstract

PURPOSE:To perform stable power supply without deteriorating the voltage of backup power source when switching a main power source and an auxiliary power source being the backup power source of a memory. CONSTITUTION:A charge/discharge current control circuit is composed of a resistance R38 for discharge current restriction between a main power source 4 and a secondary battery 9, a short-circuited transistor TR211 for current restriction short-circuiting the R38 for discharge current restriction when a main power source 4 is turned off, and a diode 12 for leakage current prevention preventing the leakage of current from the secondary battery 9 to the main power source 4 when the main power supply 4 is turned off. The power is supplied to the backup current by charging the secondary battery 9 by the main power source 4 when the main power source 4 is turned on, the secondary battery is charged by the main power source 4 discharging the secondary battery 9 when the main power source 4 is turned off.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a memory power supply device, and more particularly to a memory power supply device that supplies stable power to protect data stored in the memory. It is.

0002

BACKGROUND OF THE INVENTION Conventional power supply devices for memory of this type include Japanese Patent Laid-Open Nos. 61-213909 and 1-617.
06 and Japanese Patent Application Laid-Open No. 1-130244.

Conventionally, for example, numerical control devices that control the operation of machine tools require unique parameters for each machine, and also require individual machining programs depending on the workpiece. Therefore, a storage device whose contents can be easily changed is provided to store each piece of information. Usually, random access memory (hereinafter referred to as RAM) is used, which requires backup with an auxiliary battery or the like.

FIG. 3(a) is a circuit diagram showing a conventional memory power supply device using a secondary battery as a backup auxiliary power source, and FIG. 3(b) is a time chart showing its operation.

In the figure, 1 is an input terminal for the PDWN signal for control, 2 is a pull-down resistor for level stabilization during backup, and 3 is a pull-down resistor that allows power to be supplied from the auxiliary power supply even when the power is off.
Backup power supply supplied to AM, 4 is the main power supply, 5 is a low power consumption c-MOS type IC that maintains the state of the control PDWN signal from PDWN signal input terminal 1, 6 is for limiting the base current of the transistor Resistors R1 and 7 are power supply switching transistors TR1 that switch between the main power supply and the auxiliary power supply.
, 8 is a resistor R3 for limiting the charging current of the secondary battery, 9 is a secondary battery serving as an auxiliary power source, and 10 is a secondary battery mounting terminal.

Next, the operation of the memory power supply device having this configuration will be explained.

The PDWN signal input terminal 1 for controlling switching between the main power source 4 and the secondary battery 9, which is an auxiliary power source, is in an open state when the main power source 4 is off. Therefore, due to the action of the level stabilizing pull-down resistor 2, the c-MOS becomes "L" level and is supplied with power by the backup power supply 3.
The "L" level of the PDWN signal is determined by the type IC5.

The function of the power supply switching transistor TR17 for switching between the main power supply and the auxiliary power supply will now be described with reference to FIG. (a) to (c) of FIG. 4 are circuit diagrams showing the operation of a power supply switching transistor in a conventional memory power supply device, in which (a) is a state in which the main power supply is off;
(b) shows the state immediately after the main power is turned on, and (c) shows the state when the main power is on and the PDWN signal becomes "H".

In FIG. 4A, when the main power supply 4 is off, the input of the c-MOS type IC 5 is at the "L" level, so the output is inverted and becomes the "H" level. The "H" level voltage at this time is lower than the voltage of the backup power supply 3 supplied to the c-MOS type IC5. The voltage applied to the base of the power supply switching transistor 7 is "H" through the base current limiting resistor R16, but since the main power supply 4 connected to the emitter is off, that is, 0 [V], the power supply switching transistor 7 cannot be switched. A reverse voltage is applied between the base and emitter of the transistor TR17, and the power supply switching transistor TR1
7 is in the off state. The backup power source 3 is supplied from an auxiliary power source using a secondary battery 9 via a charging current limiting resistor R38.

In FIG. 4(b), immediately after the main power supply 4 is turned on, the PDWN signal is still "L".
”, and this PDWN signal backup c
-The output of the MOS type IC5 is "H". The base and emitter of the power supply switching transistor TR17 are both at the "H" level, and the power supply switching transistor TR17 is supposed to be maintained in the off state. However, normally, the voltage of the backup secondary battery 9 is charged from the main power supply 4 and is set lower than the main power supply voltage in order to suppress discharge current. Therefore, at the time of transition from the auxiliary power source to the main power source, a potential difference between the auxiliary power source voltage and the main power source voltage occurs in the forward direction between the base and emitter of the power source switching transistor TR17, and a forward current leaks. Then, c-MOS type IC5
The power supply voltage VCC and output voltage VOUT are VCC<VO
UT, the operation of the c-MOS type IC 5 becomes unstable, and current consumption increases. However, since the base current limiting resistor R16 works, this increase in current consumption is temporary.

In (c) of FIG. 4, when the main power supply 4 is on and the PDWN signal is "H", the output of the c-MOS type IC 5 is "L", and the power supply switching transistor T
The base of R17 is “L”, the emitter is “H”,
Since a sufficient forward potential difference is generated between the base and the emitter, the power supply switching transistor TR17 is turned on, and the emitter and collector are also conductive. Therefore, power is supplied to the backup power supply 3 connected to the emitter of the power supply switching transistor TR17. Further, since the main power supply voltage is higher than the auxiliary power supply voltage, the secondary battery 9 in FIG. 3 is charged by the main power supply 4.

Note that the c-MOS type IC 5 in FIG.
It is structured like this. FIG. 5 is a circuit diagram showing the inside of the c-MOS type IC 5 of the memory power supply device.

In the figure, 14 and 15 are diodes;
6 and 17 are MOS type transistors, 18 is a resistor, 19 is an input terminal of the c-MOS type IC5 to which the PDWN signal is input, and 20 is an output terminal of the c-MOS type IC5.

Next, the case where the backup power source is switched from the main power source to the auxiliary power source will be explained using FIG. FIGS. 6A to 6C are circuit diagrams showing the operation of a secondary battery in a conventional memory power supply device when the main power supply is turned off.

In FIG. 6A, when the main power supply 4 is on and the PDWN signal is "H", the power supply switching transistor TR17 is on, and the main power supply 4 is connected to the secondary battery 9, which is an auxiliary power supply. is charging.

In FIG. 6(b), when the PDWN signal for switching between the main power source and the auxiliary power source becomes "L",
An attempt is made to switch the backup power source 3 to the secondary battery 9. In this case, as in FIG. 4(b), a potential difference occurs between the main power supply 4 and the backup power supply 3, and the power supply switching transistor T
Leakage current flows from the emitter of R17 to the base. However, when the PDWN signal transitions from "H" to "L", the backup power supply 3 is at the same potential as the main power supply 4, and as shown in FIG.
The current consumption will not increase.

However, in FIG. 6(c), PDWN
When the signal becomes "L", the main power supply 4 is turned off, and the power supply switching transistor TR1 7 is turned off, the secondary battery 9
is switched from charging to discharging, and supply of power to the backup power source 3 is started. However, the charging current limiting resistor R38, which acts to prevent overcharging of the secondary battery 9,
becomes a load during discharging, and during the transition from charging to discharging,
There is a temporary shortage of power supply to the backup power source 3.

Next, another conventional memory power supply device that uses a transistor to short-circuit a charging current limiting resistor during discharging will be described. As a conventional memory power supply device of this type, there is a technique disclosed in Japanese Patent Laid-Open No. 1-286744.

FIG. 7 is a circuit diagram showing a circuit using a transistor to short-circuit a charging current limiting resistor during discharging in another conventional memory power supply device, and FIG.
3 is a time chart showing the operation of the circuit of FIG. In the figure, Figure 3
The same reference numerals and symbols indicate the same or corresponding components as those in FIG.

In the figure, 11 is a current limiting short-circuiting transistor TR2 that short-circuits the charging current limiting resistor R38 during discharging, and 21 is a switching control signal that inputs a BACK UP signal that is a switching control signal between the main power source and the auxiliary power source. This is an input terminal and corresponds to the PDWN signal input terminal 1 in FIG. 22 and 24 are digital transistors TR
3, TR4, 23, 25, 26 are resistors R2, R4
, R5, and 27 is an electronic circuit serving as a load of the backup power supply.

The operation of this circuit will be explained using the time chart of FIG. When the main power supply 4 is on, the switching control signal (BACK UP signal) indicating a power outage is "H",
The digital transistor TR3 22 is on, the power supply switching transistor TR1 7 is also on, but the digital transistor TR4 24 is off, the current limiting short-circuit transistor TR2 11 is off, and the charging current limiting resistor R3 is off.
8 works effectively, and the secondary battery 9, which is the auxiliary power source C1, is charged from the main power source 4 via the power source switching transistor TR1 7 and the charging current limiting resistor R3 8. The moment the main power source 4 is turned off, the secondary battery 9 switches from charging to discharging, and the load on the backup power source 3 temporarily increases. At this time, the current limiting short-circuit transistor T
The charging current limiting resistor R3 8 is not short-circuited by R2 11. Therefore, there is a shortage of backup power supply, and the voltage of the backup power supply 3 temporarily drops.

When the main power supply 4 is turned off and the switching control signal (BACK UP signal) indicating a power outage state becomes "L", the digital transistor TR3 22 is turned off,
The digital transistor TR4 24 is turned on and the current limiting short-circuit transistor TR2 11 is turned on, which are successively operated and switched. However, because there is a time delay from when the main power supply 4 is turned off until the switching control signal (BACK UP signal) is generated, and a time delay in the switching of four transistors, transient Unable to absorb the increase in backup power.

On the other hand, when switching from a power outage to charging, fortunately there is a switching delay of four transistors, and when the main power supply 4 is switched from off to on, the charging current limiting resistor R38 is still short-circuited. It remains unchanged and can absorb transient increases in backup power.
There is no drop in the voltage of the backup power supply 3.

[0024]

[Problems to be Solved by the Invention] In the conventional memory power supply device as described above, when the main power supply 4 is on,
The auxiliary power source was charged, and when the main power source 4 was off, the auxiliary power source was discharged to supply power to the backup power source.

However, in the conventional memory power supply device as shown in FIG. 3, there is no current limiting shorting transistor TR211 that shorts the charging current limiting resistor R38, and the backup power source that is the memory power source is not connected to the auxiliary power source. When switching to the main power source and when switching from the main power source to the auxiliary power source, there was a temporary shortage of power supply from the auxiliary power source to the backup power source.

Also, in other conventional memory power supply devices that use transistors to short-circuit charging current limiting resistors during discharging as shown in FIG. There was a shortage, and the voltage of backup power supply 3 temporarily dropped.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a memory power supply device that can stably supply power without reducing the voltage of the backup power source when switching between the main power source and the auxiliary power source, which are the backup power sources for the memory. It is.

[0028]

[Means for Solving the Problems] A memory power supply device according to the present invention includes a main power supply that supplies power to a memory circuit using a nonvolatile memory, and a memory circuit that is charged by the main power supply and that is powered off when the main power supply is turned off. an auxiliary power supply that supplies power to the memory circuit in order to protect the memory circuit; and a charging/discharging control circuit that limits the charging current to the auxiliary power supply and reduces the load during power supply due to discharge of the auxiliary power supply. It is equipped with the following.

[0029]

[Operation] In the memory power supply device of the present invention,
charged by the mains power supply that powers the memory circuits,
charging current to an auxiliary power supply that supplies power to the memory circuit to protect the memory circuit when the main power supply is off;
The charge/discharge control circuit reduces the load on power supply due to discharge of the auxiliary power supply, which prevents overcharging of the auxiliary power supply, and also allows the backup power supply that is the memory power source to be switched from the auxiliary power supply to the main power supply. When switching from the main power source to the auxiliary power source and from the main power source to the auxiliary power source, the power supply capability of the auxiliary power source does not decrease, power supply shortage from the auxiliary power source to the backup power source does not occur, and the voltage of the backup power source does not drop.

[0030]

[Examples] Examples of the present invention will be described below.

FIG. 1 is a circuit diagram showing a memory power supply device according to an embodiment of the present invention. In the drawings, the same reference numerals and symbols as those in the above conventional example indicate constituent parts that are the same as or correspond to those in the above conventional example.

In the figure, reference numeral 11 indicates a current limiting short-circuit transistor TR2 that short-circuits the charging current limiting resistor R3 to 8 when the main power source 4 is off, and 12 indicates a current limiting short-circuit transistor TR2 that short-circuits the charging current limiting resistor R3 to 8 when the main power source 4 is off. a leakage current prevention diode that protects the current limiting short-circuit transistor TR211 by lowering the voltage to a voltage of 9 and prevents current from leaking from the secondary battery 9 to the main power source 4 when the main power source 4 is off;
13 is a current limiting resistor. That is, this memory power supply device includes a current limiting short-circuit transistor TR2 11 and a leakage current prevention diode 12 in the circuit shown in FIG. 3(a).
, and a current limiting resistor 13 are added.

Next, the operation of the memory power supply device having the above configuration will be explained using FIG. FIG. 2 is a time chart showing the operation of an embodiment of the present invention and a conventional memory power supply device, and is a time chart showing the operation of the circuits of FIGS. 1 and 3. In FIG.

In the figure, when the main power on switch is operated, the main power supply 4 is turned on, and the main power supply voltage rises from 0 [V] to 5 [V]. Next, when the main power supply 4 is supplied to each control circuit and the PDWN signal is released, the PDWN signal changes from 0 [V] to 5 [V]. PDWN signal is 0 [V]
In this case, power is supplied from the secondary battery 9 to the RAM memory. In other words, although the secondary battery 9 is in a discharged state, the PD
When the WN signal is switched to 5 [V] and the power source switching transistor TR17 is turned on, the secondary battery 9 is charged from the main power source 4 via the charging current limiting resistor R38. Next, when you operate the main power off switch, the PDW
The N signal changes from 5 [V] to 0 [V], and the PDWN signal is activated. When the PDWN signal is activated, the power supply switching transistor T
R1 7 is turned off, power is no longer supplied from the main power supply 4 to the backup power supply 3, and power is instead supplied to the backup power supply 3 from the secondary battery 9. In other words, the secondary battery 9 returns to the discharge state again. However, in the conventional memory power supply device shown in FIG. 3, as shown by the conventional backup power supply voltage in FIG. As a result, the voltage of the backup power supply temporarily dropped.

FIG. 2A shows the power supply backup area of the RAMIC, where the voltage of the secondary battery 9 is the voltage of the backup power supply 3. (B) is an area from the rise of the main power supply voltage until the PDWN signal for switching control between the main power supply 4 and the secondary battery 9, which is the auxiliary power supply, is released. In this region, the PDWN signal is 0 [V] and the backup power source is on the auxiliary power source side. However, in the conventional memory power supply device shown in FIG. , the c-MOS type IC5 becomes unstable due to the leakage current of the power supply switching transistor TR17,
The secondary battery 9, which is an auxiliary power source, was unable to supply the temporary increase in current consumption, and the voltage of the backup power source momentarily dropped, as in the conventional backup power source voltage shown in FIG.

Therefore, in the memory power supply device of this embodiment, as shown in FIG. By connecting the emitters and collectors of 11, and connecting the rising signal of the main power source 4 to the base, the power supply shortage that occurs in the region (B) is compensated for. That is, only when the main power supply 4 is on, the charging current limiting resistor R3 8 works, and when the main power supply 4 is off, by short-circuiting the charging current limiting resistor R3 8, the charging current limiting resistor R3 8 is activated. Reduces the internal resistance of the secondary battery 9 when viewed from the backup power supply 3 when off, that is, during backup,
We are increasing our power supply capacity.

In addition, the area (C) in FIG. 2 is when the main power supply 4 is on and the PDWN signal is released, and since the backup power supply 3 to the RAMIC is supplied from the main power supply 4, the voltage is 5 [V]. ]. In region (D), the PDWN signal is turned off, and then the main power supply 4 is turned off. In this area as well, in the conventional memory power supply device shown in FIG. 3, the voltage of the backup power supply drops. This is because even after the PDWN signal becomes valid and becomes 0 [V], there is a potential difference between the main power supply 4 and the secondary battery 9, and a leakage current from the emitter to the base of the power supply switching transistor TR17 causes the secondary This is because the battery 9 is being charged. Therefore, (B) is more important than (A) and (E).
) and (D), the voltage is slightly higher in the stable parts.

In the memory power supply device of this embodiment shown in FIG. 1 as well, when the main power supply 4 is on, the secondary battery 9 is charged by the main power supply 4 and the main power supply 4 is turned on.
When turned off, the secondary battery 9 switches from charging to discharging. Moreover, in this embodiment, when the main power source 4 is off, the secondary battery 9 is quickly switched from charging to discharging, and
By short-circuiting the charging current limiting resistor R3 8, the discharging of the secondary battery 9 is not hindered by the charging current limiting resistor R3 8, and moreover, a temporary shortage of power supply from the backup power source 3 occurs. Because there is no such thing,
A drop in the voltage of the backup power supply 3 can be prevented.

As described above, the memory power supply device of this embodiment has a main power supply 4 that supplies power to a memory circuit using non-volatile memory, and is charged by this main power supply 4, and is charged by the main power supply 4 when the main power supply 4 is turned off. A charging current is provided between the secondary battery 9, which is an auxiliary power supply that supplies power to the memory circuit in order to protect the memory circuit when the main power supply 4 and the secondary battery 9 (auxiliary power supply) a limiting resistor R3 8; a current limiting shorting transistor TR2 11 that short-circuits the charging current limiting resistor R3 8 when the main power source 4 is off;
When the main power supply 4 is on, the main power supply voltage is lowered to the auxiliary power supply voltage to protect the current limiting short-circuit transistor TR2 11, and when the main power supply 4 is off, the secondary battery 9 (auxiliary power supply voltage) is ) and a charge/discharge control circuit having a leakage current prevention diode 12 that prevents current from leaking from the main power source 4 to the main power source 4.

That is, the memory power supply device of this embodiment is charged by the main power supply 4 that supplies power to the memory circuit, and supplies power to the memory circuit in order to protect the memory circuit when the main power supply 4 is off. By limiting the charging current to the secondary battery 9 (auxiliary power supply) which supplies This reduces the load when power is supplied due to discharge of the secondary battery 9 (auxiliary power source).

Specifically, a charging current limiting resistor R38 of the charge/discharge control circuit is connected in series with the secondary battery 9 to prevent overcharging of the secondary battery 9 during charging. Also,
At the base of the current limiting short-circuit transistor TR2 11 whose output side is connected in parallel with the charging current limiting resistor R3 8,
By inputting a switching signal at the same time as the main power source 4 is turned on and off, the switching time delay is minimized and the charging current limiting resistor R38 is short-circuited during discharging. In this way, the charging current limiting resistor R38 of the charge/discharge control circuit is short-circuited at the same time as the main power source 4 is switched, and the impedance of the secondary battery 9 is controlled, thereby reducing the load that increases transiently when the main power source 4 is switched. do.

Therefore, overcharging of the secondary battery 9 (auxiliary power source) can be prevented, and when the backup power source that is the power source for the memory is switched from the secondary battery 9 (auxiliary power source) to the main power source 4, From secondary battery 9 (auxiliary power source)
Since the power supply capacity of the secondary battery 9 (auxiliary power source) does not decrease when switching to . As a result, stable power can always be supplied as a backup power source to the memory circuit.

Incidentally, in the above embodiment, the switching control signal for the current limiting short-circuiting transistor TR2 11 that short-circuits the charging current limiting resistor R3 8 was created using the main power source 4, but this signal is not used as the power source switching control signal. It may also be created from a PDWN signal or the like.

[0044]

As described above, the memory power supply device of the present invention includes a main power source, an auxiliary power source, and a charge/discharge control circuit, and is charged by the main power source that supplies power to the memory circuit. In order to protect the memory circuit when the main power supply is off, a charge/discharge control circuit limits the charging current to the auxiliary power supply that supplies power to the memory circuit, and reduces the load when power is supplied due to discharge of the auxiliary power supply. By reducing the power supply, it is possible to prevent overcharging of the auxiliary power supply, and when the backup power supply that is the memory power source switches from the auxiliary power supply to the main power supply, and when switching from the main power supply to the auxiliary power supply, the power supply of the auxiliary power supply Since the performance does not decrease, the power supply from the auxiliary power supply to the backup power supply does not become insufficient, and the voltage of the backup power supply does not drop, it is possible to always stably supply power as a backup power supply to the memory circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a memory power supply device according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of an embodiment of the present invention and a conventional memory power supply device.

FIG. 3(a) is a circuit diagram showing a conventional memory power supply device, and FIG. 3(b) is a time chart showing its operation.

FIGS. 4A to 4C are circuit diagrams showing the operation of a power supply switching transistor in a conventional memory power supply device.

[Fig. 5] Fig. 5 shows a C-MOS I of a memory power supply device.
FIG. 2 is a circuit diagram showing the inside of C.

6A to 6C are circuit diagrams showing the operation of a secondary battery when the main power supply is turned off in a conventional memory power supply device.

FIG. 7 is a circuit diagram showing a circuit using a transistor to short-circuit a charging current limiting resistor during discharging in another conventional memory power supply device.

FIG. 8 is a time chart showing the operation of the circuit in FIG. 7;

[Explanation of symbols]

1 PDWN signal input terminal 2 Pull-down resistor for level stabilization 3 Backup power supply 4 Main power supply 5 c-MOS type IC 6 Base current limiting resistor R1 7 Power supply switching transistor TR18 Charging current limiting resistor R3 9 Secondary battery 10 Secondary battery installation Terminal 11 Current limiting short-circuit transistor TR212
Leakage current prevention diode 13 Current limiting resistor

Claims (1)

[Claims] 1. A main power source that supplies power to a memory circuit using nonvolatile memory; and a main power source that is charged by the main power source and supplies power to the memory circuit to protect the memory circuit when the main power source is off. A power supply device for a memory, comprising: an auxiliary power supply; and a charge/discharge control circuit that limits a charging current to the auxiliary power supply and reduces a load when power is supplied due to discharge of the auxiliary power supply.