JPH04344459A - Acoustic receiving unit - Google Patents

Acoustic receiving unit

Info

Publication number
JPH04344459A
JPH04344459A JP3115819A JP11581991A JPH04344459A JP H04344459 A JPH04344459 A JP H04344459A JP 3115819 A JP3115819 A JP 3115819A JP 11581991 A JP11581991 A JP 11581991A JP H04344459 A JPH04344459 A JP H04344459A
Authority
JP
Japan
Prior art keywords
additions
signal
acoustic
signals
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3115819A
Other languages
Japanese (ja)
Inventor
Masahiro Koike
正浩 小池
Toshiyuki Sawa
敏之 澤
Shigeru Kajiyama
茂 梶山
Tsukasa Sasaki
佐々木 典
文信 ▲高▼橋
Fuminobu Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3115819A priority Critical patent/JPH04344459A/en
Publication of JPH04344459A publication Critical patent/JPH04344459A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance the S/N of received acoustic signals even if there is noise having regularity and/or noise which is difficult to separate using gates. CONSTITUTION:An acoustic receiving unit is comprised of a receiving element 1 and a receiver 2 for receiving acoustic signals, switches 4-6 for switching signal lines, delay circuits 7-9 for delaying received signals, memories 3, 10-12 for storing the received signals, an adding circuit 14 for adding (m+1) signals together, an addition time setting circuit 13 for setting the number m of times of the addition, and an outputter 15 for outputting the added signals. First, the receiver 2 is connected to each of the delay circuits 7-9 by the switches 4-6. The acoustic signals received by the receiving element 1 are stored in the memory 3 and the signals delayed by each delay circuit are stored in the memories 10-12. The (m+1) signals stored in the memories are added together by the adding circuit 14 and the result of the addition is output to the outputter 15.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、音響を用いて、構造物
等を非破壊で検査する装置,音響源等の位置や障害物を
検出する装置に係り、特に、受信した音響のSN比の向
上に好適な装置に関する。
[Industrial Application Field] The present invention relates to a device for nondestructively inspecting structures, etc., and a device for detecting the position of a sound source, etc. and obstacles using sound, and in particular, the present invention relates to a device for nondestructively inspecting structures, etc., using sound, and a device for detecting the position of a sound source, etc., and an obstacle. The present invention relates to a device suitable for improving.

【0002】0002

【従来の技術】SN比を向上させる従来の方法は、主に
次の二つの方法がある。
2. Description of the Related Art There are two main conventional methods for improving the signal-to-noise ratio.

【0003】発生時間及び発生強度が不規則なランダム
ノイズに対しては、音響を受信するセンサ(以下、受信
子と記す)を固定した状態で信号をm回受信し、そのm
個の信号を加算する。この場合、目的とする信号Sが常
に時間軸上で同じ時刻に受信されるため、m倍になる。 しかし、ランダムノイズNは常に同じ時刻に受信されな
いためにm回加算しても√m倍にしかならない。したが
って、SN比m/√m=√m倍になる(分析情報の自動
処理,日刊工業新聞,昭和45年)。他の方法は、ラン
ダムノイズと異なり、時間軸上で同じ時刻に受信される
信号ではあるが、目的としない信号を分離する方法であ
る。具体的には、時間軸上に目的とする信号のみが入る
ゲートを設け、このゲート内信号のみを取り出すことに
より、信号を分離する。これにより、SN比を向上でき
る。
[0003] For random noise with irregular generation time and generation intensity, a sensor that receives sound (hereinafter referred to as a receiver) is fixed and receives a signal m times, and the m
Add signals. In this case, the target signal S is always received at the same time on the time axis, so it is multiplied by m. However, since the random noise N is not always received at the same time, even if it is added m times, it will only be multiplied by √m. Therefore, the S/N ratio becomes m/√m=√m times (Automatic Processing of Analysis Information, Nikkan Kogyo Shimbun, 1970). Another method is to separate signals that are received at the same time on the time axis but are not of interest, unlike random noise. Specifically, the signals are separated by providing a gate on the time axis into which only the target signal enters and extracting only the signal inside the gate. Thereby, the SN ratio can be improved.

【0004】0004

【発明が解決しようとする課題】実際には、ランダムノ
イズではない規則性のあるノイズや、目的とする信号と
ゲートによる分離が困難な信号が存在する。また、それ
らが組み合わされた信号も存在する。ゲートによる信号
の分離が困難な場合には、信号同士が重なっている場合
や信号が時間軸上で移動する(すなわち、受信子と信号
源との距離が変化する)ために、はじめに分離できてい
たのが、目的とする信号がゲートから外れたり、また目
的以外の信号がゲート内に入り込んだりする場合が考え
られる。このような場合には、従来技術を適用してもS
N比の向上を図ることは困難である。
In reality, there are regular noises that are not random noises, and signals that are difficult to separate from a target signal using a gate. There are also signals that are a combination of these. If it is difficult to separate signals using a gate, it may be difficult to separate them in the first place because the signals overlap or because the signals move on the time axis (that is, the distance between the receiver and the signal source changes). However, it is conceivable that the desired signal may come out of the gate, or that a signal other than the desired signal may enter the gate. In such a case, even if the conventional technology is applied, S
It is difficult to improve the N ratio.

【0005】本発明の目的は、これらのノイズが存在し
た場合でもSN比を向上させる手段及び装置を提供する
ことにある。
An object of the present invention is to provide a means and apparatus for improving the SN ratio even in the presence of such noise.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するには
、受信子を固定した状態で受信した音響信号を、時間軸
上で任意の時間間隔ずつ遅らせ、または、早めて加算す
る。これにより、目的以外の信号Nの強度を減少でき、
ひいては、SN比を向上できる。
[Means for Solving the Problems] In order to solve the above problems, the acoustic signals received with the receiver fixed are delayed or advanced by arbitrary time intervals on the time axis and then added together. As a result, the strength of the non-target signal N can be reduced,
As a result, the SN ratio can be improved.

【0007】[0007]

【作用】周波数により音響強度の距離減衰の割合が異な
るため、受信子と音響源との距離により、受信される音
響信号の周波数分布が異なる。また、受信信号同士の重
なり合わせにより、受信信号の周波数分布が異なる。こ
のことは、時間軸上では、目的とする信号(以下、この
信号を単に信号Sと記す)の周期と、目的以外の信号(
以下、この信号をノイズNと記す)の周期とが異なるこ
とになる。そのため、受信した信号を、時間軸上で任意
の時間間隔ずつ移動させて加算すると、信号とノイズの
一周期分加算された時に、各々の受信強度が零になる。 従って、ノイズが一周期分加算された時に、ノイズの強
度が零となるためSN比が無限大となり、SN比を向上
できる。
[Operation] Since the distance attenuation rate of acoustic intensity differs depending on the frequency, the frequency distribution of the received acoustic signal varies depending on the distance between the receiver and the acoustic source. Furthermore, the frequency distribution of the received signals differs due to the overlap between the received signals. This means that on the time axis, the period of the target signal (hereinafter, this signal is simply referred to as signal S) and the period of the non-target signal (
Hereinafter, this signal will be referred to as noise N). Therefore, when the received signals are moved by arbitrary time intervals on the time axis and added, the received strength of each signal becomes zero when one cycle of the signal and the noise are added. Therefore, when one cycle of noise is added, the intensity of the noise becomes zero, so the S/N ratio becomes infinite, and the S/N ratio can be improved.

【0008】以下、時間軸上で任意の時間間隔ずつ移動
させて加算した場合の加算回数とSN比との関係につい
て詳細に説明する。
[0008] Hereinafter, the relationship between the number of additions and the S/N ratio when the signals are added by moving at arbitrary time intervals on the time axis will be explained in detail.

【0009】図7に受信した音響信号の模式図を示す。FIG. 7 shows a schematic diagram of the received acoustic signal.

【0010】受信信号を信号SとノイズNに分けて考え
ると、信号電圧Es(t),ノイズ電圧En(t)は式
数1,数2となる。
When the received signal is divided into signal S and noise N, the signal voltage Es(t) and the noise voltage En(t) are expressed by Equations 1 and 2.

【0011】[0011]

【数1】[Math 1]

【0012】0012

【数2】[Math 2]

【0013】但し、As は信号の振幅、An はノイ
ズの振幅、Ts は信号の周期そしてTnはノイズの周
期である。
##EQU1## where As is the amplitude of the signal, An is the amplitude of the noise, Ts is the period of the signal, and Tn is the period of the noise.

【0014】これらの信号を時間軸上でΔtずつ移動し
て加算すると、式数1,数2は、数3,数4になる。
When these signals are moved by Δt on the time axis and added, Equations 1 and 2 become Equations 3 and 4.

【0015】[0015]

【数3】[Math 3]

【0016】[0016]

【数4】[Math 4]

【0017】但し、mは加算回数である。すなわち、m
=0では、受信信号そのままであり、m=1では、受信
信号と、その信号をΔt時間移動した信号とを加算した
信号が、式数3,数4の結果である。
[0017] However, m is the number of additions. That is, m
When m = 0, the received signal is the same as it is, and when m = 1, the result of Equations 3 and 4 is a signal obtained by adding the received signal and a signal obtained by shifting the signal by a time Δt.

【0018】実際に、信号SとノイズNとの関係は、二
つに大別できる。一つは、信号SとノイズNとが重なっ
ている場合(図8(a))であり、二つめは、信号Sと
ノイズNとが時間軸上で重なり合っていない場合(図8
(b))である。この二つの受信信号E(t)は、式数
5,数6となる。
In fact, the relationship between the signal S and the noise N can be roughly divided into two. One is when the signal S and the noise N overlap (Fig. 8(a)), and the second is when the signal S and the noise N do not overlap on the time axis (Fig. 8(a)).
(b)). These two received signals E(t) are expressed by Equations 5 and 6.

【0019】[0019]

【数5】[Math 5]

【0020】[0020]

【数6】[Math 6]

【0021】したがって、式数5,数6に対応するSN
比は、受信信号E(t)の最大値EmaxをノイズEn
(t)の最大値Enmaxで除した値である。
Therefore, SN corresponding to Equations 5 and 6
The ratio is the maximum value Emax of the received signal E(t) to the noise En
This is the value divided by the maximum value Enmax of (t).

【0022】[0022]

【数7】[Math 7]

【0023】[0023]

【数8】[Math. 8]

【0024】加算回数とこのSN比との関係を模式的に
示したのが図9である。
FIG. 9 schematically shows the relationship between the number of additions and the SN ratio.

【0025】具体的に、As=Anとして計算した例を
、図10及び図11に示す。図10,11中の四角は、
周期Ts,TnをΔtで規格化した値が(Ts/Δt=
20,Tn/Δt=19)の場合の例であり、プラスは
、(Ts/Δt=20,Tn/Δt=21)の例である
。加算回数mが、(Tw/Δt)−1の時、Esmax
=0となるためSN比は最小になり、(Tn/Δt)−
1の時、Enmax=0となるため、SN比は無限大に
なる。
Specifically, an example of calculation with As=An is shown in FIGS. 10 and 11. The squares in Figures 10 and 11 are
The value obtained by normalizing the periods Ts and Tn by Δt is (Ts/Δt=
20, Tn/Δt=19), and plus is an example of (Ts/Δt=20, Tn/Δt=21). When the number of additions m is (Tw/Δt)-1, Esmax
= 0, so the SN ratio becomes minimum, and (Tn/Δt)−
When it is 1, Enmax=0, so the SN ratio becomes infinite.

【0026】この関係を実験で検討した結果が図12で
ある。図12中の四角は、実験値であり、菱形は、(T
s/Δt=17,Tn/Δt=16)とした場合の計算
結果である。実験は、図13に示すように、周波数2.
25MHz の表面波210を用いて、溶接部202か
らの反射波を処理したものである。実験値と計算値との
差は、実験が、Δt=0.033μsであるのに対し、
Ts=0.567μs,Tn=0.533μs であり
、Δtで割り切れないためである。この場合でも信号の
加算により、実験結果において、SN比が35%向上し
た。
FIG. 12 shows the results of an experimental study of this relationship. The squares in FIG. 12 are experimental values, and the diamonds are (T
s/Δt=17, Tn/Δt=16). In the experiment, as shown in FIG. 13, frequency 2.
The reflected waves from the welded portion 202 are processed using a 25 MHz surface wave 210. The difference between the experimental value and the calculated value is Δt=0.033 μs in the experiment, whereas
This is because Ts=0.567 μs and Tn=0.533 μs, which are not divisible by Δt. Even in this case, the signal-to-noise ratio was improved by 35% in experimental results by signal addition.

【0027】[0027]

【実施例】以下、本発明を実施例を用いて説明する。EXAMPLES The present invention will be explained below using examples.

【0028】図1は、本発明の第一の実施例のブロック
図である。図1において、1は受信子、2は受信器、3
,10〜12はメモリ、4〜6は切替器、7〜9は遅延
回路、13は加算回数設定回路、14は加算回路、15
は出力器である。
FIG. 1 is a block diagram of a first embodiment of the present invention. In FIG. 1, 1 is a receiver, 2 is a receiver, 3
, 10 to 12 are memories, 4 to 6 are switchers, 7 to 9 are delay circuits, 13 is an addition number setting circuit, 14 is an addition circuit, 15
is an output device.

【0029】次に、動作について図1,図2を用いて説
明する。あらかじめ、加算回数設定回路13に加算回数
mを設定し、メモリの内容をクリアしておく。設定回数
mが零のときは、切替器4〜切替器6で受信器2と遅延
回路7〜遅延回路9との接続を切り離す。加算回数mが
零以外の正の整数のときは、切替器4から順にm個の切
替器において、受信器2と遅延回路7〜遅延回路9とを
接続する。又、遅延回路7〜遅延回路9では各々遅延時
間Δt1〜Δtmを設定しておく。例えば、各々遅延時
間を、Δt2=2×Δt1,Δt3=3×Δt1……Δ
tm=m×Δt1のように設定する。この状況で、受信
子1で図2(a)に示す音響信号を受信した場合には、
メモリ3にはaの信号が記憶される。同時に、受信信号
aは切替器4〜切替器6を経由して遅延回路7〜遅延回
路9に送られる。遅延回路7〜遅延回路9では設定して
おいた遅延時間だけ受信信号aを遅延させる。したがっ
て、メモリ10には、図2(b)に示すように、受信信
号aをΔt1 時間だけ遅延させた信号を記憶する。同
様にメモリ11に記憶される信号は図2(c)に、そし
て、メモリ12に記憶される信号は図2(d)に示す信
号である。これらメモリ3〜メモリ12に記憶された信
号は、加算回路14に送られて、加算される。この加算
により、SN比が向上した受信信号が出力器15に出力
される。
Next, the operation will be explained using FIGS. 1 and 2. In advance, the number of additions m is set in the addition number setting circuit 13 and the contents of the memory are cleared. When the set number of times m is zero, the switches 4 to 6 disconnect the receiver 2 from the delay circuits 7 to 9. When the number of additions m is a positive integer other than zero, the receiver 2 and the delay circuits 7 to 9 are connected in m switchers in order from the switch 4. Further, delay times Δt1 to Δtm are set in the delay circuits 7 to 9, respectively. For example, each delay time is Δt2=2×Δt1, Δt3=3×Δt1...Δ
It is set as tm=m×Δt1. In this situation, when receiver 1 receives the acoustic signal shown in FIG. 2(a),
The memory 3 stores the signal a. At the same time, the received signal a is sent to the delay circuits 7 to 9 via the switches 4 to 6. The delay circuits 7 to 9 delay the received signal a by a preset delay time. Therefore, the memory 10 stores a signal obtained by delaying the received signal a by Δt1 time, as shown in FIG. 2(b). Similarly, the signals stored in the memory 11 are shown in FIG. 2(c), and the signals stored in the memory 12 are shown in FIG. 2(d). The signals stored in these memories 3 to 12 are sent to an adding circuit 14 and added. As a result of this addition, a received signal with an improved SN ratio is output to the output device 15.

【0030】図1の実施例では遅延時間をΔt1 の整
数倍にしたが、これに限るものではない。また、m個の
切替器を切替器4から順に選択したが、どのm個を選択
しても良い。
In the embodiment shown in FIG. 1, the delay time is set to an integral multiple of Δt1, but the delay time is not limited to this. Further, although m switchers are selected in order from switch 4, any m switchers may be selected.

【0031】つぎに、第二の実施例を、図3を用いて説
明する。図3の構成は、16〜18は切替器、19は加
算回数検出回路、20は比較器である。つぎに、図3の
動作について説明する。あらかじめ、加算回数設定回路
13に加算回数mを設定し、メモリの内容,加算回数検
出回路19の検出回数をクリアする。切替器16は受信
器2とメモリ3とを、切替器18は受信器2と遅延回路
7とを接続する。加算回数mが零の場合には、加算回数
mと加算回数検出回路19の検出回数とが同じ(零)な
ので、切替器17はメモリ3と出力器15とを接続する
。従って、この場合には、受信信号がそのまま出力器1
5より出力される。加算回数検出回路で加算回数mが零
以外の正の整数の場合について考える。切替器17は、
メモリ16と加算回路14とを接続する。受信子1で受
信した音響信号は、受信器2,切替器16を経由してメ
モリ3に記憶される。同時に、受信信号は、切替器18
を経由して遅延回路7に送られる。受信信号が切替器1
6を通過後、切替器16は加算回路14とメモリ3との
接続に切替る。また、遅延回路7では受信信号を、設定
されている遅延時間Δtだけ遅らせ、メモリ10に送り
、メモリ10ではこの信号を記憶する。メモリ10に記
憶された信号は、加算回数検出回路19に送られると同
時に、切替器18を経由して遅延回路7に再び送られる
。遅延回路7でさらにΔtだけ時間を遅らせた信号(受
信信号を(2×Δt)時間遅らせた信号)をメモリ10
に記憶される。加算回数検出回路19ではこの回路を信
号が通過する回数により加算回数を求め、比較器20に
検出した加算回数を送る。加算回路14では、メモリ3
の内容とメモリ10の内容とを加算し、その結果を切替
器16を経由してメモリ3に記憶する。比較器20にお
いて、加算回数設定回路13で設定した加算回数mと加
算回数検出回路19で検出した回数とを比較し、両者の
値が違っていれば何もしない。もし、同じであれば、切
替器17の接続をメモリ3と出力器15との接続に切替
る。これにより、SN比が向上した受信信号が出力器1
5に出力される。
Next, a second embodiment will be explained using FIG. 3. In the configuration of FIG. 3, 16 to 18 are switchers, 19 is an addition count detection circuit, and 20 is a comparator. Next, the operation of FIG. 3 will be explained. In advance, the number of additions m is set in the number of additions setting circuit 13, and the contents of the memory and the number of times detected by the number of additions detection circuit 19 are cleared. The switch 16 connects the receiver 2 and the memory 3, and the switch 18 connects the receiver 2 and the delay circuit 7. When the number of additions m is zero, the number of additions m and the number of detections by the addition number detection circuit 19 are the same (zero), so the switch 17 connects the memory 3 and the output device 15. Therefore, in this case, the received signal is sent directly to the output device 1.
Output from 5. Consider the case where the number of additions m in the addition number detection circuit is a positive integer other than zero. The switch 17 is
The memory 16 and the adder circuit 14 are connected. The acoustic signal received by the receiver 1 is stored in the memory 3 via the receiver 2 and the switch 16. At the same time, the received signal is
The signal is sent to the delay circuit 7 via. Received signal is switch 1
6, the switch 16 switches the connection between the adder circuit 14 and the memory 3. Further, the delay circuit 7 delays the received signal by a set delay time Δt, and sends it to the memory 10, which stores this signal. The signal stored in the memory 10 is sent to the addition count detection circuit 19 and at the same time is sent again to the delay circuit 7 via the switch 18. A signal further delayed by Δt in the delay circuit 7 (a signal obtained by delaying the received signal by (2×Δt) time) is sent to the memory 10.
is memorized. The number of additions detection circuit 19 calculates the number of additions based on the number of times the signal passes through this circuit, and sends the detected number of additions to the comparator 20. In the adder circuit 14, the memory 3
and the contents of the memory 10, and the result is stored in the memory 3 via the switch 16. The comparator 20 compares the number of additions m set by the number of additions setting circuit 13 with the number detected by the number of additions detection circuit 19, and if the two values are different, nothing is done. If they are the same, the connection of the switch 17 is switched to the connection between the memory 3 and the output device 15. As a result, the received signal with improved S/N ratio is transmitted to the output device 1.
5 is output.

【0032】図3の実施例では、切替器,遅延回路,メ
モリ等の個数を減少できる利点がある。
The embodiment of FIG. 3 has the advantage that the number of switches, delay circuits, memories, etc. can be reduced.

【0033】上記二つの実施例は、受信子1で受信した
一個の音響信号を用いた場合である。図4は、第三の実
施例の概略図を示し、m個の音響信号を用いる場合であ
る。図4の構成は、21は遅延回路である。つぎに、図
4の動作について説明する。あらかじめ、加算回数設定
回路13に加算回数mを設定し、メモリの内容、加算回
数検出器19の検出回数をクリアする。切替器16は受
信器2とメモリ3とを接続し、切替器18は受信器2と
メモリ10との接続を切り離す。加算回数設定回路13
で加算回数mが零の場合には、加算回数mと加算回数検
出回路19の検出回数とが同じ(零)なので、切替器1
7はメモリ3と出力器15とを接続する。したがって、
この場合には、受信信号がそのまま出力器15より出力
される。つぎに、加算回数設定回路13で加算回数をm
とした場合について考える。切替器17は、メモリ16
と加算回路14とを接続する。受信子1で受信した音響
信号は、受信器2,切替器16を経由してメモリ3に記
憶される。この後、切替器16は、遅延回路21とメモ
リ3との接続に切り替える。メモリ3に記憶した信号は
、切替器17を経由して加算回路14に送られる。加算
回路14では、メモリ3の信号とメモリ10(この段階
ではまだ全て零)とを加算し、加算信号を遅延回路21
に送る。遅延回路21では、加算回路14の出力信号を
、設定したΔt時間だけ遅延させて、切替器16を経由
してメモリ3に記憶する。また、加算回路14では、加
算を終えると同時に加算終了信号を切替器18に送る。 一方、比較器20では、加算回数設定回路13で設定し
た加算回数mと加算回数検出回路19で検出した回数(
この場合零)とを比較する。両者の値が異なっていれば
、切替器17の接続をそのままにする。切替器18では
、加算回路14からの加算終了信号を受けると、受信器
2とメモリ10とを接続し、新たに受信した音響信号を
メモリ10に送る。つぎに、加算回数検出回路19の検
出回数に1を加えて、メモリ10の内容を加算回路14
に送る。加算回路14では、メモリ3の内容(1回前に
加算してΔt時間遅らせた信号)と加算する。その結果
を遅延回路21に送ると同時に、加算終了信号を受信器
2に送る。比較器20では、加算回数設定回路13で設
定した加算回数mと加算回数検出回路19で検出した回
数とを比較する。両者の値が異なっていれば、切替器1
7の接続をそのままにする。以上の動作を、加算回数検
出回路19で検出した回数が、加算回数設定回路13に
設定した加算回数mに一致するまで繰り返す。もし、両
者の値が一致した場合には、切替器17の接続をメモリ
3と出力器15との接続に切替る。これにより、SN比
が向上した受信波形信号出力器15に出力される。
The above two embodiments are cases in which one acoustic signal received by the receiver 1 is used. FIG. 4 shows a schematic diagram of a third embodiment, in which m acoustic signals are used. In the configuration of FIG. 4, 21 is a delay circuit. Next, the operation in FIG. 4 will be explained. In advance, the number of additions m is set in the number of additions setting circuit 13, and the contents of the memory and the number of detections by the number of additions detector 19 are cleared. The switch 16 connects the receiver 2 and the memory 3, and the switch 18 disconnects the receiver 2 and the memory 10. Addition count setting circuit 13
If the number of additions m is zero, the number of additions m and the number of detections by the addition number detection circuit 19 are the same (zero), so the switch 1
7 connects the memory 3 and the output device 15. therefore,
In this case, the received signal is output from the output device 15 as it is. Next, the addition number setting circuit 13 sets the number of additions to m.
Consider the case where The switch 17 is connected to the memory 16
and the adder circuit 14 are connected. The acoustic signal received by the receiver 1 is stored in the memory 3 via the receiver 2 and the switch 16. Thereafter, the switch 16 switches the connection between the delay circuit 21 and the memory 3. The signal stored in the memory 3 is sent to the adder circuit 14 via the switch 17. The adder circuit 14 adds the signal in the memory 3 and the memory 10 (all zeros at this stage), and sends the added signal to the delay circuit 21.
send to In the delay circuit 21, the output signal of the adder circuit 14 is delayed by a set time Δt and stored in the memory 3 via the switch 16. Further, the addition circuit 14 sends an addition completion signal to the switch 18 at the same time as the addition is completed. On the other hand, in the comparator 20, the number of additions m set by the number of additions setting circuit 13 and the number of additions m detected by the number of additions detecting circuit 19 (
(in this case zero). If the two values are different, the connection of the switch 17 is left as is. When the switch 18 receives the addition end signal from the addition circuit 14, it connects the receiver 2 and the memory 10, and sends the newly received acoustic signal to the memory 10. Next, 1 is added to the number of detections by the addition number detection circuit 19, and the contents of the memory 10 are transferred to the addition circuit 14.
send to The adder circuit 14 adds the signal to the contents of the memory 3 (the signal added once before and delayed by Δt time). At the same time as sending the result to the delay circuit 21, an addition end signal is sent to the receiver 2. The comparator 20 compares the number of additions m set by the number of additions setting circuit 13 with the number detected by the number of additions detection circuit 19. If the two values are different, switch 1
Leave connection 7 as is. The above operation is repeated until the number of additions detected by the addition number detection circuit 19 matches the number of additions m set in the addition number setting circuit 13. If the two values match, the connection of the switch 17 is switched to the connection between the memory 3 and the output device 15. As a result, the received waveform signal is output to the received waveform signal output device 15 with an improved SN ratio.

【0034】図4の実施例では、受信した時間が異なる
(m+1)個の受信信号を加算するため、発生時間や発
生強度が不規則なランダムノイズを確実に1/√(m+
1)にできる利点がある。
In the embodiment shown in FIG. 4, since (m+1) received signals having different reception times are added, random noise with irregular occurrence times and occurrence strengths can be reliably reduced to 1/√(m+
1) has the advantage of being possible.

【0035】上記の実施例では、遅延回路を用いて受信
した信号を遅らせて加算していたが、受信信号をΔt時
間早くして加算しても同じである。
In the above embodiment, the received signals are delayed and added using a delay circuit, but the same result can be obtained even if the received signals are advanced by Δt and added.

【0036】また、第一,第二の実施例でランダムノイ
ズを除去するために、図5に示すランダムノイズ除去回
路101を設けて、ランダムノイズを除去した信号をm
回加算することも可能である。ランダムノイズ除去回路
101は受信器2の直後に設置し、その動作はつぎの通
りである。あらかじめ、加算回数設定回路107に加算
回数j(加算回数mとは異なる)を設定し、メモリの内
容、加算回数検出器の検出回数をクリアする。切替器1
03は加算回路102とメモリ104とを接続する。受
信した信号を加算回路102でメモリ104の内容と加
算しその結果を、メモリ104に記憶する。加算回路1
02での加算を終えたならば、加算終了信号を受信器2
に送り、再び受信する。比較器106では加算回数設定
回路107で設定した回数jと加算回数検出回路105
で検出した回数とを比較し、両者の値が同じになるまで
加算を繰り返す。両者の値が同じになったならば、切替
器103により、加算回路102を、第一,第二の実施
例の受信器2の直後の信号線に接続する。
In order to remove random noise in the first and second embodiments, a random noise removal circuit 101 shown in FIG.
It is also possible to add times. The random noise removal circuit 101 is installed immediately after the receiver 2, and its operation is as follows. In advance, an addition number j (different from the addition number m) is set in the addition number setting circuit 107, and the contents of the memory and the detection number of the addition number detector are cleared. Switcher 1
03 connects the adder circuit 102 and the memory 104. The received signal is added to the contents of memory 104 by addition circuit 102, and the result is stored in memory 104. Addition circuit 1
When the addition at step 02 is completed, the addition end signal is sent to the receiver 2.
and receive it again. The comparator 106 calculates the number j set by the addition number setting circuit 107 and the addition number detection circuit 105.
Compare the number of times detected with , and repeat the addition until both values are the same. When both values become the same, the switch 103 connects the adder circuit 102 to the signal line immediately after the receiver 2 of the first and second embodiments.

【0037】図6は第四の実施例の概略構成図である。 図6は、前述の実施例で示した音響受信装置を備えた、
音響源位置検出装置である。201は試験片、202は
音響源(溶接部)、203は送,受信子、204は送信
器、205は音響受信装置、206は検波器、207は
伝播距離測定回路、208は音響源位置検出回路、20
9は表示器である。次に、図6の動作について説明する
。送信器204の信号に基づいて送,受信子から音響信
号(表面波)210を音響源(溶接部)202に送信す
る。音響信号(表面波)210は、溶接部202で反射
されて、送,受信子202に戻り、受信される。受信さ
れた音響信号は、音響受信装置505でSN比を向上し
、検波器206に送られる。検波された音響信号は、伝
播距離測定装置207に送られ、伝播距離測定装置20
7では送信から受信までの伝播距離を求め、その結果を
音響位置検出回路208に送る。音響位置検出回路20
8では、伝播距離から音響位置を検出し、その結果を表
示器209に送り、表示される。
FIG. 6 is a schematic diagram of the fourth embodiment. FIG. 6 shows a system equipped with the acoustic receiving device shown in the above embodiment.
This is a sound source position detection device. 201 is a test piece, 202 is an acoustic source (welded part), 203 is a transmitter and receiver, 204 is a transmitter, 205 is an acoustic receiver, 206 is a detector, 207 is a propagation distance measuring circuit, and 208 is an acoustic source position detection circuit, 20
9 is a display. Next, the operation in FIG. 6 will be explained. It transmits based on a signal from a transmitter 204, and an acoustic signal (surface wave) 210 is transmitted from a receiver to an acoustic source (welding part) 202. The acoustic signal (surface wave) 210 is reflected by the welding part 202, returns to the transmitter/receiver 202, and is received. The received acoustic signal has an S/N ratio improved by an acoustic receiving device 505 and is sent to a detector 206. The detected acoustic signal is sent to the propagation distance measuring device 207, and the propagation distance measuring device 20
In step 7, the propagation distance from transmission to reception is determined and the result is sent to the acoustic position detection circuit 208. Acoustic position detection circuit 20
8, the acoustic position is detected from the propagation distance, and the result is sent to the display 209 and displayed.

【0038】[0038]

【発明の効果】本発明によれば、規則性のあるノイズや
目的としない信号(ノイズN)が存在する場合にも、受
信信号を時間軸上でシフトさせて加算することにより、
このノイズNの強度を小さくすることができるので、目
的とする信号SとノイズNとの比であるSN比を向上す
ることができる。例えば、周波数2.25MHz の表
面波を用いて、溶接部からの反射波に適用した場合には
、SN比が35%向上した。
According to the present invention, even when regular noise or unintended signals (noise N) are present, by shifting the received signals on the time axis and adding them,
Since the intensity of this noise N can be reduced, the SN ratio, which is the ratio between the target signal S and the noise N, can be improved. For example, when a surface wave with a frequency of 2.25 MHz was applied to a reflected wave from a weld, the S/N ratio was improved by 35%.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例のブロック図。FIG. 1 is a block diagram of one embodiment of the present invention.

【図2】信号波形の説明図。FIG. 2 is an explanatory diagram of signal waveforms.

【図3】本発明の第二の実施例のブロック図。FIG. 3 is a block diagram of a second embodiment of the invention.

【図4】本発明の第三の実施例のブロック図。FIG. 4 is a block diagram of a third embodiment of the present invention.

【図5】ランダムノイズ除去回路のブロック図。FIG. 5 is a block diagram of a random noise removal circuit.

【図6】音響受信装置を備えた音響源位置検出装置のブ
ロック図。
FIG. 6 is a block diagram of a sound source position detection device including a sound receiving device.

【図7】受信した音響信号の模式図。FIG. 7 is a schematic diagram of a received acoustic signal.

【図8】信号とノイズとの関係を示すタイミングチャー
ト。
FIG. 8 is a timing chart showing the relationship between signals and noise.

【図9】加算回数とSN比との関係の特性図。FIG. 9 is a characteristic diagram of the relationship between the number of additions and the SN ratio.

【図10】加算回数とSN比との関係の計算例を示す説
明図。
FIG. 10 is an explanatory diagram showing a calculation example of the relationship between the number of additions and the SN ratio.

【図11】加算回数とSN比との関係の計算例を示す説
明図。
FIG. 11 is an explanatory diagram showing a calculation example of the relationship between the number of additions and the SN ratio.

【図12】加算回数とSN比との関係の実験結果の一例
を示す説明図。
FIG. 12 is an explanatory diagram showing an example of experimental results regarding the relationship between the number of additions and the SN ratio.

【図13】実験体系の説明図。FIG. 13 is an explanatory diagram of the experimental system.

【符号の説明】[Explanation of symbols]

1…受信子、2…受信器、3,10〜12…メモリ、4
〜6…切替器、7〜9…遅延回路、13…加算回数設定
回路、14…加算回路、15…出力器。
1...Receiver, 2...Receiver, 3, 10-12...Memory, 4
~6...Switcher, 7~9...Delay circuit, 13...Addition count setting circuit, 14...Addition circuit, 15...Output device.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】音響信号を受信する受信子と受信器を備え
、受信した音響信号を出力する音響受信装置において、
前記受信した音響信号を任意の時間だけシフトする手段
と、複数個の前記音響信号を加算する手段とを備えたこ
とを特徴とする音響受信装置。
Claim 1: An acoustic receiving device comprising a receiver and a receiver for receiving an acoustic signal, and outputting the received acoustic signal,
An acoustic receiving device comprising: means for shifting the received acoustic signal by an arbitrary amount of time; and means for adding a plurality of the acoustic signals.
【請求項2】請求項1において、前記受信した音響信号
を分配する切り替え手段と、前記切り替え手段を選択す
る加算回数設定手段と、前記音響信号を記憶するメモリ
とを備えた音響受信装置。
2. The acoustic receiving device according to claim 1, comprising switching means for distributing the received acoustic signal, addition number setting means for selecting the switching means, and a memory for storing the acoustic signal.
【請求項3】請求項1において、前記音響信号の流れを
切り替える切り替え手段と、加算回数を検出する手段と
、加算回数を設定する手段と、前記加算回数を設定する
手段で設定した加算回数と前記加算回数を検出する手段
で検出した加算回数とを比較する手段と、前記音響信号
を記憶するメモリとを備えた音響受信装置。
3. In claim 1, a switching means for switching the flow of the acoustic signal, a means for detecting the number of additions, a means for setting the number of additions, and a number of additions set by the means for setting the number of additions. An acoustic receiving device comprising means for comparing the number of additions detected by the means for detecting the number of additions, and a memory for storing the acoustic signal.
【請求項4】請求項1において、前記音響信号の流れを
切り替える切り替え手段と、前記音響信号を加算する手
段からの加算終了信号に基づいて音響信号を通過させる
切り替え手段と、前記加算回数を検出する手段と、前記
加算回数を設定する手段と、前記加算回数を設定する手
段で設定した加算回数と前記加算回数を検出する手段で
検出した加算回数とを比較する手段と、前記音響信号を
記憶するメモリとを備えた音響受信装置。
4. According to claim 1, switching means for switching the flow of the acoustic signal, switching means for passing the acoustic signal based on an addition completion signal from the means for adding the acoustic signal, and detecting the number of additions. means for setting the number of additions, means for comparing the number of additions set by the means for setting the number of additions and the number of additions detected by the means for detecting the number of additions, and storing the acoustic signal. An acoustic receiving device comprising a memory for
【請求項5】請求項1ないし4の音響受信装置を備えた
音響源位置検出装置。
5. A sound source position detection device comprising the sound receiving device according to claim 1.
JP3115819A 1991-05-21 1991-05-21 Acoustic receiving unit Pending JPH04344459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3115819A JPH04344459A (en) 1991-05-21 1991-05-21 Acoustic receiving unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3115819A JPH04344459A (en) 1991-05-21 1991-05-21 Acoustic receiving unit

Publications (1)

Publication Number Publication Date
JPH04344459A true JPH04344459A (en) 1992-12-01

Family

ID=14671892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3115819A Pending JPH04344459A (en) 1991-05-21 1991-05-21 Acoustic receiving unit

Country Status (1)

Country Link
JP (1) JPH04344459A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013205287A (en) * 2012-03-29 2013-10-07 Mitsui Eng & Shipbuild Co Ltd Defect inspection device and defect inspection method
JP2014173939A (en) * 2013-03-07 2014-09-22 Hitachi Power Solutions Co Ltd Ultrasonic flaw detection method and ultrasonic flaw detection device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013205287A (en) * 2012-03-29 2013-10-07 Mitsui Eng & Shipbuild Co Ltd Defect inspection device and defect inspection method
JP2014173939A (en) * 2013-03-07 2014-09-22 Hitachi Power Solutions Co Ltd Ultrasonic flaw detection method and ultrasonic flaw detection device

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