JPH04343506A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To eliminate the necessity of a large capacity capacitor for removing DC voltage gain in a convensional BTL type amplifier circuit and to attain IC formation. CONSTITUTION:A signal inputted from a signal source 18 is amplified by a transistor(TR) 12 and the amplified signal is inputted to the base of a TR 7. The input voltage V1 of the amplified signal is equal to the voltage level VIN of the input signal. The signal concerned is amplified by a differential amplifier including TRs 7, 8, an in-phase signal is outputted to the collector of the TR 8 and a reverse phase signal is outputted to the collector of the TR 7. When the resistance values or resistors 20, 23, 24 are defined as the same value, the voltage levels of these output signals are respectively VIN and -VIN. The in- phase signal and the reverse phase signal are respectively inputted and amplified to/by negative feedback amplifiers 26, 27 and outputted to output terminals 103, 104. By the way, the input side bias voltage of said differential amplifier is set up by setting up a power supply terminal reference potential.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit.

0002

[Prior Art] Conventionally, so-called BTL (BRIDGE T
In an amplifier circuit using the IED LOAD method, two sets of amplifiers are used, the outputs of each amplifier are driven so that the phases of the signals are opposite to each other, and a load is connected between the output terminals. This provides the load with twice the output voltage of a single amplifier. Therefore, if the load impedance is the same, it is possible to output four times as much power as a single amplifier.

FIG. 2 is a circuit diagram showing an example of a conventional BTL type amplifier circuit. In FIG. 2, a signal input from a signal source 61 through input terminals 106 and 107 is transmitted to a PNP transistor 40 and a diode 37.
The DC level is shifted by PNP transistor 3.
The signal transmitted to the base of PNP 5 and amplified by a differential amplifier including PNP transistors 35 and 36 is transmitted to the base of PNP
It is output in the same phase to the collector of the transistor 36, and P
The signal is output to the collector of the NP transistor 35 in reverse phase. Further, the in-phase output signal is input to the negative feedback amplifier 56 via the PNP transistor 46 and the diode 45, amplified, and outputted to the output terminal 108, and the opposite-phase output signal is input to the negative feedback amplifier 56 via the PNP transistor 46 and the diode 45. is input to the negative feedback amplifier 57 via the diode 48, amplified, and output to the output terminal 109. in this case,
Resistors 41 and 4 serve as the output load of the input stage differential amplifier.
2 are set to the same resistance value, and the feedback resistance values of resistors 58 and 59 are set so that the voltage gains of feedback amplifiers 56 and 57 are the same, output terminals 108 and 109 have the same level and opposite phase, respectively. A signal is output, thereby providing four times as much signal power to the load 62 as compared to a single amplifier.

Note that the constant current sources 50 and 51 apply a DC bias voltage (
In addition, capacitors 52 and 53 act to prevent negative feedback amplifiers 56 and 57 from having a DC voltage gain.

[0005]

[Problem to be solved by the invention] The above-mentioned conventional BTL
In amplifier circuits based on this method, in order to input signals based on the ground terminal, the DC voltage (
Normally, the voltage (1/2 of the power supply voltage) is set by utilizing the voltage increase caused by flowing a DC current through a feedback resistor, and it is necessary to remove the DC voltage gain of the negative feedback amplifier. For this reason, as mentioned above, the use of a capacitor is essential, and this capacitor not only limits the frequency characteristics of the amplifier, especially in the low frequency region, but also makes it difficult to integrate the amplifier circuit into an IC. However, since the capacitance value of the capacitor is large, the size of the capacitor is also large, which is a major obstacle to miniaturization and cost reduction of ICs.

[0006]

[Means for Solving the Problems] The amplifier circuit of the present invention includes a differential amplifier at the front stage, inputs a pair of output voltages from the differential amplifier at the rear stage, and outputs in-phase and anti-phase voltages, respectively. an amplifier circuit comprising a pair of negative feedback amplifiers, the first and second PNs forming the differential amplifier;
first and second constant current sources connected respectively between the P transistor, the collectors of the first and second PNP transistors, and a ground terminal indicating a reference potential on the low potential side; first and second diodes connected between the bases of the first and second PNP transistors and a reference voltage source on the high potential side, respectively; the bases of the first and second PNP transistors; A first NPN transistor/third PNP transistor, a second NPN transistor/fourth PNP transistor, and a second NPN transistor/fourth PNP transistor inserted and connected as an amplifier circuit between a ground terminal indicating a reference potential on the low potential side, respectively; The first and second PNP transistors input the output voltages of the collectors of the first and second PNP transistors to the positive-phase input terminals, amplify them, and feed back the respective output voltages to the negative-phase input terminals via the feedback resistors. With respect to the second negative feedback amplifier, the positive phase side input terminal and the negative phase side input terminal of the first and second negative feedback amplifiers,
A constant voltage source that supplies a reference voltage via a resistor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a signal source 18,
PNP transistors 1, 7, 8 and 12 and N
PN transistors 2 and 11, diodes 3 to 6,
9 and 10, constant current sources 13 to 17, and resistors 19 and 2
0, 22 to 25, 28 and 29, a DC voltage source 21, and negative feedback amplifiers 26 and 27.

In FIG. 1, input terminal 1 is input from signal source 18.
The signals inputted through 01 and 102 are amplified by an amplifier formed by PNP transistor 1 and NPN transistor 2, and transmitted to the base of PNP transistor 7. The voltage level of the input signal at this time is VIN
, when the voltage level of the signal transmitted to the base of the PNP transistor 7 is V1, the following equation is obtained.

V1 = VIN・(re3+re4)/(
re1+re2) ………………(1) In the above equation, re1, re2, re3 and re4 are PNP transistor 1, NPN transistor 2,
It represents the equivalent resistance in diodes 3 and 4. However, since the currents flowing through these PNP transistor 1, NPN transistor 2, and diodes 3 and 4 are the same, V1=VIN.

The signal transmitted to the base of the PNP transistor 7 is amplified by a differential amplifier including the PNP transistor 7 and the PNP transistor 8, and is output as an in-phase signal to the collector of the PNP transistor 8.
The signal is outputted to the collector of the PNP transistor 7 as a signal of opposite phase. The voltage levels of these in-phase and anti-phase output signals are V2-1 and V2-2, respectively, and the resistance values of resistors 20, 23, and 24 are R20 and R, respectively.
Assuming that the resistance value R20 of the resistor 20 is sufficiently larger than the equivalent resistance value of the PNP transistors 7 and 8 as 23 and R24, the following equation is obtained.

[0012] V2-1≒V1 (R23/R20)=
VIN (R23/R20)…………(2)
V2-2 ≒-V2 (R24/R20)=-VIN
(R24/R20)……(3) Here, if the resistance values R20, R23 and R24 are set to the same value, obviously V2-1 = VIN, V2-2 = -V
It becomes IN. These in-phase and anti-phase signals are further
The signals are input to negative feedback amplifier 26 and negative feedback amplifier 27, amplified, and output to output terminals 103 and 104, respectively. That is, in this embodiment, the signal source 18
As mentioned above, the gain from the input stage to the input stage of the two negative feedback amplifiers 26 and 27 is determined by the resistance value R20.
, R23 and R24 to the same value, it is possible to achieve 0 dB. Also, in the negative feedback amplifiers 26 and 27, the resistances 22, 28 and 25, 29 that act as feedback resistances can be set to 0 dB. By appropriately setting the resistance value, the gain of this amplifier circuit can be set arbitrarily.

In the case of this embodiment, since the DC potential output from the differential amplifier including the PNP transistors 7 and 8 is floating, the DC bias is applied from the DC voltage source 21 via the resistors 23 and 24, respectively. voltage is applied. As a result, the resistors 22 and 25, which form part of the feedback resistance of the negative feedback amplifiers 26 and 27, also have their one ends connected to the DC voltage source 21. Therefore, the negative feedback amplifier 26
and 27, it is possible to operate based on the potential of the DC voltage source 21 (1/2 potential of the power supply voltage), and a capacitor for removing the DC voltage gain is not required as in the conventional example. .

Further, the bias voltage corresponding to the input side of the differential amplifier formed by PNP transistors 7 and 8 is applied to the amplifier formed by PNP transistor 1 and NPN transistor 2, and the PNP transistor 12.
However, since the collectors of NPN transistors 2 and 11 are floating, the base potentials of NPN transistors 7 and 8 are set to the power supply terminal 105 as a reference potential. Therefore, the base-collector voltages of PNP transistors 7 and 8 are set over a wide range. In addition, since the input terminal 101 is directly connected to the base of the PNP transistor, input can be made based on the ground terminal as in the past, and a capacitor for blocking input direct current is not required.

[0015]

As described above, the present invention is applied to an amplifier circuit that includes a differential amplifier at the front stage and a pair of negative feedback amplifiers at the rear stage, and is capable of supplying a bias voltage to the input side of the negative feedback amplifier. For practical purposes, the provision of a predetermined constant voltage source eliminates the need for large capacitance capacitors, and has the effect of eliminating obstacles to IC implementation of the amplifier circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 7, 8, 12, 35, 36, 40, 46, 49
PNP transistors 2, 11 NPN transistors 3 to 6, 9, 10, 37, 38, 43, 45, 48
Diodes 13-17, 31-34, 44, 47, 50, 51
Constant current sources 18, 61 Signal sources 19, 20, 22-25, 28, 29, 39, 41, 4
2, 54, 55, 58-60 Resistance 21
DC voltage sources 26, 27, 56, 57 Negative feedback amplifiers 30, 6
2 Load

Claims (1)

[Claims] 1. An amplifier circuit comprising a differential amplifier at the front stage and a pair of negative feedback amplifiers at the rear stage which input the pair of output voltages of the differential amplifier and output in-phase and anti-phase voltages, respectively. , respectively connected between the first and second PNP transistors forming the differential amplifier, the collectors of the first and second PNP transistors, and a ground side terminal indicating a reference potential on the low potential side. the first and second constant current sources;
first and second diodes connected respectively between the base of the NP transistor and the reference voltage source on the high potential side; the bases of the first and second PNP transistors and the reference on the low potential side; a first NP that is inserted and connected as an amplifier circuit between the ground side terminal that indicates the potential;
The output voltages of the collectors of the N transistor/third PNP transistor, the second NPN transistor/fourth PNP transistor, and the first and second PNP transistors are input to the positive phase side input terminal and amplified. death,
first and second negative feedback amplifiers that feed back their respective output voltages to the negative phase side input terminals via feedback resistors;
and a constant voltage source that supplies a reference voltage to the positive phase side input terminal and negative phase side input terminal of the second negative feedback amplifier via a resistor.