JPH04340638A - Disk cache control system - Google Patents

Abstract

PURPOSE:To shorten a wait time till the execution start of a following instruction in the case plural instructions exsist successively. CONSTITUTION:A disk cache controller 3 is provided with a link pointer monitor means 3-1 to discriminate whether the instruction held in a disk instruction indicating means 2-1 of a main storage device 2 has a following instruction or not. If it has a following instruction, a data transfer instruction outputted from the disk cache controller 3 to a disk device 5 is not accompanied with prefetch. But otherwise, it is accompanied with prefetch. Thus, data other than essential data required for execution of the current instruction is not transferred if this instruction has a following instruction, and the wait time till the execution start of the following instruction is minimum. Another instruction is prefetched in the case of the absence of any queued instructions to improve the following hit rate of a disk cache memory 4.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a disk cache memory that reduces the waiting time until the start of execution of a subsequent instruction when there are multiple instructions to be executed in succession when reading data from a disk device to a disk cache memory. This concerns the control method.

0002

2. Description of the Related Art FIG. 5 shows a computer system to which a conventional disk cache control method is applied. In Figure 5, 1
is the CPU (central processing unit), 2 is the main memory, 2-
1 is a disk command instruction means, 3 is a disk cache control device, 4 is a disk cache memory, and 5 is a disk device. The main storage device 2 and disk cache memory 4 are D
RAM (dynamic random access memory)
Consists of.

[0003] Data necessary for the CPU 1 to perform processing is provided from a disk device 5. However, a disk cache memory 4 is provided, and part of the data in the disk device 5 is copied thereto. A command to read data necessary for processing is issued by the CPU 1, but it is issued by the disk command instruction means 2- of the main storage device 2.
It is held at 1 and executed sequentially.

FIG. 2 is a diagram showing the types of instruction holding states in the disk instruction instruction means 2-1. In FIG. 2, 6 is a queue head, 7 to 9 are instructions, and P is a link pointer. The disk command instruction means 2-1 is a means capable of holding a plurality of "commands" in the form of a queue, and is also called a queue.

[0005] A queue head 6 indicates the head portion of the queue. Instructions to be executed are held after the queue head 6 in the order in which they are to be executed. The queue head 6 and the instructions 7 and the like connected thereto have a link pointer P indicating the location address of the next consecutive instruction.

FIG. 2(a) shows that the instruction to be executed is
This shows a state in which 3 messages have already been emitted from 1. The link pointer P of the instruction 7 to be executed first indicates the location address of the instruction 8 to be executed next. The link pointer P of instruction 8 indicates the location address of instruction 9. If the next command to be executed has not yet been issued,
The link pointer P in the previous instruction is usually “0” (n
il, nil). This "0" means that there is no next instruction. Therefore, the link pointer P of instruction 9 in FIG. 2(a) is nil.

FIG. 2(B) shows a case where there is one command issued by the CPU 1, and FIG. 2(C) shows a case where there is no command issued at the moment, that is, when the queue head 6 is The case where it is nil is shown.

According to the command held in the disk command instruction means 2-1, the target data is transferred from the disk cache memory 4 or the disk device 5 to the main storage device 2.
The disk cache control device 3 controls the transfer to the disk cache controller 3. Next, its operation will be explained.

FIG. 6 is a flowchart illustrating the operation of the conventional disk cache control method. Item numbers ■ to ■ in the following description correspond to steps ■ to ■ in FIG. 6 .

(2) Check whether the queue head 6 of the disk command instruction means 2-1 is nil. n
If il, that is, if there is no instruction as in the case of FIG. 2(c), the flow of processing proceeds to the end. (2) If the queue head 6 is not nil, follow the instruction and first check whether the desired data exists in the disk cache memory 4. That is, the disk cache memory 4 is checked to see if there is a hit.

(2) If there is a hit, the data is transferred from the disk cache memory 4 to the main storage device 2. ■
If there is no hit, the data must be retrieved from the disk device 5, so the disk cache control device 3 issues a command to do so. The instruction is assumed to be a prefetch instruction. An instruction to prefetch is an instruction to order not only data that is needed immediately but also data that will be needed later. The reason why such a prefetch command is issued is that if data other than the data that is needed immediately is also ordered, the probability of a hit later in the disk cache memory 4 is reduced.
This is because it can be made higher.

FIG. 4 is a diagram illustrating data with and without prefetching. Assume that A is data that is needed immediately, and B is data that is about to be ordered. FIG. 4A shows a case where prefetching is not performed, and when data is requested from the disk device 5, only data A is requested. Figure 4
(b) is a case of prefetching, in which data B is also ordered in addition to data A.

[0013] ■ Execute data transfer. Conventionally, prefetching is performed, so according to the example of FIG. 4, data A and data B in the disk device 5 are transferred to the disk cache memory 4. Then, the data A that is needed immediately is transferred from the disk cache memory 4 to the main storage device 2.

However, in such a disk cache control system, when a plurality of instructions are held in the disk instruction instruction means 2-1, the waiting time until the next instruction is executed is as described below. For some reason, it has the disadvantage of being longer than necessary.

That is, in the disk cache control system described above, whenever an instruction is executed, the disk cache control device 3 issues a prefetch instruction to the disk device 5. Therefore, as shown in FIG. 2(a), when multiple instructions are issued from the CPU 1, execution of instruction 8 starts with the data (A) that is absolutely needed by instruction 7. This is after the transfer of both data (B), which is not necessary but is to be ordered, is completed.

It is unavoidable to have to wait for the time required to transfer data (A), but data (B) that is not needed right away is unavoidable.
) is forced to wait for the next waiting instruction 8 to transfer unnecessary data, and is forced to wait longer than necessary. There will be.

[0017] Therefore, in order to eliminate this increase in waiting time, various proposals have been made in the past. For example, in Japanese Patent Application Laid-open No. 60 (1986), it was designed to respond to the next instruction in the middle of prefetching.
In addition to JP-A-101654, JP-A-61-75942, JP-A-62-243044, JP-A-60
-163146, JP 63-5447, JP 63-284651, JP 63-7
No. 5950, Japanese Unexamined Patent Publication No. 1-70844,
There are Japanese Patent Application Laid-Open No. 1-144141, etc.

[0018]

[Problems to be Solved by the Invention] However, each of the above proposals has a problem in that the programs and hardware become extremely complicated. Therefore, it is an object of the present invention to prevent an increase in the waiting time of subsequent instructions using extremely simple means.

[0019]

[Means for Solving the Problems] In order to solve the above problems, the disk cache control method of the present invention includes a main storage device, a disk device, and a disk cache provided between the main storage device and the disk device. A link pointer monitoring means for determining whether a link pointer of an instruction to be executed is nil is provided in a disk cache control device that controls data transfer between memories, and link pointer monitoring means for determining whether a link pointer of an instruction to be executed is nil is provided, When the link pointer is nil, the data transfer instruction to be issued is an instruction to prefetch, and when it is not nil, it is an instruction not to prefetch.

[0020]

[Operation] When there is a subsequent instruction to the instruction held in the disk instruction instruction means of the main storage device, the data transfer instruction issued from the disk cache control device to the disk device is set as a non-prefetch instruction. On the other hand, when there is no subsequent instruction, the instruction is prefetched.

[0021] By doing this, when there is a subsequent instruction, no data other than data essential for the execution of the current instruction is transferred, so that the waiting time until the execution of the subsequent instruction can be started is minimized. Further, when there is no waiting instruction, prefetching can improve the subsequent hit rate in the disk cache memory.

[0022]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a computer system to which the disk cache control method of the present invention is applied. Reference numerals correspond to those in FIG. 5, and 3-1 is a link pointer monitoring means. Those corresponding to those shown in FIG. 5 operate in the same way, so a description thereof will be omitted. Link pointer monitoring means 3-
Reference numeral 1 denotes means for checking the contents of the link pointer P included in the instruction of the disk instruction instruction means 2-1 and determining whether there is a subsequent instruction.

The difference from the conventional example shown in FIG. 5 is that a link pointer monitoring means 3-1 is provided in the disk cache control device 3, and it is used to determine whether or not to prefetch depending on whether there is a subsequent instruction.

FIG. 3 is a flowchart illustrating the operation of the disk cache control method of the present invention. Item numbers ■ to ■ in the following explanation correspond to steps ■ to ■ in FIG. 3 . (2) The queue head 6 of the disk command instruction means 2-1 checks whether it is nil. If nil, that is, if there is no instruction as in the case of FIG. 2(c), the flow of processing proceeds to the end. ■Cue head 6
If is not nil, it is first checked to see if the desired data exists in the disk cache memory 4 according to that instruction. That is, the disk cache memory 4 is checked to see if there is a hit. (2) If there is a hit, the data is transferred from the disk cache memory 4 to the main storage device 2.

(2) Check whether another instruction is waiting in the disk instruction instruction means 2-1 after the instruction that is about to be executed. This is checked by the link pointer monitoring means 3-1. For example, disk command instruction means 2-
If the state of instruction 1 is as shown in Figure 2 (b), there is no subsequent instruction after instruction 7, which is about to be executed, so the link pointer P of instruction 7 should indicate nil. . By checking this nil, it is determined that there is no subsequent instruction. On the other hand, in the case shown in FIG. 2(a), there is instruction 8 after instruction 7, so the link pointer P of instruction 7 should indicate the location address of instruction 8, not nil. be. In this case, it is determined that there is a subsequent instruction by checking that it is not nil.

(2) If there is a subsequent instruction, the disk cache control device 3 issues a non-prefetch instruction as an instruction to retrieve data from the disk device 5. In other words, it issues a command to retrieve only the data that is absolutely necessary now (data A in Figure 4), and it also issues a command to retrieve data that includes data that will be needed in the future (data A+B in Figure 4). I won't release it. By doing this, the time to transfer data is shortened (the time required to transfer data B is shortened), the time required to complete the current command is shortened, and the next command can be started quickly. become. That is, the waiting time for the next command is shortened.

(2) If there is no subsequent instruction, the disk cache control device 3 issues a prefetch instruction as an instruction to retrieve data from the disk device 5. In this case, since there is no next instruction waiting, prefetching does not cause problems such as delaying the execution of subsequent instructions. If prefetching is performed, data that will be used soon will also be transferred to the disk cache memory 4, so that the subsequent hit rate in the disk cache memory 4 will be improved.

■ Execute data transfer. If prefetching is not performed, according to the example of FIG. 4, only data A in the disk device 5 is transferred to the disk cache memory 4 and further transferred to the main storage device 2. In the case of prefetching, data A and data B in the disk device 5 are transferred to the disk cache memory 4. and,
Data A that is needed immediately is transferred from the disk cache memory 4 to the main storage device 2.

[0029]

As described above, according to the disk cache control system of the present invention, when there is a subsequent instruction to the instruction held in the disk instruction instruction means of the main storage device, the disk cache control device The data transfer instruction issued to the device is an instruction that does not prefetch, and (2) when there is no subsequent instruction, it is an instruction that prefetch.

Therefore, when there is a subsequent instruction, no data other than data essential for the execution of the current instruction is transferred, so the waiting time until the execution of the subsequent instruction can be started is minimized. Further, when there is no waiting instruction, prefetching can improve the subsequent hit rate in the disk cache memory.

Furthermore, the present invention can be realized by simply monitoring whether or not the link pointer is nil using the link pointer monitoring means provided in the disk cache control device. Unexamined Japanese Patent Publication 1986
This method is extremely simple compared to the technique disclosed in Japanese Patent Publication No. 243044).

[Brief explanation of the drawing]

[Figure 1] Computer system applying the disk cache control method of the present invention

[Figure 2] Diagram showing types of instruction holding states in the disk instruction instruction means

[Figure 3] Flowchart explaining the operation of the disk cache control method of the present invention

[Figure 4] Diagram explaining data when prefetching and not prefetching

[Figure 5] Computer system applying conventional disk cache control method

[Figure 6] Flowchart explaining operations in the conventional disk cache control method

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...CPU, 2...Main storage device, 2-1...Disk command instruction means, 3...Disk cache control device, 3-1...Link pointer monitoring means, 4...Disk cache memory, 5
...Disk device, 6...Cue head, 7-9...Instruction, P
…link pointer

Claims (1)

[Claims] Claim 1: A program to be executed in a disk cache control device that controls data transfer between a main storage device, a disk device, and a disk cache memory provided between the main storage device and the disk device. A link pointer monitoring means for determining whether a link pointer of an instruction is nil is provided, and a data transfer instruction issued from the disk cache control device to the disk device is treated as a prefetch instruction when the link pointer is nil. , a disk cache control method characterized in that an instruction is not prefetched when it is not nil.