JPH04340473A - Comparator having input buffer - Google Patents

Abstract

PURPOSE:To reduce the bias current of a comparator by connecting an input buffer circuit having a function transmitting input voltage and a function preventing the lowering of an input dynamic range using a dummy transistor and cancelling an input bias current. CONSTITUTION:An input buffer circuit 3 fitted with a bias current cancelling circuit is provided before a window comparator constituted of comparators 1a, 1b and constituted of bipolar transistors without using an FET. Since the currents connected to transistors Q10, Q12 are equal, the base current of said transistors become equal. A Wilson current mirror composed of transistors Q14-Q16 allows a reference current to flow. By providing the input buffer circuit of the bias current cancelling circuit before the comparator as mensioned above, a bias current can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator having an input buffer, and more particularly to a technique for reducing the bias current of a window comparator.

0002

2. Description of the Related Art FIG. 4 is a diagram showing an example of a circuit configuration of a general window comparator. This window comparator consists of two comparators 1a and 1b configured by combining an input stage emitter follower and a differential amplifier.

0003

[Problem to be solved by the invention] In the circuit of FIG.
An input signal that can be followed by emitter follower Q1 in the input stage (
Pulse signal) Consider the slew rate (SR) of Vin (
An example of SR in a window comparator is shown in FIG. 5).

In FIG. 4, if the current of the current source is IE and the parasitic capacitance attached to it is CS, then the emitter follower Q1
The SR (V/ns) that can be followed is IE (mA) /
Determined by C(pF).

Therefore, when processing an input signal with high SR using the same element, it is necessary to increase IE, and in this case, the base current also increases (base current IB1 of emitter follower Q1 is approximately equal to IEQ1/ (because it can be approximated as β). Furthermore, since two comparators are always required, the input bias current is twice that amount. For example, when SR is 2 (V/ns), CS=0.5pF,
If βQ1=100, IE=2×0.5 =1m
A, IIN=2×(1(mA)/100)=20(μA
), and a bias current of 20 μA flows.

[0006] This bias current reduces the accuracy when making measurements using a window comparator, and also
Measurement accuracy will also be reduced when performing DC measurements without using a window comparator. Therefore, when the comparator is not used, such as during DC measurement, it is necessary to use a relay or the like to disconnect it from other circuits, which leads to the complexity of the circuit.

The present invention has been made based on such consideration, and its purpose is to reduce the bias current of the comparator, and in particular, to reduce it while maintaining the input voltage dynamic range.

[0008]

SUMMARY OF THE INVENTION The present invention is constructed by connecting an input buffer circuit to an input terminal of a comparator, which has a function of transmitting an input voltage signal and a function of canceling an input bias current. Furthermore, the bias current cancel circuit has a circuit configuration that uses dummy transistors to prevent a decrease in the input dynamic range.

[0009]

[Operation] The input bias current is sufficiently reduced by the function of the bias current cancellation circuit included in the input buffer. Furthermore, since the bias current canceling circuit has an ingenious configuration using dummy transistors, it is possible to prevent a decrease in the input dynamic range. Therefore, reduction in bias current can be achieved without using FETs.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the basic configuration of the present invention. An input buffer circuit 3 with a bias current cancellation circuit is provided in front of the common input VINC of a window comparator composed of comparators 1a and 1b (to which a high-level reference voltage VrefH and a low-level reference voltage VrefL are applied, respectively). There is. This input buffer circuit 3 is constructed entirely of bipolar transistors without using FETs.

FIG. 1 is a diagram showing a specific example of the circuit configuration of the input buffer circuit 3. As shown in FIG. (Configuration) The input buffer circuit 3 includes an emitter follower (dummy transistor) Q10 and a constant current source (VB, Q11) with a current amount IE1, and a constant current source (VB, Q11) with an emitter follower Q12 and IE2 (current amount equal to IE1). Q
17), a transistor Q18 for absorbing the emitter current of the emitter follower Q12, an emitter follower Q13 for sensing the collector current of the emitter follower Q12, and an output current based on the base current of the emitter follower Q13. Transistors Q14, Q15, Q1 injected into the base of Q10
6 Wilson current mirrors. (Operation) The input buffer circuit 3 receives the input signal VIN and transmits the voltage VIN-VBEQ10 to the window comparator (VBEQ10 is the voltage between the base and emitter of Q10, and the same applies hereinafter).

As mentioned above, transistors Q10 and Q
Since the current amounts IE1 and IE2 of the current sources connected to the transistors 12 and 12 are equal, the base currents IB1 and IB2 of each transistor are equal (therefore, ID=ICM also holds true). Further, since substantially the same collector current flows through the transistor Q13 connected to the collector of the transistor Q12, IB1=IB2=IB3.

Here, the Wilson current mirror made up of transistors Q14 to Q16 uses IB3 as a reference current and causes a current IC6 (=IB3) to flow through transistor Q16. That is, IB1=IC6, and ideally, IIN=0.

In reality, there is a difference between IB1 and IB2, and when calculated with βnpn = 100 and βpnp = 50, IIN = 6.55 x 10-6 x IE1, and IE
When 1=1 mA, the bias current is approximately 6.5 nA. (Study of input voltage range) Considering that the maximum input voltage that can be input without saturating all transistors with respect to the power supply voltage Vcc is up to VCB = 0 for each transistor, VINMA
When X=VCC-VBEQ15-VBEQ16, VCB of transistor Q16 becomes 0. Also, at this time, from VBEQ10=VBEQ10, transistor Q1
2 also becomes VCB=0 at the same time. Therefore, this is the maximum input voltage.

It is also possible to use a conventional bias cancellation circuit as shown in FIG.
INMAX=VCC-VBEQ15-VBEQ16-V
BEQ13, and at this time, the V of transistor Q10
CB=0V.

Therefore, in the case of FIG. 1, the input voltage range is expanded by VBEQ13, that is, about 0.75V, compared to the case of FIG.

[0018]

[Effects of the Invention] As explained above, the present invention can significantly reduce the bias current by providing an input buffer circuit with an improved bias current canceling circuit in front of the comparator. This has the effect of expanding the input voltage range compared to a bias cancel circuit.

[0019] By reducing the bias current, there is no need for disconnection using a relay during DC measurement, making it possible to create a compact and highly reliable system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment using a conventional bias cancellation circuit.

FIG. 3 is a diagram showing the basic configuration of the present invention.

FIG. 4 is a diagram showing a conventional example.

FIG. 5 is a diagram showing an example of slew rate (SR) in the circuit of FIG. 4;

[Explanation of symbols]

1a, 1b Comparator 3 Input buffer circuit

Claims (1)

[Claims] 1. An input buffer circuit (3) having a bias cancel circuit is connected to an input terminal of the comparator, and the bias cancel circuit has a base to which an input signal is input, and an emitter to which a predetermined amount of current is applied. A first transistor (Q10) is connected to a constant current source, and a base is connected to the emitter of the first transistor (Q10), and a second constant current source having the same current amount as the first constant current source is connected to the emitter. A second transistor (Q12) to which a constant current source is connected, and this second transistor (Q12)
A third transistor (Q13) has an emitter-collector path connected to the collector of the third transistor (Q13), and the base current of this third transistor (Q13) is taken as an input current, and the output current is the output current of the first transistor (Q10). Current mirror circuit sending to the base (Q14, Q15, Q1
6) The first transistor (Q10)
A comparator having an input buffer, wherein the input signal is transmitted to the comparator via a base-emitter of the comparator.