JPH04337833A - Data processor - Google Patents

Abstract

PURPOSE:To invalidate an entry having same virtual machine number(VMN) registered in a branching history table when TLB by means of VMN is invalidated and to eliminate an invalid address conversion processing. CONSTITUTION:VMN is registered in accordance with the respective entries of the branching history table (TAB) 7 and respective VMN of TAB 7 are sequantially read out in accordance with a VMN invalidating instruction 120. Having read VMN 110 is compared with VMN 107 which is to be invalidated in a VMN match circuit 10. When they match, the entry in TAB 7 at that time is invalidated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus in which a branch destination address of a branch instruction is predicted in advance using a branch history table.

0002

2. Description of the Related Art Conventional data processing devices of this type have a branch history table that stores the instruction address of a branch instruction and the branch destination address of this branch instruction as paired entries, and a branch history table that is indexed by an instruction fetch address. The branch target address is configured to be a predicted branch target address based on the result of this comparison.

[0003] Here, in order to translate from a virtual address to a real address, TLB (Translation
Lookaside Buffer) is used. In this TLB, the corresponding contents of the TLB may be invalidated by the virtual machine number (VMN) (this is called TLB invalidation by virtual machine number), and data cannot be retrieved by the invalidated VMN. When a request is made, since there is no corresponding entry in the TLB, it is necessary to access the main memory, generate a real address, and retrieve the data. Furthermore, data retrieval using such an address is likely to be an exception.

[0004] The above-mentioned branch history table is
Even after the TLB is invalidated by VMN, the virtual address corresponding to that VMN remains registered in the branch history table. Therefore, when a virtual address in a VMN that does not exist in the TLB is read as a predicted branch destination virtual address from the branch history table and converted to a real address in the TLB, the real address corresponding to this VMN is not registered, so a useless operation is performed. There is a high possibility that it will be done. Furthermore, since it is necessary to access the main memory in order to convert the virtual address to a real address, there is a drawback that the processing of instructions is delayed.

Furthermore, the instruction address and predicted branch destination address of the branch instruction stored in the branch history table are
If it corresponds to the VMN used for TLB invalidation,
That entry is unused and useless.

[0006]

OBJECTS OF THE INVENTION An object of the present invention is to provide a data processing device that invalidates entries having the same VMN registered in a branch history table when a TLB is invalidated by a VMN. be.

[0007]

According to the present invention, a branch history table stores an instruction address of a branch instruction and a branch destination address of this branch instruction as a pair of entries, and the branch history table is indexed by an instruction fetch address. A virtual machine type data processing device comprising means for comparing the derived instruction address and the instruction fetch address, and configured to set the branch destination address as a predicted branch destination address based on the comparison result, A means for registering virtual machine numbers corresponding to instruction addresses in the branch history table, and a means for sequentially reading out and invalidating the virtual machine numbers registered in the branch history table in response to a virtual machine number invalidation instruction. The present invention is characterized by comprising means for comparing a virtual machine number with a read virtual machine number, and means for invalidating a corresponding entry in the branch history table when a match is detected as a result of this comparison. A data processing device is obtained.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The instruction address selector 1 is a selector that selects an instruction address to be sent to the instruction address register (IAR) 4 via the signal line 101. In the case of branch history table read and write operations in normal operation, the instruction address selector 1 is a selector that selects an instruction address to be sent to the instruction address register (IAR) 4 via the signal line 101. selects the instruction fetch address and branch address of the branch instruction sent from the instruction fetch control unit via the signal line 102, and selects the address sent from the +1 counter 6 and the upper bits of the register 4 via the signal line Select.

Register 4 is a register that receives an instruction address sent from selector 1 via signal line 101. The lower bits of register 4 are stored in the branch history table (T) via signal line 103 as a RAM address.
AB) 7, branch destination history table (DAB) 8 and +
1 counter 6. The upper bit of register 4 is connected to TAB7 via signal line 104 in the case of a write operation.
will be sent to. In addition, in the case of read operation, the signal line 105
The data is sent to the TAB hit detection circuit 9 via the TAB hit detection circuit 9.

+1 counter 6 is a counter that increments the RAM address sent from the lower bit of register 4 via signal line 103, and its output is sent to signal line 102.
is sent to selector 1 via. The virtual machine number selector 2 is a selector that selects the VMN to be sent to the virtual machine number holding register 3 via the signal line 106, and in the case of branch history table write operation in normal operation, TLB control is sent via the signal line 117. When clearing the TLB, select the VMN sent from the TLB controller via the signal line 118.
Select clear VMN.

The VMN holding register 3 is a register that receives the VMN sent from the selector 2 via the signal line 106, and in the case of a write operation, it is sent to the TAB 7 via the signal line 107. Furthermore, when the TLB is cleared, it is sent to the VMN coincidence detection circuit 10 via the signal line 107.

Branch destination address register (PDWD) 11
is a register that holds a branch destination address paired with the branch address of the branch instruction received by the instruction register 4 during a write operation, and is sent to the DAB 8 via the signal line 109.

TAB7 stores the upper bits of the branch address sent from the upper bits of the instruction register 4 via the signal line 104 and the VMN corresponding to the branch address sent from the VMN register 3 via the signal line 107. The VMN side (higher bits) of TAB7 is sent to the VMN coincidence detection circuit 10 via a signal line 110. In addition, the branch address side (lower bit) is connected to the signal line 105.
The data is sent to the TAB hit detection circuit 9 via the TAB hit detection circuit 9. D.A.B.
8 is sent to the predictive branch destination address register (PDAR) 12 via the signal line 115.

The TLB clear display flag 5 is an F/F that indicates that the TLB is being cleared, and receives a signal sent from the TLB control unit via the signal line 120 and sends the signal to the AND gate 13 and the instruction register 4 via the signal line 108. It is sent as a reset signal.

In the case of a RAM read operation, the TAB hit detection circuit 9 detects the upper bits of the branch address of the branch instruction read from the TAB 7 via the signal line 105 and the upper bits of the register 4 via the signal line 104. This is a comparator that compares the sent instruction fetch address with the upper bits, and sends it to the TAB hit detection flag 14 via the signal line 111. This flag 14 is connected to the signal line 111
This flag receives the result sent from the TAB hit detection circuit 9 via the TAB hit detection circuit 9, and sends it to the outside.

Predicted branch destination address register (PDAR)
12 is a register that receives the branch destination address sent from DAB8 via signal line 115.

The VMN coincidence detection circuit 10 has a signal line 110.
VMN corresponding to the branch address of the branch instruction read from TAB7 via signal line 107, and VM via signal line 107.
This is a comparator that compares the TLB clear VMN sent from the N holding register 3, and the result is sent to the AND gate 13 via the signal line 113.

The VMN coincidence detection flag 15 is set on the signal line 11.
2 to the result of the VMN coincidence detection circuit 10 and the signal line 1
This flag receives the logical product of the signal sent from the TLB clear display flag 5 via the signal line 113 via the signal line 113, and if the result is “1”, the inverted result is sent via the signal line 114 to the V bit. It is sent to the selector 16. The bit selector 16 selects the V bit sent from the VMN match detection flag 15 via the signal line 114 and the signal line 1.
It is a selector that selects the internally generated V bit via the signal line 121, and the TAB7 via the signal line 121.
Send to.

Next, the operation will be explained. The normal operation includes registering the result of a branch instruction and indexing operation when fetching an instruction. In the case of registration operation, via the signal line 119,
Selector 1 selects the instruction address of the branch instruction, and register 4 receives it. At the same time, the register 11 receives the branch destination address that is paired with the instruction address of the previous branch instruction. In addition, the VMN corresponding to the instruction address of the previous branch instruction is selected by the selector 2 via the signal line 117, and the VM
Received by N holding register 3.

The lower bits of the instruction address received in register 4 are sent to TAB7 and DAB8 via signal line 103 as the write address of TAB7 and DAB8, and the upper bits of the instruction address, VMN received in register 3, and register 11 are The received branch destination address is sent to the signal line 104.
, 107 and 109 respectively TAB7, DAB
Write to 8.

In the case of an index, the selector 1 selects the instruction fetch address via the signal line 119, and
Receive at register 4. The lower bit of this register 4 is T
TAB7, D as the index address of AB7, DAB8
The instruction address and branch destination address of the written branch instruction are read from AB8. The read instruction address and the instruction fetch address received by the register 4 are compared in the TAB coincidence detection circuit 9, and if they are equal, the flag 14 is set to "1". At the same time, the register 12 receives the predicted branch destination address read from DAB8 via the signal line 115.

Next, the operation of erasing the branch history table when clearing the TLB, which is a feature of the invention, will be explained. When clearing the TLB, the VMN to be cleared sent from the TLB control unit is selected by selector 2 via signal line 117 and received by register 3, and the TLB clear signal is set to flag 5 via signal line 120. do. The register 4 is reset by the TLB clear signal received by the flag 5 via the signal line 108.

Using the lower bit of the register 4 as an index address, the VM written to the TAB 7 is counted up by +1 by the + counter 6 via the signal line 103.
N (VMN corresponding to the instruction address and branch destination address of the branch instruction written in TAB7 and DAB8).

The VMN coincidence detection circuit 1 detects the VMN read from the TAB 7 via the signal line 110 and the VMN whose TLB is cleared received by the register 3 via the signal line 107.
Compare with 0. The result is ANDed with the signal sent from flag 5 via signal line 112 and signal line 108 by AND gate 13, and received by flag 15 via signal line 113. If the result is “1”, TL
The VMNs cleared during B clearing are TAB7, DA
This indicates that it is registered in B8, so the signal line 114
The index address whose flag 13 is set to "1" is set to "0" as the V bit (indicating that the data registered in the RAM is valid), and the selector 16
Write to TAB7 via.

[0026]

Effects of the Invention As described above, the present invention provides that when a TLB is invalidated by a VMN in a TLB in a branch history table, the instruction address of a branch instruction corresponding to the invalidated VMN is stored in the branch history table. , when the branch destination address paired with the instruction address of the previous branch instruction is stored, by providing a circuit to invalidate the entry, it is possible to prevent data retrieval from the VMN invalidated in the TLB. This has the effect of suppressing wasteful address translation processing due to TLB misses and improving the usage efficiency of the branch history table.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention.

[Explanation of symbols]

1 Instruction address selector 2 VMN selector 3 VMN holding register 4 Instruction address register 5 TLB clear display flag 7 Branch history table (TAB) 8 Branch destination history table (DAB) 9 TAB hit detection circuit 10 VMN match detection circuit 11 Branch destination address Register 12 Predicted branch destination address register

Claims (1)

[Claims] 1. A branch history table that stores an instruction address of a branch instruction and a branch destination address of this branch instruction as paired entries, and an instruction address derived by indexing the branch history table using an instruction fetch address. and means for comparing the instruction fetch address with the instruction fetch address, and is configured to set the branch destination address as the predicted branch destination address based on the comparison result, wherein the virtual machine number is set as the predicted branch destination address. A means for registering corresponding instruction addresses in a history table, and a means for sequentially reading virtual machine numbers registered in the branch history table in response to an instruction to invalidate a virtual machine number, and reading the virtual machine numbers as virtual machine numbers to be invalidated. A data processing device comprising: means for comparing a virtual machine number with a virtual machine number; and means for invalidating a corresponding entry in the branch history table when a match is detected as a result of the comparison.