JPH04336818A - Radio communication equipment - Google Patents

Radio communication equipment

Info

Publication number
JPH04336818A
JPH04336818A JP3138392A JP13839291A JPH04336818A JP H04336818 A JPH04336818 A JP H04336818A JP 3138392 A JP3138392 A JP 3138392A JP 13839291 A JP13839291 A JP 13839291A JP H04336818 A JPH04336818 A JP H04336818A
Authority
JP
Japan
Prior art keywords
pll
channel
setting
plls
setting data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3138392A
Other languages
Japanese (ja)
Inventor
Takayuki Tanabe
孝幸 田辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP3138392A priority Critical patent/JPH04336818A/en
Publication of JPH04336818A publication Critical patent/JPH04336818A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce a waiting time being a frequency setting time to a negligible degree by driving individually and sequentially plural PLLs so as to set a transmission/reception frequency continuously. CONSTITUTION:A CPU 1 sends a 10ch setting data (a 1st setting data) to a 1st PLL 2a and sends a PLL selective signal to the selector 3 so that the output of the selector 3 is an output from the 1st PLL 2a thereby, awaiting channel setting of the 1st PLL 2a. On the other hand, 1ch, 2ch used succeedingly are respectively set to 2nd and 3rd PLLs 2b, 2c for a time till the channel setting of the 1st PLL 2a is finished. That is, a 1ch setting data being a 2nd setting data and a 2ch setting data being a 3rd setting data are set respectively to the 2nd PLL 2b and 3rd PLLs 2b, 2c being 1ch, 2ch channel setting data.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は無線通信装置、より詳し
くは位相同期回路(Phase lock loop、
以下、「PLL」という)を用いて送受信用周波数が設
定される無線通信装置に関する。
[Industrial Application Field] The present invention relates to a wireless communication device, more specifically a phase lock loop.
The present invention relates to a wireless communication device in which transmitting and receiving frequencies are set using a PLL (hereinafter referred to as "PLL").

【0002】0002

【従来の技術】従来の無線通信装置は、一般に1個又は
1組のPLLを用いて送受信用周波数(以下、「チャネ
ル」という)の設定が行われている。
2. Description of the Related Art Conventional wireless communication devices generally use one or a set of PLLs to set transmitting and receiving frequencies (hereinafter referred to as "channels").

【0003】そして、この種の無線通信装置においては
、図5に示すように、PLLによりチャネル設定がなさ
れた後、該チャネルを使用してデータの送受信を行い、
データの送受信が終了した後、再びPLLにより次に使
用するチャネルの設定が行われている。
[0003] In this type of wireless communication device, as shown in FIG. 5, after a channel is set by a PLL, data is transmitted and received using the channel.
After data transmission and reception are completed, the next channel to be used is set again by the PLL.

【0004】このように従来の無線通信装置は、1個又
は1組のPLLを用いることにより多くのチャネルを効
率よく設定することができる。
[0004] In this manner, conventional wireless communication devices can efficiently set many channels by using one or one set of PLLs.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来の無線通信装置においては、上述した如く、多くのチ
ャネルを1つのPLLで設定することができるという長
所を有する一方、PLLの特性上一つの空チャネルを検
出するのに時間がかかるため、一つのチャネル設定が完
了するのに時間がかかり過ぎるという欠点があった。し
かも、データ送受信が終了した後、次のチャネル設定が
開始されるため、データ送受信が開始するまでにかなり
の待ち時間が生じるという欠点があった(図5中、送受
信時間をt1、待ち時間をt2で示す)。そして、該待
ち時間t2のために次のような問題点があった。すなわ
ち、 (1)この待ち時間が、基地局(親機)における処理能
力アップを阻んでいる。 (2)データ通信専用の通信システムの場合、送受信時
間が音声系に比べ極端に短いため、チャネル設定時の待
ち時間は無視できない程大きい。 (3)この無駄な待ち時間が、バッテリー駆動の無線タ
ーミナルにおいては、無駄な消費電流を生み、バッテリ
ー寿命に影響を与える。 等の問題点があった。
[Problems to be Solved by the Invention] However, as mentioned above, while the conventional wireless communication device has the advantage of being able to set many channels with one PLL, due to the characteristics of the PLL, one empty Since it takes time to detect a channel, there is a drawback that it takes too much time to complete one channel setting. Moreover, since the next channel setting is started after data transmission/reception is completed, there is a drawback that there is a considerable waiting time before data transmission/reception starts (in Figure 5, the transmission/reception time is t1, the waiting time is (denoted as t2). The waiting time t2 causes the following problems. That is, (1) This waiting time prevents the base station (base station) from increasing its processing capacity. (2) In the case of a communication system dedicated to data communication, the transmission and reception time is extremely short compared to that of a voice system, so the waiting time when setting a channel is so large that it cannot be ignored. (3) This wasted waiting time generates wasted current consumption in battery-powered wireless terminals, which affects battery life. There were problems such as.

【0006】本発明はこのような問題点に鑑みなされた
ものであって、より高効率で無線通信を行うことができ
る無線通信装置を提供することを目的とする。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a wireless communication device that can perform wireless communication with higher efficiency.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明は、PLLを用いて送受信用周波数が設定され
る無線通信装置において、PLLを複数個備え、前記複
数個のPLLを個別に順次駆動して送受信用周波数を連
続して設定する設定手段を有していることを特徴として
いる。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a wireless communication device in which transmitting/receiving frequencies are set using PLLs, which includes a plurality of PLLs, and individually controls the plurality of PLLs. It is characterized in that it has a setting means that sequentially sets the transmitting and receiving frequencies by sequentially driving the transmitting and receiving frequencies.

【0008】さらに、上記無線通信装置において、複数
個のPLLに対し、個別に異なる送受信用周波数が設定
されることを特徴としている。
Furthermore, the wireless communication device is characterized in that different transmission and reception frequencies are individually set for the plurality of PLLs.

【0009】[0009]

【作用】上記構成によれば、複数個のPLLを個別に順
次駆動して送受信用周波数を連続して設定するので、周
波数設定時の待ち時間を無視できる程度にまで短縮する
ことが可能となる。
[Operation] According to the above configuration, multiple PLLs are individually and sequentially driven to successively set the transmitting and receiving frequencies, so it is possible to shorten the waiting time when setting the frequency to a negligible level. .

【0010】また、複数個のPLLに対し、個別に異な
る送受信用周波数が設定されるので、異なる送受信用周
波数を使用して無線通信を行うことが可能となる。
Furthermore, since different transmitting and receiving frequencies are individually set for a plurality of PLLs, it is possible to perform wireless communication using different transmitting and receiving frequencies.

【0011】[0011]

【実施例】以下、本発明の実施例を図面に基づき詳説す
る。
[Embodiments] Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

【0012】図1は本発明に係る無線通信装置の一実施
例を示すブロック構成図である。
FIG. 1 is a block diagram showing an embodiment of a wireless communication device according to the present invention.

【0013】同図において、1は所定のチャネル制御を
行うCPU、2a,2b,2cはチャネルを設定する第
1〜第3のPLL、3は第1〜第3のPLL2a〜2c
からの出力を選択して、相手通信装置に出力信号を発す
るセレクタである。
In the figure, 1 is a CPU that performs predetermined channel control, 2a, 2b, 2c are first to third PLLs that set channels, and 3 are first to third PLLs 2a to 2c.
This is a selector that selects the output from the communication device and issues an output signal to the other party's communication device.

【0014】第1〜第3のPLL2a〜2cは、いずれ
も同一の構成要素からなり、具体的には図2に示すよう
に、入力信号の位相を比較するPLL本体4と、不要な
周波数を減衰させるローパスフィルタ(Law pas
s filter:以下、「LPF」という)5と、チ
ャネル設定を行うVCO(Voltage−contr
olled oscillator)6とを備えている
The first to third PLLs 2a to 2c are all composed of the same components, and specifically, as shown in FIG. 2, they include a PLL main body 4 that compares the phases of input signals, and Low pass filter to attenuate
s filter (hereinafter referred to as "LPF") 5, and a VCO (Voltage-controller) that performs channel settings.
olled oscillator) 6.

【0015】しかして、第1〜第3のPLL2a〜2c
においては、所定のクロック信号に同期してストローブ
信号と共にチャネルデータがライン7を介してPLL本
体4に入力され、このチャネルデータはLPF5により
低周波数域がカットされてVCO6に送られる。一方、
送信データはライン8を介してVCO6に入力される。 そして、VCO6において、チャネルの設定がなされ、
該チャネルに対応して送信データが変調される。
[0015] Therefore, the first to third PLLs 2a to 2c
, channel data is input to the PLL main body 4 via a line 7 along with a strobe signal in synchronization with a predetermined clock signal, and this channel data is sent to a VCO 6 after its low frequency range is cut by an LPF 5. on the other hand,
Transmission data is input to VCO 6 via line 8. Then, in VCO 6, channel settings are made,
Transmission data is modulated in accordance with the channel.

【0016】次いで、VCO6からは送信データを変調
した変調データが出力される一方、該変調データはPL
L本体4に入力され、PLL本体4は、変調データが安
定するのを確認した後、ライン9を介してチャネルロッ
ク信号を出力する。これにより、第1〜第3のPLL2
a〜2cの外部では、チャネル設定が完了したと認識す
る。
Next, the VCO 6 outputs modulated data obtained by modulating the transmission data, while the modulated data is output from the PL
After confirming that the modulated data is stabilized, the PLL main body 4 outputs a channel lock signal via the line 9. As a result, the first to third PLL2
Outside of a to 2c, it is recognized that the channel setting is completed.

【0017】このように構成された無線通信装置では、
図1において例えばCPU1が10ch,1ch,2c
hという順番でこれらのチャネルを使用する場合、CP
U1は第1のPLL2aに10chの設定データ(第1
の設定データ)を送り、次いでセレクタ3の出力が第1
のPLL2aからの出力となるようにPLL選択信号を
セレクタ3に送り、第1のPLL2aのチャネル設定が
完了するのを待つ。一方、第1のPLL2aのチャネル
設定が完了するまでの時間に次に使用する1ch,2c
hをそれぞれ第2、第3のPLL2b,2cに設定する
[0017] In the wireless communication device configured in this way,
In FIG. 1, for example, CPU1 is 10ch, 1ch, 2c
If we use these channels in order h, then CP
U1 sends 10ch setting data (first
setting data), and then the output of selector 3 is
A PLL selection signal is sent to the selector 3 so as to be output from the first PLL 2a, and the channel setting of the first PLL 2a is waited for. On the other hand, during the time until the channel setting of the first PLL 2a is completed, the channels 1ch and 2c to be used next are
h is set in the second and third PLLs 2b and 2c, respectively.

【0018】すなわち、第2の設定データである1ch
の設定データ、及び第3の設定データである2chの設
定データを、夫々第2のPLL2b及び第3のPLL2
cに順次送り、第2、第3のPLL2b,2cに1ch
,2chのチャネル説定を行う。
That is, 1ch which is the second setting data
and the third setting data, 2ch setting data, are transferred to the second PLL 2b and the third PLL 2, respectively.
Sequentially send to c, 1ch to 2nd and 3rd PLL 2b, 2c
, 2ch.

【0019】このように3個のPLLを個別に順次パイ
プライン処理的にチャネル設定をしておくことにより、
図3に示すように、第1のPLL2aにより設定された
チャネル10chの使用が終了した後(図中、送受信時
間をT1で示す)、第2のPLL2bによって設定され
たチャネル1chを待ち時間T2がほとんど無い程度で
続いて使用できる。さらに、チャネル2chについても
上述と同様、チャネル1chの使用後、待ち時間T2が
ほとんど無い程度で続いて使用できる。さらに、第1の
PLL2aにより設定されたチャネル10chによる送
受信が終了した後においても、例えば第3のPLL2c
により設定されたチャネル2chの送受信時間を利用し
て、再び第1のPLL2aが、次に使用するチャネルの
設定を行うことができ、さらにより一層の効率向上を図
ることができる。
By setting the channels of the three PLLs individually and sequentially in pipeline processing in this way,
As shown in FIG. 3, after the use of channel 10ch set by the first PLL 2a is completed (transmission/reception time is indicated by T1 in the figure), the waiting time T2 is reached for channel 1ch set by the second PLL 2b. Can be used continuously with almost no use. Furthermore, as described above, channel 2ch can be used continuously after channel 1ch is used with almost no waiting time T2. Furthermore, even after the transmission and reception by the channel 10 set by the first PLL 2a is completed, for example, the third PLL 2c
By using the transmission/reception time of channel 2ch set by , the first PLL 2a can again set the channel to be used next, and it is possible to further improve efficiency.

【0020】このように、上記実施例では、複数個のP
LLを有効に使い、PLL設定の際に生じる、待ち時間
(送受信できない休止時間)を無視できる程度にまで押
さえられる。したがって、送受信できる回数、及びそれ
に伴う送受信データ量の大幅な増大を可能にしている。
In this way, in the above embodiment, a plurality of P
By using the LL effectively, the waiting time (pause time during which transmission and reception cannot be performed) that occurs when setting the PLL can be suppressed to a negligible level. Therefore, it is possible to significantly increase the number of times that data can be transmitted and received, and the amount of data that can be transmitted and received accordingly.

【0021】図4は他の実施例を示す無線通信装置のブ
ロック構成図であって、PLL制御部10を設け、該P
LL制御部10でチャネル制御を行うことによりCPU
11の負担軽減を図ったものである。
FIG. 4 is a block diagram of a wireless communication device showing another embodiment, in which a PLL control section 10 is provided and the PLL control section 10 is provided.
By performing channel control in the LL control unit 10, the CPU
This is aimed at reducing the burden of 11.

【0022】すなわち、CPU11からの設定データは
、PLL選択信号に基づいて制御されるPLL制御部1
0からの出力信号により、第1〜第3のPLL2a〜2
cのいずれか1個のPLLに設定データが入力され、上
述と同様のチャネル設定が行われる。
That is, the setting data from the CPU 11 is transmitted to the PLL control section 1 which is controlled based on the PLL selection signal.
0, the first to third PLLs 2a to 2
Setting data is input to any one PLL of c, and the same channel setting as described above is performed.

【0023】このようにCPU11の負担を軽減させる
ことにより、より効率のよい環境を実現することができ
る。
By reducing the load on the CPU 11 in this way, a more efficient environment can be realized.

【0024】[0024]

【発明の効果】以上説明したように、本発明は位相同期
回路を用いて送受信用周波数が設定される無線通信装置
において、位相同期回路を複数個備え、前記複数個の位
相同期回路を個別に順次駆動して送受信用周波数を連続
して設定する設定手段を有しているので、送受信用周波
数切り換え時間を無私できる程度にすることができ、次
のような効果がある。 (1)実データ送受信時間の比率が高くなるので、無駄
な待ち時間がなくなり消費電力の節約と、実行スピード
の大幅な向上ができる。 (2)この無駄な待ち時間を本来の作業に回すことがで
き、特に基地局(親機)において、子機移動局(子機)
管理可能な台数が大幅に増加する。 (3)システムの能力を高める上でネックであった、P
LL設定時の待ち時間から開放されることで、システム
アップが容易に行える。
As explained above, the present invention provides a wireless communication device in which transmitting and receiving frequencies are set using phase-locked circuits, which includes a plurality of phase-locked circuits, and individually controls the plurality of phase-locked circuits. Since it has a setting means that sequentially drives and sets the transmitting and receiving frequencies continuously, the time required for switching the transmitting and receiving frequencies can be made selfless, and the following effects are achieved. (1) Since the ratio of actual data transmission and reception time increases, unnecessary waiting time is eliminated, power consumption can be saved, and execution speed can be significantly improved. (2) This wasted waiting time can be diverted to the original work, and especially at the base station (master unit), the handset mobile station (slave unit)
The number of devices that can be managed increases significantly. (3) P, which was a bottleneck in improving the system's ability
By being freed from the waiting time during LL setting, system upgrades can be easily performed.

【0025】さらに、本発明は複数個の位相同期回路に
対し、個別に異なる送受信用周波数が設定されるので、
待ち時間をほとんど有することなく順次異なる送受信用
周波数を使用して無線通信を行うことができる。
Furthermore, in the present invention, since different transmitting and receiving frequencies are set individually for a plurality of phase synchronized circuits,
Wireless communication can be performed using different transmitting and receiving frequencies sequentially with almost no waiting time.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明に係る無線通信装置の一実施例を示すブ
ロック構成図である。
FIG. 1 is a block configuration diagram showing an embodiment of a wireless communication device according to the present invention.

【図2】位相同期回路(PLL)の内部構造を示すブロ
ック図である。
FIG. 2 is a block diagram showing the internal structure of a phase locked loop (PLL).

【図3】チャネル設定と送受信時間及び待ち時間との関
係を示すタイムチャートである。
FIG. 3 is a time chart showing the relationship between channel settings, transmission/reception time, and waiting time.

【図4】他の実施例を示すブロック構成図である。FIG. 4 is a block configuration diagram showing another embodiment.

【図5】従来例のタイムチャートである。FIG. 5 is a time chart of a conventional example.

【符号の説明】[Explanation of symbols]

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  位相同期回路を用いて送受信用周波数
が設定される無線通信装置において、位相同期回路を複
数個備え、前記複数個の位相同期回路を個別に順次駆動
して送受信用周波数を連続して設定する設定手段を有し
ていることを特徴とする無線通信装置。
1. A wireless communication device in which a frequency for transmission and reception is set using a phase-locked circuit, comprising a plurality of phase-locked circuits, and a frequency for transmission and reception is continuously set by sequentially driving the plurality of phase-locked circuits individually. What is claimed is: 1. A wireless communication device characterized by comprising a setting means for setting.
【請求項2】  複数個の位相同期回路に対し、個別に
異なる送受信用周波数が設定されることを特徴とする請
求項1記載の無線通信装置。
2. The wireless communication device according to claim 1, wherein different transmission and reception frequencies are individually set for the plurality of phase synchronized circuits.
JP3138392A 1991-05-14 1991-05-14 Radio communication equipment Pending JPH04336818A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3138392A JPH04336818A (en) 1991-05-14 1991-05-14 Radio communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3138392A JPH04336818A (en) 1991-05-14 1991-05-14 Radio communication equipment

Publications (1)

Publication Number Publication Date
JPH04336818A true JPH04336818A (en) 1992-11-25

Family

ID=15220874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3138392A Pending JPH04336818A (en) 1991-05-14 1991-05-14 Radio communication equipment

Country Status (1)

Country Link
JP (1) JPH04336818A (en)

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