JPH04334204A - Logic circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by reducing operating current at the time of the low-level output of bipolar NTL circuits and the like including pull down MOSFET to rapidly discharge a load capacitance connected with the output terminal of a circuit and reducing the stationary current of a gate array integrated circuit and the like mounting the many bipolar NTL circuits. CONSTITUTION:A diode D2 for a level shift, which has prescribed forward voltage which sets voltage between the drain and the source of pull down MOSFET Q12 to almost zero V when an output signal Sout is set to be constantly in a low level between the output terminal Sout of the circuit and pull down MOSFET Q12 is provided.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to logic circuits, such as bipolar NTL (Non Threshold) mounted as standard cells in gate array integrated circuits, etc.
The present invention relates to technology that is particularly effective when used in Logic (Logic) circuits.

0002

2. Description of the Related Art There is a bipolar NTL circuit that includes a phase divider circuit that receives an input signal and an output emitter follower circuit that transmits an inverted output signal of the phase divider circuit. Furthermore, there are digital integrated circuit devices such as gate array integrated circuits that are equipped with a plurality of such bipolar NTL circuits as standard cells.

Bipolar NTL circuits are described in, for example, Japanese Patent Laid-Open No. 124615/1983.

0004

Prior to the present invention, the inventors of the present application developed a bipolar NTL circuit as shown in FIG. 4, which follows the bipolar NTL circuit described above. That is, in FIG. 4, the bipolar NTL circuit includes a phase division circuit centered on an input transistor T1 that receives an input signal Sin, and an output emitter follower circuit centered on an output transistor T2 that receives an inverted output signal of this phase division circuit. including. The collector load of the input transistor T1 is constituted by a variable impedance circuit consisting of a P-channel MOSFET Q1 that receives the input signal Sin and a diode D1, and the resistor R1 serving as the emitter load has a variable impedance circuit that receives the output signal Sout of the circuit.
Channel MOSFET Q11 is provided in parallel form. In addition, a resistor R2 serving as an emitter load of the output transistor T2 has an N
A channel type pull-down MOSFET Q12 is provided.

When the input signal Sin is at a low level such as -1.3V, the emitter potential of the input transistor T1, that is, the gate potential VG of the pull-down MOSFET Q12 is at a low level such as -2.0V, as shown in FIG. It is considered to be a low level. Therefore, the gate-source voltage VGS becomes 0V since the power supply voltage VTT is -2.0V, and the pull-down MOSFETQ12
is in the off state. At this time, the circuit output signal Sou
t becomes a high level such as -0.8V because the P-channel MOSFET Q1 is turned on, and the drain-source voltage VD of the pull-down MOSFET Q12
S becomes 1.2V. However, pull-down MOSFET
Since the gate-source voltage VGS is 0V, the operating point of Q12 is point E in FIG. 2, and its drain current ID is almost cut off.

On the other hand, when the input signal Sin is set to a high level such as -0.8V, the emitter potential of the input transistor T1, that is, the gate potential VG of the pull-down MOSFET Q12, becomes -1.6V as shown in FIG. It is considered to be a high level such as. Therefore, the gate-source voltage VGS becomes approximately 0.4V, and the pull-down MOS
FETQ12 is turned on. At this time, the output signal Sout of the circuit becomes a low level such as -1.3V with a slight delay because the P-channel MOSFET Q1 is turned off, and the drain-source voltage VDS of the pull-down MOSFET Q12 becomes 0.7V. However, the operating point of the pull-down MOSFET Q12 is at point C in FIG. 2 until the output signal Sout of the circuit is set to a low level, and at point D in FIG. 2 when the output signal Sout of the circuit is set to a stable low level. Transition. When the operating point of pull-down MOSFET Q12 is at point C, its drain current ID becomes a relatively large current value ID2,
This causes the load capacitance coupled to the output terminal Sout of the circuit to be rapidly discharged. Then, the output signal Sout is set to a stable low level and the pull-down MOS
When the operating point of FETQ12 shifts to point D, pull-down MOSFETQ12 does not turn off, but instead flows a drain current ID with a relatively small current value ID3. As a result, while reducing the power consumption of bipolar NTL circuits,
This makes it possible to speed up the operation.

However, it has become clear to the inventors of the present invention that the bipolar NTL circuit shown in FIG. 4 still has the following problems. That is, this bipolar NTL
In the circuit, when the input signal Sin is at a high level and the operating point of the pull-down MOSFET Q12 is at point C, a drain current with a relatively large current value ID2 is caused to flow, so that the load capacitance coupled to the output terminal Sout is almost discharged. Nevertheless, while the input signal Sin is at a high level, the pull-down MOSFET Q12 is turned on and continues to flow a drain current with a relatively small current value ID3. As a result, the steady state current of a gate array integrated circuit or the like equipped with a large number of bipolar NTL circuits increases, which limits the reduction in power consumption thereof.

[0008] The purpose of the present invention is to provide a pull-down MOSFE
The object of the present invention is to reduce the operating current of a bipolar NTL circuit including T at the time of low level output. Another object of the present invention is to reduce the steady-state current of a gate array integrated circuit or the like equipped with a large number of bipolar NTL circuits, thereby promoting lower power consumption.

[0009]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, in a bipolar NTL circuit or the like that is mounted on a gate array integrated circuit or the like and includes a pull-down MOSFET for rapidly discharging a load capacitance coupled to the output terminal of the circuit, there is a gap between the output terminal of the circuit and the pull-down MOSFET. Pull-down MOSFE when the output signal of the circuit is at a stable low level
A level shifting diode having a predetermined forward voltage such that the drain-source voltage of T is approximately 0V is provided.

0010

According to the above means, when the output signal of the circuit is set to a stable low level, the pull-down MOSFET is completely turned off, thereby reducing the operating current when the bipolar NTL circuit outputs a low level. As a result, it is possible to reduce the steady current of a gate array integrated circuit, etc., equipped with a large number of bipolar NTL circuits, and to promote lower power consumption.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit diagram of an embodiment of a bipolar NTL circuit to which the present invention is applied. Also,
FIG. 2 shows an operating characteristic diagram of an embodiment of the pull-down MOSFET Q12 included in the bipolar NTL circuit of FIG. 1, and FIG. 3 shows a signal waveform diagram of an embodiment of the bipolar NTL circuit of FIG. ing. Based on these figures,
An overview of the configuration and operation of the bipolar NTL circuit of this embodiment as well as its characteristics will be described. Incidentally, the bipolar NTL circuit of this embodiment has a large number of similar bipolar NTL circuits.
It is mounted on the gate array integrated circuit together with the TL circuit. Each circuit element in FIG. 1 is formed on a single semiconductor substrate, such as single crystal silicon, along with other circuit elements of a bipolar NTL circuit mounted on a gate array integrated circuit. Also, in the same figure, the channel (back gate)
MOSFET (metal oxide semiconductor field effect transistor; in this specification, MOSFET is a general term for insulated gate field effect transistor).
is a P-channel MOSFET, and is shown to be distinguished from an N-channel MOSFET that is not marked with an arrow. The illustrated transistors (in this specification, bipolar transistors are simply referred to as transistors) are all NPN type bipolar transistors.

In FIG. 1, the bipolar N
The TL circuit includes an input transistor T1 receiving an input signal Sin at its base. Although not particularly limited, there is a connection between the collector of the input transistor T1 and the ground potential (first power supply voltage) of the circuit, but the input signal Sin is connected to the gate of the input transistor T1.
P-channel MOSFET Q1 and diode D
1 are provided in parallel form, and their emitters and power supply voltage VE
A resistor R1 serving as an emitter load and an N-channel MOSFET Q11 are provided in parallel between Ei and Ei. As a result, MOSFET Q1, together with diode D1, constitutes a variable impedance circuit that serves as a collector load of input transistor T1. Also, MOSFETQ1
1 acts, together with resistor R1, as an active emitter load for input transistor T1, and together with input transistor T1 and the variable impedance circuit described above,
A phase division circuit of a bipolar NTL circuit is constructed. The collector potential of the input transistor T1 is an inverted output signal of the phase division circuit, and the emitter potential thereof is a non-inverted output signal of the phase division circuit.

Here, the power supply voltage VEEi of the circuit is -2.
A negative power supply voltage such as 0V is used, and the input signal Sin is
As shown in FIG. 3, it is a relatively small amplitude digital signal with a high level of -0.8V and a low level of -1.3V. Further, the diode D1 is formed based on an NPN type transistor, and has a forward voltage VDF1 corresponding to its base-emitter voltage.

The bipolar NTL circuit further includes an output transistor T2 provided between the circuit's ground potential and the output terminal Sout. The base of this output transistor is coupled to the collector of the input transistor T1, that is, the inverted output node of the phase division circuit, and its emitter, that is, the output terminal Sout of the circuit, is connected to the level shifting diode D2 (level shifting means) in series form and It is coupled to the power supply voltage VTT (second power supply voltage) via an N-channel type pull-down MOSFET Q12. Diode D2 and pull-down MOSFET Q12 include resistor R.
2 are provided in parallel configuration. Pull-down MOSFETQ
The gate of 12 is coupled to the emitter of the input transistor T1, ie the non-inverting output node of the phase divider circuit. This causes output transistor T2 and diode D1 to
and pull-down MOSFET Q12 is a bipolar NT
Configures the output emitter follower circuit of the L circuit. Also,
The pull-down MOSFETQ12 substantially has its gate and drain connected to the MOSFETQ through the diode D2.
As a result, it is cross-coupled with the drain and gate of MOSFET Q11, and together with this MOSFET Q11, a latch type is formed.

In the bipolar NTL circuit of this embodiment, the power supply voltage VTT of the circuit is a negative power supply voltage such as -2.0V, similar to the power supply voltage VEEi described above. Further, the resistor R2 has a relatively large resistance value, and the diode D2 is connected in a predetermined order such that the drain-source voltage VDS of the pull-down MOSFET Q12 is set to 0V when the output signal Sout of the circuit is set to a low level. It is assumed to have a directional voltage. In other words, the power supply voltage VTT
When the absolute values of the low level of the output signal Sout and the output signal Sout are VTT and VOL, respectively, the forward voltage VDF2 of the diode D2 is VDF2 =VTT-VOL, and its value is approximately 0.7V.

When the input signal Sin is at a low level such as -1.3V, in the bipolar NTL circuit, the input transistor T1 is almost turned off, and the MOSFET
Q1 is turned on. Therefore, the input transistor T
The collector potential of MOSFET Q1, that is, the inverted output signal of the phase dividing circuit, is rapidly brought to a high level similar to the ground potential of the circuit by the pull-up action of MOSFET Q1. As a result, the output signal Sout of the circuit is at a high level such as -0.8V, which is lower than the high level of the inverted output signal of the phase dividing circuit by the base-emitter voltage of the output transistor T2, as shown in FIG. It is said that The high level of this output signal Sout is transmitted to a subsequent stage circuit (not shown) and is also transmitted to the drain of the pull-down MOSFET Q12 via a level shift diode D2. As mentioned above, the forward voltage VD of diode D2
F2 is set to 0.7V. Therefore, the drain voltage of pull-down MOSFET Q12 is -1.5V, and there is a drain voltage of 0.5V between the drain and source.
A source-to-source voltage VDS is applied.

At this time, the emitter potential of the input transistor T1, that is, the non-inverted output signal of the phase dividing circuit, that is, the gate voltage VG of the pull-down MOSFET Q12 is as follows.
As shown in FIG. 3, the low level becomes -2.0V, which is lower than the low level of the input signal Sin by the base-emitter voltage of the input transistor T1. Therefore, the gate-source voltage VGS of pull-down MOSFETQ12 becomes 0V, and pull-down MOSFETQ1
2, when the output signal Sout of the circuit is set to a high level such as -0.8V, the drain-source voltage V
Even though DS is set to 0.5V, it is in the off state with point E in FIG. 2 as the operating point. Also, MOSFETQ1
1 is turned on when the output signal Sout of the circuit is set to a high level, but its state transition speed is increased by the latch action with the pull-down MOSFET Q12. The load capacitance coupled to the output terminal Sout of the circuit is rapidly charged via the output transistor T2.

On the other hand, when the input signal Sin is changed to a high level such as -0.8V, in the bipolar NTL circuit, the input transistor T1 is first turned on, and the MO
SFETQ1 is turned off. Therefore, the inverted output signal of the phase dividing circuit is set to a low level such as -VDF1 by the clamping action of the diode D1, and the output signal Sout of the circuit is brought to the base-emitter level of the output transistor T2 with a slight delay from the low level of the inverted output signal. It is set to a low level such as -1.3V, which is lower by the voltage. The low level of the output signal Sout is transmitted to a subsequent stage circuit (not shown) and is also transmitted to the drain of the pull-down MOSFET Q12 via the level shift diode D2. As mentioned above, the forward voltage VDF2 of the diode D2 is set to 0.7V. Therefore, after the output signal Sout reaches a stable low level, the drain voltage of the pull-down MOSFET Q12 is -2
．． 0V, and its drain-source voltage VDS is 0.
It becomes V.

At this time, the emitter potential of the input transistor T1, that is, the gate voltage VG of the pull-down MOSFET Q12 is as shown in FIG.
From the high level of in, the base of input transistor T1
It becomes a high level of -1.6V, which is lower by the emitter voltage. However, the gate-source voltage VGS of pull-down MOSFET Q12 becomes 0.4V, and the pull-down MOSFET Q12 becomes 0.4V.
First, the OSFET Q12 is completely turned on with point A in FIG. 2 as the operating point until the output signal Sout is set to a low level. For this reason, the pull-down MOSFETQ
A drain current ID of a relatively large current value ID1 is caused to flow through the drain terminal 12, and the load capacitance coupled to the output terminal Sout of the circuit is rapidly discharged. Output signal So
When ut reaches a stable low level, the pull-down MO
As mentioned above, since the drain-source voltage VDS is set to 0V, the SFET Q12 is turned off with the operating point at point B in FIG. 2, and the drain current ID is set to 0. As a result, the pull-down MOSFET Q12 performs a substantial impulse operation, as shown in FIG. 3, which makes it possible to maintain the high-speed operation of the bipolar NTL circuit and reduce the operating current during low-level output. Become what you can. As a result, the steady current of a gate array integrated circuit equipped with a large number of bipolar NTL circuits can be reduced, and its power consumption can be reduced.

As shown in the above embodiment, the present invention can be applied to a bipolar N
By applying it to a logic circuit such as a TL circuit, the following effects can be obtained. That is, (1) a bipolar NT including a pull-down MOSFET for rapidly discharging a load capacitance mounted on a gate array integrated circuit or the like and coupled to an output terminal of the circuit;
In L circuits, etc., the circuit output terminal and pull-down MOS
By providing a level shift diode with a predetermined forward voltage between the FET and the MOSFET so that the voltage between the drain and source of the pull-down MOSFET is approximately 0V when the output signal of the circuit is at a stable low level, When the output signal of the circuit is at a stable low level, the voltage between the drain and source of the pull-down MOSFET is set to 0V, and the pull-down MOSFET can be completely turned off. (2) According to the above item (1), the operating current when the bipolar NTL circuit outputs a low level can be reduced while maintaining the high-speed operation of the bipolar NTL circuit. (3) Items (1) and (2) above have the effect of reducing the steady current of gate array integrated circuits, etc. equipped with a large number of bipolar NTL circuits, and promoting lower power consumption. It will be done.

[0021] Above, the invention made by the present inventor has been specifically explained based on examples, but this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is. For example, in FIG. 1, various embodiments may be considered for the configuration of the phase division circuit of the bipolar NTL circuit, such as omitting the resistor R1. Further, a plurality of diodes D2 can be provided depending on the amount of level shift, and other level shift means can also be used. Furthermore, various embodiments may be adopted, such as the specific configuration of the bipolar NTL circuit, the level of each signal, and the polarity and absolute value of the power supply voltage.

[0022] In the above explanation, the invention made by the present inventor was mainly applied to a bipolar NTL circuit mounted on a gate array integrated circuit, which is the background field of application, but the invention is limited thereto. For example, bipolar NTL circuits installed in various high-speed logic integrated circuit devices and similar pull-down M
It can also be applied to various logic gate circuits including OSFETs. The present invention is widely applicable to logic circuits including at least pull-down MOSFETs and digital integrated circuit devices equipped with such logic circuits.

[0023]

Effects of the Invention In a bipolar NTL circuit, etc., which is mounted on a gate array integrated circuit and includes a pull-down MOSFET for rapidly discharging the load capacitance coupled to the output terminal of the circuit, the connection between the output terminal of the circuit and the pull-down MOSFET is improved. In between, by providing a level shift diode with a predetermined forward voltage that makes the voltage between the drain and source of the pull-down MOSFET approximately 0V when the output signal of the circuit is at a stable low level,
When the output signal of the circuit is at a stable low level, the pull-down MOSFET is completely turned off, and the operating current of the bipolar NTL circuit when the bipolar NTL circuit outputs a low level can be reduced. As a result, a large number of bipolar N
It is possible to reduce the steady current of a gate array integrated circuit, etc. equipped with a TL circuit, and promote lower power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a bipolar NTL circuit to which the present invention is applied.

FIG. 2 is an operational characteristic diagram showing an example of a pull-down MOSFET included in the bipolar NTL circuit of FIG. 1;

FIG. 3 is a signal waveform diagram showing one embodiment of the bipolar NTL circuit of FIG. 1;

FIG. 4 is a circuit diagram showing an example of a bipolar NTL circuit developed by the inventors of the present invention prior to the present invention.

FIG. 5 is a signal waveform diagram showing an example of the bipolar NTL circuit of FIG. 4;

[Explanation of symbols]

T1-T2...NTN type bipolar transistor, Q
1...P channel MOSFET, Q11~Q12・
...N-channel MOSFET, D1-D2...diode, R1-R2...resistance.

Claims (3)

[Claims] 1. An input transistor that receives an input signal at its base, an output transistor that is provided between a first power supply voltage and an output terminal of the circuit and that receives a collector potential of the input transistor at its base, and an output of the circuit. A logic circuit comprising level shift means and a pull-down MOSFET provided in series between a terminal and a second power supply voltage. 2. The pull-down MOSFET is an N-channel MOSFET that receives the emitter potential of the input transistor at its gate, and the level shift means shifts the drain level of the pull-down MOSFET when the input signal is at a stable low level. 2. The logic circuit according to claim 1, wherein the logic circuit is a diode having a predetermined forward voltage such that the source-to-source voltage is approximately 0V. 3. The logic circuit according to claim 1, wherein the logic circuit is a bipolar NTL circuit mounted on a gate array integrated circuit.