JPH04329663A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a soft error at the time of writing data while preventing a soft error of stored data by reducing a leakage current to a bit line of each memory cell, etc. CONSTITUTION:A substrate bias circuit 20 can reduce an absolute value of a substrate bias voltage at each memory cell block 12. A substrate bias voltage change selector 30 selects the block 12 corresponding to a memory cell to be selected at the time of writing data. The absolute value of the bias voltage of the block 12 corresponding to the cell to be written with the data is reduced by that circuit 20 the selector 30. Thus, a writing potential of the cell in which the data is written, is obtained.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device in which a substrate bias voltage is applied to at least a memory cell portion, and in particular, the present invention relates to a semiconductor memory device in which a substrate bias voltage is applied to at least a memory cell portion. Regarding improvement of characteristics such as reduction. This soft error caused by alpha rays occurs when the alpha rays incident on the semiconductor substrate generate electron-hole pairs, and these electrons are collected in the memory cell section, destroying information.

0002

2. Description of the Related Art Generally, if an undershoot occurs in the input portion or internal wiring of a semiconductor memory device, which causes the PN junction to move in the forward direction, there is a risk that minority carriers will be injected into the substrate of the semiconductor memory device. be.

Minority carriers injected into the substrate due to such undershoot etc. may increase the substrate potential of a semiconductor memory device using a P-type substrate, for example, and cause a latch-up phenomenon.

Normally, inside a semiconductor memory device,
Design considerations are made to prevent such undershoot from occurring.

However, in the input section of a semiconductor memory device, it is not desirable to provide usage regulations regarding undershoot for the convenience of the user of the semiconductor memory device.

Therefore, even if an undershoot occurs at the input portion of a semiconductor memory device, in order to prevent carriers from being injected into the substrate of the semiconductor memory device, the potential of the substrate is lower than the potential at the expected undershoot. A substrate bias voltage is applied to the substrate of the semiconductor memory device to lower the potential.

[0007] In the case of a P-type substrate, this substrate bias voltage is usually a voltage of about -2 to -3 V with respect to the ground potential.

Furthermore, by applying a substrate bias voltage to the semiconductor memory device in this manner, it is possible to obtain effects such as reducing parasitic capacitance, and the operating speed can be improved.

Furthermore, by applying a substrate bias voltage to the memory cell portion of a semiconductor memory device, it is possible to reduce leakage current to the bit line of each memory cell.

As will be described in detail later with reference to FIG. 3, the threshold voltage Vth changes by biasing the substrate. Hereinafter, this will be referred to as the substrate effect.

[0011]

However, when a substrate bias voltage is applied to the substrate of a semiconductor memory device, when data is written, it is difficult to effectively write data in a memory cell to be written in the semiconductor memory device. There is a problem that the potential decreases.

[0012] If the actual write potential to the memory cell to be written is reduced in this manner, the accumulated charge of the memory cell will be reduced, resulting in a problem that soft errors are likely to occur.

The present invention has been made to solve the above-mentioned conventional problems, and in a semiconductor memory device in which a substrate bias voltage is applied to at least a memory cell portion, when writing data, the memory cell to be written is It is a semiconductor memory that secures write potential to increase accumulated charge and reduce soft errors, and does not increase leakage current to cells in blocks that are not selected for writing. The purpose is to provide equipment.

[0014]

[Means for Accomplishing the Object] The present invention provides a semiconductor memory device in which a substrate bias voltage is applied to at least a memory cell portion, in which the substrate bias voltage is changed for each memory cell block divided into a plurality of blocks. By providing a possible substrate bias means and a substrate bias voltage change selection means for selecting a memory cell block corresponding to a predetermined memory cell and changing the substrate bias voltage when writing data to a predetermined memory cell, The above-mentioned problem has been achieved.

[0015]

[Operation] The present invention provides effects such as reducing leakage current to bit lines of each memory cell by applying a substrate bias voltage to the memory cell portion of a semiconductor memory device. This was done with a focus on

Furthermore, in the present invention, when applying a substrate bias voltage to the memory cell portion of a semiconductor memory device, the larger the substrate bias voltage is, the more the substrate bias voltage becomes This was done based on the discovery that the lower the substrate potential, the lower the actual write potential of each memory cell during data writing.

FIG. 2 is a circuit diagram of a first example of a memory cell for explaining the principle of the present invention.

In FIG. 2, the memory cell includes one inverter composed of an N-channel MOS transistor T1 and a resistor R1, and an N-channel MOS transistor T1.
2 and another inverter consisting of a resistor R2.

That is, the memory cell shown in FIG. 2 is composed of a so-called flip-flop in which the output of each of two inverters is connected to the input of the other inverter.

To write data to such a memory cell, the word line WL is set to the H state, and a total of two N
This is done by turning on both channel MOS transistors T10 and T11.

When a total of two N-channel MOS transistors T10 and T11 are both turned on, nodes a and b are almost conductive, and nodes c and d are almost conductive.
is almost in a conductive state.

Therefore, in such a conductive state, the potential of the node a is made almost equal to the potential of the bit line BLa, and the potential of the node c is also made equal to the potential of the bit line BLb (bit line BL).
The potential is made substantially equal to the potential of bit line pair BLa-BLb, which is the opposite logic state to a, and data is written into the memory cell according to the state of bit line pair BLa-BLb.

At this time, at either node a or c, which is in the H state, charge is accumulated in the parasitic capacitance shown by the broken line in FIG.

As an initial state, in the memory cell shown in FIG. 2, the node a is in the L state, and the node c is in the L state.
Let us consider as an example a case where data is stored such that the data is in the H state, and data is written using the bit line BLa which is in the H state and the bit line BLb which is in the L state.

In this case, the logic state of the memory cell constituted by the flip-flop shown in FIG. 2 is inverted.

In writing data to such a memory cell, for example, the word line WL is first set to the H state, then the bit line BLa is set to the H state, and the bit line BLb is set to the L state.

At this time, the higher the voltage at node a (hereinafter referred to as write voltage Va), the more the charge accumulated in the cell can be increased. Soft errors caused by lines can be reduced.

This write voltage Va is equal to the power supply voltage Vc
Assuming that the voltage at node b of bit line BLa, which is at potential c, is Vb, and the potential of the word line is power supply voltage Vcc, it can be expressed as in the following equation.

Va=Vb-Vth
...(1)

Note that Vth is a threshold voltage.

Here, N channel MOS transistor T
The threshold voltage Vth of No. 10 has characteristics as shown in the graph of FIG.

FIG. 3 shows the relationship between the voltage Vbs between the source and the bulk (well or substrate) to which a substrate bias voltage is applied, and the threshold voltage Vth of an N-channel MOS transistor, and shows the relationship between the so-called substrate effect. This is a graph showing.

In this graph, Vbs1 is the voltage when writing "H" information to node a when the substrate bias voltage is 0V. The threshold voltage of N-channel MOS transistor T10 at this time is Vth1.

[0034] Also, in the graph of Fig. 3, Vbs2
is the bulk-source voltage of N-channel MOS transistor T10 when writing "H" information to node a when a substrate bias voltage is applied, and is higher than voltage Vbs1 by the applied substrate bias voltage. The threshold voltage of N-channel MOS transistor T10 when such a substrate bias voltage is applied is Vth2.

That is, N channel MOS transistor T1
The zero threshold voltage increases as the substrate bias voltage is applied.

Therefore, the threshold voltage Vth2 of this N-channel MOS transistor T10 when the substrate bias voltage is applied is set by the increase in the threshold voltage by Δ
Letting Vth be Vth, the threshold voltage Vth1 when no substrate bias voltage is applied can be expressed as follows.

[0037]Vth2=Vth1+ΔVth
...(2)

Accordingly, from the above equation (1) and this equation (2), the write voltage Va at the node a can be expressed as follows.

[0039]

In this equation (3), the effective write voltage V when writing data to the memory cell shown in FIG.
It can be understood that in order to further increase a and improve the writing characteristics, the voltage ΔVth, which is the increase in the threshold voltage due to the application of the substrate bias voltage, must be made smaller.

That is, in order to increase the substantial write voltage Va, the absolute value of the substrate bias voltage must be reduced.

On the other hand, for the purpose of substrate bias, that is, to reduce parasitic capacitance to achieve high-speed operation, to prevent undershoot and latch-up, etc., the substrate bias voltage is Deeper is better. Further, in order to reduce the subthreshold current in order to prevent a decrease in accumulated charge, it is better to have a higher substrate bias voltage.

FIG. 4 shows an N-channel MOS transistor T.
10 gate voltage Vgs and drain-source current I
d is a graph showing the relationship with d.

In FIG. 4, gate voltage Vgs1 is a voltage that turns off the channel of N-channel MOS transistor T10, and is called the threshold voltage Vth of N-channel MOS transistor T10.

However, as shown in the graph of FIG. 4, even if the gate voltage is below the threshold voltage, a very small drain-source current Id (subthreshold current) flows. Even if the gate voltage is 0V, a subthreshold current exists,
This causes cell leakage current.

In order to reduce the drain-source current (subthreshold current) of such an N-channel MOS transistor when it is in the off state, the threshold voltage is increased.

As described above, the threshold voltage Vth of the N-channel MOS transistor is influenced by the bulk-source voltage Vbs, and increases as the substrate bias voltage becomes deeper.

Therefore, in order to maintain the H state of the data stored in the memory cell and to reduce the subthreshold current, it is desirable that the substrate bias voltage be deep.

As explained above using FIGS. 2 to 4, in order to achieve both the effect of lowering the substrate bias voltage and the effect of increasing the substrate bias voltage, the substrate bias voltage is normally applied. However, it was discovered that the substrate bias voltage of the target memory cell in the memory cell section should be changed when writing data.

That is, in the present invention, each memory cell block divided into a plurality of blocks has substrate bias means capable of changing the substrate bias voltage.

The present invention also includes substrate bias voltage change selection means for selecting a memory cell block corresponding to a predetermined memory cell and changing the substrate bias voltage when writing data to a predetermined memory cell. .

In the present invention, by using these substrate bias means and substrate bias voltage change selection means, only the substrate bias voltage applied to the memory cell block corresponding to the memory cell in which data is being written is changed. That's what I do.

For example, when this substrate bias voltage is applied to a P-type substrate, the absolute value of this substrate bias voltage is made small when writing data.

[0054] As a result, it is usually possible to reduce leakage current to the bit line of a memory cell, secure a substantial write potential when writing data to the memory cell, and improve the write speed. is possible.

Note that the present invention does not limit the structure of the memory cell section divided into a plurality of blocks, and the number of memory cells in each block may be different from each other.

Note that the explanation regarding the substrate bias voltage of semiconductor memory devices up to now applies not only to semiconductor memory devices using memory cells as shown in the circuit diagram of FIG.
The same applies to semiconductor memory devices using other types of memory cells.

For example, as shown in FIG. 5, an inverter includes an N-channel MOS transistor T1 and a P-channel MOS transistor T3, and another inverter includes an N-channel MOS transistor T2 and a P-channel MOS transistor T4. The same applies to semiconductor memory devices using memory cells.

Note that in FIG. 5, the symbols T1 and T2
, T10, T11, WL, BLa, BLb, Vcc
, GND, Va, Vds, Vth, Vgs, Id,
a to d are the same as those with the same symbols in FIG. 2 described above.

[0059]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In FIG. 1, the semiconductor memory device 1 includes:
It is composed of a memory cell section 10, a substrate bias circuit section 20, and a substrate bias voltage change selection section 30.

In the semiconductor memory device 1 of FIG. 1, the memory cell section 10 is composed of a total of four memory cell blocks 12.

The substrate bias circuit section 20 is composed of a total of four substrate bias circuits 22 for each block. These four block-by-block substrate bias circuits 22 are as follows:
It is provided for each of the aforementioned four memory cell blocks 12 in total.

Further, these memory cell blocks 12 can change the substrate bias voltage independently of each other.

The substrate bias voltage change selection section 30 includes a total of four 2-input AND gates 34 and a block selector 3.
2. The block selector 32 is
A total of two address signals A0 and A1 are decoded to select one of the total four outputs when the chip selection signal CE is in an active state.

A total of four outputs of the block selector 32 are input to each memory cell block 12 and also to a two-input AND gate 34.

The two-input AND gate 34 outputs an output to the substrate bias circuit 22 for each block by ANDing the activation state of the signal input from the block selector 32 and the activation state of the write selection signal WE. is selected.

Therefore, in the semiconductor memory device 1 shown in FIG. 1, the chip selection signal CE is activated, and a predetermined memory cell block 12 is selected by a total of two address signals A0 and A1. When the write selection signal WE becomes activated, the memory cell block 12
By the block-by-block substrate bias circuit 22 provided correspondingly, the substrate bias voltage of the selected memory cell block 12 is changed, that is, its absolute value is made smaller.

Therefore, according to the embodiment of the present invention, when writing data to the selected memory cell block 12, the absolute value of the substrate bias voltage of this memory cell block is reduced, and the absolute value of the substrate bias voltage of the memory cell to which data is written is reduced. Substantive write potential (voltage Va in FIGS. 2 and 5 described above)
(equivalent to) can be increased.

On the other hand, a normal deep substrate bias voltage is applied to the other three memory cell blocks 12 that are not selected, and a predetermined voltage is applied by reducing the leakage current to the bit line of each memory cell. It is now possible to obtain the substrate effect of

[0071]

As explained above, according to the present invention, in a semiconductor memory device in which a substrate bias voltage is applied to at least a memory cell portion, when data is written, the write potential to the memory cell to be written is changed. In addition to increasing accumulated charge and reducing soft errors, it is possible to obtain an excellent effect of not increasing leakage current in cell portions of blocks that are not selected for writing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a circuit diagram of a first example of a memory cell for explaining the principle of the present invention.

FIG. 3 is a graph showing the relationship between bulk-source voltage Vbs and threshold voltage Vth of an N-channel MOS transistor used between a memory cell and a bit line.

FIG. 4 is a graph showing the relationship between gate voltage Vgs and drain-source current Id of the N-channel MOS transistor.

FIG. 5 is a circuit diagram of a second example of a memory cell for explaining the principle of the present invention.

[Explanation of symbols]

10... Memory cell section, 12... Memory cell block, 20... Substrate bias circuit section, 22... Substrate bias circuit for each block, 30... Substrate bias voltage change selection section, 32... Block selector, 34... 2-input AND gate, T1, T2, T10, T11...N channel MOS transistor, T3, T4...P channel MOS transistor, R1, R
2...Resistor, WE...Write selection signal, CE...Chip selection signal, A0, A1...Address signal, WL...Word line, BLa, BLb...Bit line, Vcc...Power supply voltage, GND...Ground, Vgs, Vgs1...Gate voltage , Vbs, Vbs1, Vbs2... bulk source voltage,
Vth, Vth1, Vth2...Threshold voltage, I
d, Id 1...Drain-source current, a to d
…node.

Claims (1)

[Claims] 1. A semiconductor memory device configured to apply a substrate bias voltage to at least a memory cell portion, comprising substrate bias means capable of changing a substrate bias voltage for each memory cell block divided into a plurality of blocks; 1. A semiconductor memory device comprising substrate bias voltage change selection means for selecting a memory cell block corresponding to a memory cell and changing a substrate bias voltage when data is written to the memory cell.