JPH04326811A - Integration circuit - Google Patents

Abstract

PURPOSE:To prevent the output signal of the integration circuit from being affected by noise mixed into an input signal. CONSTITUTION:When the input signal is at an H level, a capacitor C is charged from a current source 11 through a switch SW1. When the input signal is turned to an L level, the switch SW1 is changed over and the electric charge of the capacitor C1 is discharged through a current source 21. The terminal voltage of the capacitor C is compared with a reference voltage by a comparator 13. The output signal of the comparator 13 is the output signal of the integration circuit. A switch SW3 to select either the current source 11 or a power supply voltage Vcc, a switch SW4 to select either the current source 21 or a ground and an EOR gate 14 are provided. When the both output signal and input signal are at the H level or the L level, the power supply voltage Vcc and the ground are selected by the switches SW3 and SW4, and rapid reset is executed against noise.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrating circuit that delays the edges (rising and falling, or leading and trailing edges) of an input binary digital signal.

0002

2. Description of the Related Art A conventional integrating circuit is shown in FIG. 6, and its operation is shown in FIG. 7.

First, referring to FIG. 6, the integrating circuit is composed of a charging/discharging circuit and a level discrimination circuit.

The charging/discharging circuit includes a charging/discharging capacitor C, a current source 11 that supplies a current I1 for charging the capacitor C, a current source 21 that draws the current discharged from the capacitor C as a constant current I2, and It is composed of a switching element SW1 that switches the connection of these current sources 11 or 21 to the capacitor C.

[0005] Switching element SW1 is controlled by a binary input signal having an H level and an L level. When the input signal becomes H level, the current source 11 is connected to the capacitor C, and the capacitor C is charged by the current I1. When the input signal becomes L level, the capacitor C is connected to the current source 21, and the charge stored in the capacitor C is discharged as a current I2.

The level discrimination circuit includes a comparator 13. The terminal voltage of the capacitor C is input to the positive input terminal of the comparator 13. A threshold voltage is applied to the negative input terminal of the comparator 13. This threshold voltage has hysteresis characteristics. 3
Three resistors R1, R2, and R3 are connected in series, and a predetermined constant voltage E (power supply voltage or stabilized voltage) is applied to this series circuit. Resistors R1 and R2
The connection point is connected to the negative input terminal of the comparator 13. A switching element SW2 is connected in parallel to the resistor R3. This switching element SW2 is controlled by the output signal of the comparator 13 (which becomes the output signal of the integrating circuit). When the output signal is at the L level, the switching element SW2 is off, and the threshold voltage applied to the negative input terminal of the comparator 13 is E・(
It is given by R2 +R3 )/(R1 +R2 +R3). When the output signal becomes H level, switching element SW2 turns on, so the threshold voltage becomes E.
R2/(R1 +R2), which is a relatively low level.

Referring to FIG. 7, when the input signal changes from L level to H level, current I1 is supplied from current source 11 to capacitor C, and capacitor C is charged. When the terminal voltage of capacitor C reaches a relatively high threshold level, the output signal of comparator 13 is inverted from L level to H level. Assuming that the relatively high threshold level is V1 and the capacitance of capacitor C is C, the rising edge (leading edge) of the input signal is T.
It appears as the rising edge of the output signal after being delayed by a time given by 1 = C·V1 /I1.

When the input signal is reversed from H level to L level after the terminal voltage of capacitor C reaches the highest potential,
The charge on capacitor C is discharged through current source 21 with current I2. If the difference between the highest potential of the terminal voltage of capacitor C and a relatively low threshold level is V2, the falling edge (trailing edge) of the input signal is T.
It appears as a falling edge of the output signal after being delayed by a time given by 2 = C·V2 /I2.

[0009]

[Problem to be Solved by the Invention] In the conventional integrating circuit as described above, the pulse width is determined by the delay time T1 or T
When noise narrower than 2 is mixed in, the continuation of this noise pulse causes the capacitor C
There is a problem in that charging to or discharging from the capacitor C occurs in stages, resulting in erroneous pulses being included in the output signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrating circuit that generates a correct output signal that is not affected by noise even if noise is mixed into an input signal.

[0011]

[Means for Solving the Problems] The present invention provides a charging/discharging circuit, a switching circuit that switches the charging/discharging operation of the charging/discharging circuit according to the level of a binary input signal, and a switching circuit that controls the charging/discharging voltage of the charging/discharging circuit at a predetermined level. an exclusive OR circuit that takes the exclusive OR of the input signal and the output signal, and , and a time constant switching circuit that switches the charging/discharging time constant of the charging/discharging circuit to be relatively small when the input signal and the output signal are at the same level, according to the output of the exclusive OR circuit. It is characterized by having the following.

0012

[Operation] When the level of the input signal and the level of the output signal are the same, that is, when the charging/discharging voltage of the charging/discharging circuit is at the highest or lowest potential, noise is mixed into the input signal, and this noise causes the charging/discharging circuit to Even if the input signal is discharged or charged for a short period of time, the charging/discharging time constant of the charging/discharging circuit is switched to a relatively small value when the input signal returns to its original level, so the charging/discharging voltage of the charging/discharging circuit remains the same as before. Instantly reset to the highest or lowest potential. This prevents the charging/discharging voltage from changing stepwise even if noise with a time width smaller than the delay time is continuously input.

[0013]

As described above, even if noise is mixed into the input signal, no erroneous pulses will appear in the output signal, and a correct output signal unaffected by noise can be obtained.

[0014]

[Embodiment] Fig. 1 shows an integrating circuit according to an embodiment of the present invention.
FIG. 2 shows its operation. In these figures, the same reference numerals are given to the parts shown in FIGS. 6 and 7 to avoid redundant explanation.

In FIG. 1, when compared with the circuit shown in FIG. 6, there are switching elements SW3 and SW4 for changing the charging/discharging time constant of the charging/discharging circuit, and E for controlling switching of these switching elements SW3, SW4.
An OR gate (exclusive OR circuit) 14 is provided.

The switching element SW3 is connected to the current source 1.
1 and the short circuit connected to the power supply voltage VCC are selectively connected to one input terminal of the switching element SW1. The switching element SW4 is connected to the current source 2.
Either one of the short circuits connected to 1 and earth (ground) is selectively connected to the other input terminal of switching element SW1.

The EOR gate 14 receives the input signal of this integrating circuit and the output signal of the comparator 13 as input. E
When the output of the OR gate 14 is at the H level, the switching elements SW3 and SW4 select the current sources 11 and 21, respectively, and when the output is at the L level, they select the short circuit, respectively.

Referring to FIG. 2, when both the input signal and the output signal are at L level, the output of EOR gate 14 is at L level.
At the level, both switching elements SW3 and SW4 select the short circuit.

When the input signal rises to H level in this state, the output of EOR gate 14 becomes H level, so current source 11,
21 are selected respectively. Also, switching element SW
1 selects the current source 11, so the capacitor C
Charging is performed by current I1.

When the terminal voltage of capacitor C reaches a relatively high threshold level, comparator 13
Since the output signal of EOR gate 14 becomes H level, the output of EOR gate 14 becomes L level. This causes switching elements SW3 and SW4 to select a short circuit. Since the state of the switching element SW1 does not change, the capacitor C is rapidly charged by the power supply voltage through a short circuit.

After the terminal voltage of the capacitor C is maintained at the highest potential (power supply voltage), when the input signal is inverted to L level, the output of the EOR gate 14 is also inverted to H level, so the current is controlled by switching elements SW3 and SW4. Source 11
, 21 are selected, respectively. Since the switching element SW1 selects the current source 21 by inverting the input signal,
Capacitor C is discharged by current I2. When the terminal voltage of capacitor C reaches a relatively low threshold level, the output signal of comparator 13 becomes L level. Since the output of the EOR gate 14 also becomes L level, switching elements SW3 and SW4 select a short circuit. Since the switching element SW1 is held in the previous state, the charge on the capacitor C is rapidly discharged to the ground and becomes the lowest potential (zero).

According to the integrating circuit shown in FIG. 1, as shown in FIG. 3, even if noise is mixed into the input signal, the effect thereof does not appear on the output signal.

In other words, if we consider the case where narrow noise is mixed into the input signal when both the input and output signals are at the L level, charging of the capacitor C starts due to the H level of the noise, but when the noise disappears and the input When the signal returns to the L level, the output of the EOR gate 14 becomes the L level, so the charge stored in the capacitor C is transferred to the switching element S.
It is rapidly discharged via W4 and the short circuit connected thereto, and the terminal voltage of capacitor C returns to its lowest potential.

[0024] Also, considering the case where narrow noise is mixed into the input signal when both the input and output signals are at H level,
Discharging from the capacitor C starts due to the L level of noise, but when the noise disappears and the input signal returns to H level, the output of the EOR gate 14 becomes L level.
The capacitor C is rapidly charged through the switching element SW3 and the short circuit connected to it, and the capacitor C
The terminal voltage returns to the highest potential.

In this way, even if the level of the input signal is instantaneously reversed due to noise being mixed into the input signal, the voltage of capacitor C will instantaneously return to its original level when the input signal level returns to its original level. Reset to voltage (highest potential or lowest potential). Therefore, even if pulsed noise with a width narrower than the delay time T1 or T2 is continuously mixed in, the charge in the capacitor C will not be charged or discharged in stages as in the conventional case.

FIG. 4 shows a modification.

The two charging circuits selected by switching element SW3 are composed of current sources 11 and 12 of currents I11 and I12, respectively. Here, current source 1
The current I12 of the current source 11 is much larger than the current I11 of the current source 11. The two discharge circuits selected by the switching element SW4 have currents I21 and I22, respectively.
It is composed of current sources 21 and 22. Here, the current I22 of the current source 22 is much larger than the current I21 of the current source 21. Even with such a configuration, the same operation as described above is performed.

FIG. 5 shows another modification.

The two charging circuits selected by the switching element SW3 include resistors R11 and R12, respectively.
It is included. The resistance value of resistor R12 is much smaller than the resistance value of resistor R11. Each of the two discharge circuits selected by the switching element SW4 has a resistor R2.
1 and R22. The resistance value of resistor R22 is much smaller than the resistance value of resistor R21. Even with such a configuration, the same operation as described above is performed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an integrating circuit according to an embodiment of the invention.

FIG. 2 is a waveform diagram showing the operation of the integrating circuit shown in FIG. 1;

FIG. 3 is a waveform diagram showing that the output signal of the integrating circuit shown in FIG. 1 is not affected by noise mixed into the input signal.

FIG. 4 is a circuit diagram showing a modification of the invention.

FIG. 5 is a circuit diagram showing another modification of the invention.

FIG. 6 is a circuit diagram showing a conventional integration circuit.

7 is a waveform diagram showing the operation of the conventional integrating circuit shown in FIG. 6. FIG.

FIG. 8 is a waveform diagram showing that the output signal of the conventional integrating circuit shown in FIG. 6 is affected by noise mixed into the input signal.

[Explanation of symbols]

11, 12, 21, 22 Current source 13 Comparator 14 EOR gate C Capacitor

Claims (6)

[Claims] [Claim 1] A charging/discharging circuit, a switching circuit that switches the charging/discharging operation of the charging/discharging circuit according to the level of a binary input signal, and a switching circuit that compares the charging/discharging voltage of the charging/discharging circuit with a predetermined reference voltage. In an integrating circuit consisting of a comparison circuit that generates a binary output signal according to the comparison result,
An exclusive OR circuit that takes an exclusive OR of the input signal and the output signal, and the charging and discharging when the input signal and the output signal are at the same level according to the output of the exclusive OR circuit. An integrating circuit characterized by being provided with a time constant switching circuit that switches the charging/discharging time constant of the circuit so that it becomes relatively small. 2. A charging/discharging capacitor, first and second charging circuits having different time constants for charging the capacitor, first and second discharging circuits having different time constants for discharging the capacitor, and a binary input signal. Depending on the level, the first
and a first switching circuit that switches the connection of the second charging circuit and the first and second discharging circuits to the capacitor, which compares the terminal voltage of the capacitor with a predetermined reference voltage and responds to the comparison result. a comparison circuit that generates a binary output signal, a second switching circuit that switches connection of the first charging circuit and the second charging circuit to the capacitor, and the first discharging circuit and the second discharging circuit. a third switching circuit for switching the connection of the to the capacitor;
and a logic circuit that controls the second and third switching circuits according to the levels of the input signal and the output signal. 3. The integrating circuit according to claim 2, wherein one of the first and second charging circuits and one of the first and second discharging circuits are short circuits. 4. The first and second charging circuits are composed of current sources, and the magnitudes of the currents are mutually different, and the first and second discharging circuits are composed of current sources, and the magnitudes of the currents are mutually different. 3. The integrating circuit according to claim 2, wherein the integrating circuit is different from the above. 5. Claim 2, wherein the first and second charging circuits each include a resistor with a different resistance value, and the first and second discharge circuit each include a resistor with a different resistance value. Integrator circuit described in . 6. The integrating circuit according to claim 2, wherein the comparison circuit includes a hysteresis generation circuit that changes the reference voltage according to the state of its output signal.