JPH04326227A - High-speed line controller - Google Patents

Abstract

PURPOSE:To prevent reception over-run from occurring in the case of inter- network connection concerning the high-speed line controller to control data transfer with a high-speed communication network and mutually between networks while being positioned between the high-speed communication network and a host processor through a transmission line. CONSTITUTION:All the plural buffer memories are provided with the same capacity and same address space, a buffer memory control information storing means 15 is provided to store control information for each address of the plural buffer memories so as to show which buffer memory stores valid data, and connection control means 11, 12 and 13 are provided to connect a path with the prescribed buffer memory in the case of writing the data in the buffer memory, to write the correspondent control information in the buffer memory control information storing means 15 and to connect a path with the buffer memory corresponding to the control information read out of the buffer memory control information storing means 15 in the case of reading the data from the buffer memory.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention is located between a communication network (high-speed communication network) that performs high-speed data transfer via a transmission path and a higher-level processing device, The present invention relates to a high-speed line control device that performs data transfer control. moreover,
The present invention relates to a high-speed line control device that controls data transfer between a plurality of terminals connected via a plurality of high-speed communication networks and a higher-level processing device.

0002

2. Description of the Related Art Conventional line interface control for transmitting and receiving data between a high-speed communication network and a higher-level processing device is performed by individual high-speed line control devices that are compatible with line interfaces specific to the communication network. FIG. 8 is a block diagram showing an example of the overall configuration of a system using a conventional high-speed line control device.

[0003] In the figure, a high-speed line control device 83 is connected to a high-speed communication network 81 via a transmission path 82, and a higher-level processing device 84 is further connected to the high-speed communication network 81. Further, a plurality of terminals 85 are connected via the transmission path 82. High-speed line control device 8
3 is provided with a network interface control unit 86 corresponding to each line interface, and controls data transfer respectively.

[0004] In recent years, the number of types of high-speed communication networks has increased, and with the spread of these networks, the demand for inter-network connections has increased. In the conventional high-speed line control device shown in FIG. It was being processed. However, the upper processing device 8
In order to avoid placing a load on the network interface controllers 861 and 862, one high-speed line control device 83-1 accommodates a plurality of high-speed lines, as shown by the broken line data transfer path in FIG. It has become necessary to perform data transfer control through bridge connections.

FIG. 10 is a block diagram showing an example of the configuration of a high-speed line control device that controls two high-speed lines. In the figure, the internal bus 91 includes a network interface control unit 861 that supports a plurality of n (in this case, n=2) high-speed lines.
862, a higher-level interface processing section 92 that processes the interface with the higher-level processing device 84, a protocol processing section 93 that performs protocol control in common to the line, and a buffer memory (BM) 9 that temporarily stores transmitted and received data.
4 is connected. The line speed is 1/1/2 compared to the speed of the internal bus 91, that is, the access speed of the buffer memory 94.
In the case of less than n, network interface control units 861 and 862 for transferring data between the line and the buffer memory 94 may be provided for each line as shown in FIG.

However, when the line speed becomes faster and becomes almost equal to the access speed of the buffer memory 94, as shown in FIG. bus 9
11, 912 and buffer memories 941, 94
2 is required. That is, for each line, a network interface control unit 861 and a buffer memory 941, a network interface control unit 862 and a buffer memory 942 are connected to internal buses 911 and 9, respectively.
12, and is configured to provide a bridge connection between high-speed communication networks. At the time of bridge connection, the inter-BM data transfer processing unit 95 is connected to each internal bus 911 , 912 and controls data transfer between the buffer memories 941 , 942 . Figure 1
1 broken line arrows ■, ■, ■ indicate the network interface control unit 8
61 to the network interface control unit 862.

[0007] In recent years, CSMA/
CD, LAN, token bus LAN, token ring L
AN, FDDI, B-ISDN, and others are popular.

[0008]

By the way, in the high-speed line control device 83b having the configuration shown in FIG. 11, a dedicated internal bus and buffer memory are provided for each line, so when connecting between networks, once received data is It is necessary to transfer the data to the buffer memory corresponding to the network interface control unit (dashed arrow ■). Therefore, during this time, the data received from the line cannot be transferred to the buffer memory.
As a result, writing to the buffer memory may be delayed, leading to the possibility that received data may be discarded. The state of data discard indicated by the broken line arrow ■ in FIG. 11 indicates the occurrence of this reception overrun.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed line control device that can avoid reception overruns in bridge connections between high-speed communication networks.

0010

[Means for Solving the Problems] The present invention accommodates a plurality of lines having a predetermined line speed between a transmission line connected to a high-speed communication network and a host processing device, and transmits and receives data for each line. A network interface control unit that performs transfer processing, a protocol processing unit that performs common protocol control over lines, an upper interface processing unit that performs interface control with the upper processing device, and data transmitted and received via the network interface control unit. and a plurality of buffer memories for temporarily storing data, and controls data transfer between the network interface control units or between the network interface control unit and the upper interface processing unit via the buffer memory. In the high-speed line control device, all of the plurality of buffer memories have the same capacity and the same address space, and control information indicating which buffer memory stores valid data is stored for each address of the plurality of buffer memories. Connecting a path between the buffer memory control information storage means to be stored and a predetermined buffer memory when writing data to the buffer memory, corresponding to each of the network interface control unit, protocol processing unit, and upper interface processing unit. At the same time, corresponding control information is written in the buffer memory control information storage means, and a path is connected to the buffer memory according to the control information read from the buffer memory control information storage means when reading data from the buffer memory. The present invention is characterized by comprising a connection control means.

[0011]

[Operation] A write operation from the network interface control unit to an arbitrary address in the buffer memory is performed to the buffer memory that is connected one-to-one to the network interface control unit via the connection control means. At this time, it also accesses the buffer memory control information storage means and writes control information indicating in which buffer memory the data is stored. Therefore, even if a request to transfer received data is issued to each network interface control unit, the data can be transferred to the corresponding buffer memory.

[0012] Furthermore, the data read operation from an arbitrary address in the buffer memory to the network interface control unit is as follows:
The connection control means retrieves control information indicating in which buffer memory the data at the address is stored from the buffer memory control information storage means, and connects the path between the corresponding buffer memory and the network interface control unit. The network interface control unit can read the requested data through conventional internal bus interface processing.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an embodiment of a high-speed line control device according to the present invention. In the figure, a plurality n(
Here, network interface control units 861, 862 and internal buses 911, 9 corresponding to high-speed lines (n=2)
It has 12. This network interface control unit 861
, 862 , a higher-level interface processing section 92 that processes the interface with the higher-level processing device 84 , and a protocol processing section 93 that performs common protocol control for the lines, connect to the internal buses 911 , 862 via the bus connection control sections 11 , 12 , and 13 , respectively. 912. Furthermore, each internal bus 911, 912 has buffer memories (BM) 141, 14 for temporarily storing transmitted and received data.
2 and the BM control information storage section 15 are connected.

Note that the buffer memories 141 and 142
have the same capacity and the same address space, and the BM control information storage unit 15 includes buffer memories 141 and 142.
Control information indicating where valid data is stored is stored. In addition, bus connection control units 11, 12,
13 are network interface control units 861 and 8, respectively.
62, the upper interface processing section 92 and the protocol processing section 93 decide which of the buffer memories 141, 142 to access based on the information in the BM control information storage section 15, and access the corresponding internal buses 911, 912.
Control connection/disconnection with.

Now, referring to FIG. 2, the operation when receiving data from the transmission path to the network interface control units 861 and 862 will be described. The bus connection control unit 11 connects the network interface control units 861 and 862 and the internal bus 91.
1 and 912 are connected one to one, respectively. Therefore, for example, the network interface control unit 861 stores the received data at a predetermined address in the buffer memory 141 via the internal bus 911 currently connected by the bus connection control unit 11 (dashed arrow ■). Also, at the same time as writing to the buffer memory 141 , the buffer memory 141 ,
Control information indicating which of the 142 write operations has been performed is written (broken arrow ■). On the other hand, the network interface control unit 862 similarly stores the received data at a predetermined address in the buffer memory 142 via the internal bus 912 (dashed arrow ■), and at the same time stores the received data at the corresponding address in the BM control information storage unit 15. control information is written (dashed arrow ■).

In this way, by always exclusively connecting the internal buses 911 and 912 in the bus connection control section 11, even if a request to transfer received data occurs to the network interface control sections 861 and 862 at the same time, Data can be transferred to the corresponding buffer memory without making each one wait. FIG. 3 shows each buffer memory 14
1, 142 and the state of the BM control information storage unit 15. FIG. That is, each buffer memory 141,
The data stored for each address A0, A1, A2, ... of 142 is indicated by diagonal lines, and the data stored in the BM control information storage unit 15 corresponding to each address is "0" if stored in the buffer memory 141; If it is stored in the memory 142, "1" is set.

Next, referring to FIG. 4, the operation when data is transmitted from the network interface control units 861 and 862 to the outside will be described. Each network interface control unit 861
, 862 reads data from any address in each buffer memory 141 , 142 and transmits it to the outside, it also accesses the BM control information storage section 15 and the bus connection control section 11 Control information indicating which buffer memory stores the data at the address is fetched from the network interface control unit, and a path is set so that the network interface control unit is connected to the target buffer memory.

That is, each internal bus 911, 912
If both are not being accessed, for example, the network interface control unit 862 connects the BM via the bus connection control unit 11.
Control information storage unit 15 and each buffer memory 141,
142 (dashed arrow ■). At this time, each buffer memory 141, 142
A ready signal is output from the network interface controller 862 to the network interface controller 862. The bus connection control unit 11 temporarily suspends each ready signal, and based on the control information of the corresponding address in the BM control information storage unit 15 (dashed arrow ■), transfers the data to the buffer memory 141 on the side where the data is stored. The connection destination of the network interface control unit 862 is switched to the internal bus 911 so that the network interface control unit 862 is connected to the network interface control unit 862. Note that at this time, the network interface control unit 8
61 is connected to internal bus 912. Thereafter, the network interface control unit 862 stores the buffer memory 14.
1, the corresponding data and response signal are transferred and data transmission is performed (dashed arrow ■).

Further, as shown in FIG. 5, if one of the internal buses 912 is being accessed, the network interface control unit 862 connects the BM control information storage unit 15 via the bus connection control unit 11 to the accessed internal bus 912. The read address is output to the buffer memory 141 on the side that is not being read (dashed arrow ■). At this time, the buffer memory 141
A ready signal is output from the network interface controller 862 to the network interface controller 862. The bus connection control unit 11 indicates, based on the control information for the address in the BM control information storage unit 15 (dashed arrow ■), that the data at the address is in the buffer memory 141 on the side that is not being accessed. If so, pass the ready signal as is and transfer it to buffer memory 1.
41, the corresponding data and response signal are transferred, and data transmission is performed. However, if the bus connection control unit 11 indicates that the data at the address is in the buffer memory 142 on the side being accessed,
It waits until the internal bus 912 to which the buffer memory 142 is connected is free and the data output is confirmed.

In this manner, the bus connection control section 11 sets paths for connecting each buffer memory 141 , 142 and each network interface control section 861 , 862 based on the output information from the BM control information storage section 15 . By doing so, each network interface control unit 861, 862
can read data from the buffer memory using conventional internal bus interface processing without being aware of the existence of multiple buses. That is, through the series of processes described above, the network interface control unit 861
A bridge connection between the network interface controller 862 and the network interface controller 862 can be realized without data transfer between buffer memories.

Now, referring to FIG. 6, a procedure for transferring data received by the network interface control section 862 to the upper interface processing section 92 will be explained. In the network interface control unit 862, as explained in FIG.
The bus connection control unit 11 writes the received data to the currently connected buffer memory 142 (dashed arrow ■),
The corresponding control information is set in the BM control information storage section 15 (broken arrow ■). Next, the protocol processing unit 93 receives a notification of data reception from the network interface control unit 862 (dashed arrow ■), and after completing the line-compatible protocol processing, the upper-level interface processing unit 92 sends the data to the upper-level processing device 84. Instructs data transfer (dashed arrow ■). Upon receiving this, the higher-level interface processing unit 92 performs a read operation on the buffer memories 141 and 142 in order to transfer the data to the higher-level processing device 84 (
dashed arrow ■). Note that the procedure is the same as the read procedure to the network interface control units 861 and 862 described above, and the network interface control units 861 and 862 and the bus connection control unit 11 in FIGS. The same explanation can be given by replacing the bus connection control unit 92 with the bus connection control unit 12.

Next, referring to FIG. 7, a procedure for transmitting data from the upper interface processing section 92 to the network interface control section 862 will be explained. In the upper interface processing unit 92, the network interface control unit 8 in FIG.
61, 862 to buffer memory 141, 142
Similarly to the data writing procedure to the bus connection control unit 1,
In step 2, the data to be transmitted is written in the currently connected buffer memory 141 (dashed arrow ■), and the corresponding control information is set in the BM control information storage section 15 (dashed arrow ■). Next, the protocol processing unit 93 receives an instruction to send data from the upper interface processing unit 92 (dashed arrow ■),
After completion of line-compatible protocol processing, data transmission is instructed to the network interface control unit 862 that controls the line for transmission (dashed arrow ■). Upon receiving this, the network interface control unit 862 performs a read operation on the buffer memories 141 and 142 according to the procedure explained in FIGS. 4 and 5 (broken line arrow ■) in order to transmit the data.

Note that in the embodiment described above, the number of network interface control units 86 and the number of buffer memories 14 are both two depending on the high-speed line to be accommodated, but these numbers do not have to match each other. , is larger than 2, the device of the present invention can be similarly realized.

[0024]

[Effects of the Invention] As explained above, the present invention enables switching of connections between a plurality of network interface control units and a buffer memory using a connection control means (bus connection control unit).
Data transfer can be performed directly from a plurality of network interface control units to any buffer memory. Therefore, data transfer between buffer memories is no longer necessary in inter-network connections, and furthermore, even if one network interface control unit is in the process of transmitting, another network interface control unit can perform reception processing, which prevents the occurrence of reception overruns. can be easily avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a high-speed line control device of the present invention.

FIG. 2 is a diagram illustrating an operation when receiving data to a network interface control unit.

FIG. 3 is a diagram showing the states of a buffer memory and a BM control information storage section when receiving data.

FIG. 4 is a diagram illustrating the operating state when data is transmitted from the network interface control unit to the outside.

FIG. 5 is a diagram illustrating the operating state when data is transmitted from the network interface control unit to the outside.

FIG. 6 is a diagram illustrating a data transfer procedure from a network interface control unit to a higher-level interface processing unit.

FIG. 7 is a diagram illustrating a data transfer procedure from a higher-level interface processing unit to a network interface control unit.

FIG. 8 is a block diagram showing an example of the overall configuration of a system using a conventional high-speed line control device.

FIG. 9 is a block diagram showing another example of the overall configuration of a system using a conventional high-speed line control device.

FIG. 10 is a block diagram showing a configuration example of a high-speed line control device that controls two high-speed lines.

FIG. 11 is a block diagram showing another configuration example of a high-speed line control device that controls two high-speed lines.

[Explanation of symbols]

11, 12, 13 Bus connection control section 14 Buffer memory (BM) 15 BM control information storage section 81 High-speed communication network 82 Transmission lines 83, 83a, 83b High-speed line control device 84 Upper processing device 85 Terminal 86 Network interface control section 91 Internal Bus 92 Upper interface processing section 93 Protocol processing section 94 Buffer memory (BM) 95 Inter-BM data transfer processing section

Claims (1)

[Claims] Claim 1: A network interface control unit that accommodates a plurality of lines having a predetermined line speed between a transmission path connected to a high-speed communication network and a higher-level processing device, and performs transfer processing of transmitted and received data for each line. a protocol processing unit that performs common protocol control over the line; an upper interface processing unit that performs interface control with the upper processing device; and a plurality of buffer memories that temporarily store data transmitted and received via the network interface control unit. and controlling data transfer between the network interface control units or between the network interface control unit and the upper interface processing unit via the buffer memory, wherein the plurality of All of the buffer memories have the same capacity and the same address space, and buffer memory control information storage means stores control information indicating which buffer memory stores valid data for each address of the plurality of buffer memories. and, corresponding to each of the network interface control unit, protocol processing unit, and upper interface processing unit, connect a path to a predetermined buffer memory when writing data to the buffer memory, and write corresponding control information to the above-mentioned buffer memory. connection control means for connecting a path with the buffer memory according to control information written in the buffer memory control information storage means and read from the buffer memory control information storage means when reading data from the buffer memory; A high-speed line control device featuring: