JPH0432551B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device using a non-single crystal semiconductor, particularly an intrinsic or artificial semiconductor device having a photovoltaic generation semiconductor layer (hereinafter simply referred to as an active semiconductor layer) that generates electron/hole pairs upon irradiation with light. An IN ^- junction is formed by laminating a so-called substantially intrinsic semiconductor layer (hereinafter simply referred to as an I layer or an intrinsic semiconductor layer) to which no P or N type impurity is added in a layered manner and a P type or N type semiconductor layer. The present invention relates to semiconductor devices.

In the present invention, the photoelectric conversion device is operated from the light irradiation surface side.
The purpose of the PIN ^- N junction is to substantially lengthen the lifetime of minority carriers in the active semiconductor layer, thereby providing a large current output.

In the present invention, when stacking the first, second, third, and fourth non-single crystal semiconductor layers to form a PIN ^- N junction, these semiconductor layers are not manufactured using the same reaction chamber. After forming a first semiconductor layer by connecting four independent reaction chambers, a substrate having a surface to be formed in an adjacent reaction chamber is placed on the first semiconductor layer without exposing it to the atmosphere. Second
By gradually repeating this process, a second semiconductor layer is formed on the first semiconductor layer, a third semiconductor layer is formed on the second semiconductor layer, and a third semiconductor layer is formed on the second semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device in which a fourth semiconductor layer is formed on a semiconductor layer.

The present invention relates to a method for manufacturing a semiconductor device having four reaction chambers connected to each other. The purpose is to provide a first preliminary chamber for isolation from the atmosphere and a second preliminary chamber for preliminary heating to remove adsorbed substances on the substrate so that there is no contamination with the atmosphere (air, especially oxygen and water). It is said that

Regarding a photoelectric conversion device that utilizes a conventional plasma CVD method, particularly a glow discharge method, and has a PIN junction by a lamination method, there is an application filed by the present inventor entitled "Semiconductor layer for photovoltaic power generation" (filed on June 20, 2013, published in Japanese Patent Application Laid-Open No. 51-890 (Japanese Patent Application No. 49-71739) is known. A semiconductor device (Japanese Unexamined Patent Publication No. 52-16990) is also known. However, although they point out that the I layer as an active semiconductor layer in these semiconductor devices has a lower impurity concentration than the P or N type semiconductor layers that sandwich the I layer, they do not disclose the details at all. I haven't.

In the present invention, in a photoelectric conversion device manufactured by laminating a semiconductor layer on a surface to be formed, as a result of further study of this active semiconductor layer, the interior of the active semiconductor layer is an I-type semiconductor with an impurity concentration of 5×10 ¹⁶ cm ^-3 or less. layer and 7x
P- or N-type semiconductor layers doped with impurities at a concentration of 10 ¹⁶ to 1 x 10 ¹⁸ cm ^-3 are stacked in separate reaction chambers to prevent impurities from mixing with each other. It is a feature. As a result, this active semiconductor layer is stacked against electrons or holes, and a minority of carriers generated by light irradiation can easily drift toward the electrode, which in turn lengthens their lifetime. .

Furthermore, the present invention removes the concentration of oxygen added to the semiconductor by providing first and second preparatory chambers, thereby reducing the concentration of oxygen added to the semiconductor.
10 ¹⁸ cm ^-3 concentration less than 1/3, preferably 1/1
0 to 1/50, the silicon oxide insulating component is removed from the semiconductor, making it more of a semiconductor, and the lifetime of the carrier is extended.

In addition, the method of laminating semiconductor layers independently was developed by the present inventor for a semiconductor device (patent application filed in 1983).
152887S53.12.10 application) and its divisional application Semiconductor device manufacturing method (Patent application 1982-55607S56.4.15)
It is written in However, although these are described as independently connected plasma vapor phase methods, the active semiconductor layer is further divided into multiple layers and then IP ^- ,
There is no description of the IN ^-junction and its further development to form the PIN ^- N junction. The present invention further develops this and provides a photoelectric conversion device with a conversion efficiency of 10 to 14%/cm ² (intrinsic conversion efficiency of 5 cm in AM 1100 mW/cm ² irradiation light), compared to the conventional 6 to 8%/cm 2 . It is characterized by an improvement of 4 to 6% over ^cm2 .

In the photoelectric conversion device of the present invention, the P or N type semiconductor layer, particularly the P type semiconductor layer on the incident light side, has a wider energy band width than the active semiconductor layer,
This prevents an increase in absorption loss of irradiated light in the semiconductor layer.

A semiconductor device (U.S. patent application) filed by the present inventor as a device in which this energy band structure is continuously bonded and a window structure is provided for the P-type semiconductor layer
4239554 US Patent issued on December 6, 1980 4254429
Published March 3, 1981) is known. The present invention is a further development of the application resulting from the invention by the present inventor.

The present invention provides such a semiconductor layer with a halogen element such as hydrogen, fluorine or chlorine for neutralizing recombination centers.
By containing an alkali metal element such as lithium at a concentration of 0.1 to 20 mol% and a concentration of 10 ¹⁴ to 10 ¹⁷ cm ^-3 to have a neutralizing effect on dangling bonds, typically 5 to 2000 Å Semi-amorphous semiconductor (semi-amorphous) with crystallinity in the range of 5 to 100 Å (short range crystallinity)
SAS) and an amorphous semiconductor (hereinafter referred to as AS) which does not have crystallinity in the short range order are provided in a layered structure.

In particular, in the present invention, the P-type semiconductor layer on the light irradiation side of the photoelectric conversion device is made of SAS to reduce the absorption of incident light in that area, and the intrinsic semiconductor layer adjacent to it is made of SAS, and the P-type semiconductor layer on the side of the incident light is made of SAS. This increases the lifetime of the carrier and
By stacking AS or a semiconductor layer mixed with AS in an intrinsic step-like or continuous manner on the top surface of SAS, an internal electric field is spontaneously created to promote improvement in light-to-electricity conversion efficiency.

Regarding SAS, Japanese Patent Application No. 55-026388, S55.3.3 (semi-amorphous semiconductor) filed by the present inventor is known. Furthermore, as an invention that utilizes this SAS to provide a PIN junction type photoelectric conversion device, patent application No. 56-008699 filed by the present inventor,
S56.1.22 (photoelectric conversion device) is known.

This will be explained below with reference to the drawings.

FIG. 1 shows an outline of a plasma CVD apparatus necessary for carrying out the present invention.

That is, the substrate 1 is parallel to the flow of reactive gas from above to below in a reactor 25 to 28 in which an insulating holder, e.g., a quartz holder (boat) 2 is held, and an electrode 2 for high frequency energy 4,
It is installed in a direction parallel to the discharge of No. 3. The reactive gas is 5 silicide gas (SixH _2x+2 x1),
From 9, 13, and 17, the P-type impurity diborane (B ₂ H ₆ ) is from 6, the N-type impurity phosphin (PH ₃ ) is from 18, and the carrier gas hydrogen or helium (He) is from 8. 12, 16,
It was supplied from 20. In addition, additives such as methane (CH ₄ ) to provide a wide energy band width are added to the
Supplied from 9. 1 diborane diluted to 10-100 PPM with silane for adding trace impurities.
0.14 or similar silane or hydrogen diluted
10 to 100 PPM of phosphin is supplied from 11 and 15.

Electrodes 51, 52, 5 serve as outlets for ejecting these reactive gases into the reaction chamber and are also used for plasma generation.
3 and 54 to the reaction chambers 25, 26, 27, and 28. Once the reactive gases are released into the reaction chamber, electromagnetic energy is applied to activate and decompose the gases and deposit reaction products onto the surface on which they are formed. In this reaction chamber, electromagnetic energy with a frequency of DC to 20 MHz, for example, DC, 500 KHz, and 13.56 MHz, was applied from electrodes 2 and 3. Furthermore, it has become possible to heat a substrate 1 having a surface to be formed to 100 to 500 DEG C., typically 200 to 300 DEG C., in an infrared heating furnace 4 to process a large number of substrates.

The substrate 1 was first inserted into the first preliminary chamber 23 and evacuated using the rotary pump 30. Nitrogen was introduced from 21 to bring the preliminary chamber to atmospheric pressure. After this preparatory chamber is evacuated, the gate 55 is opened and transferred to a second preparatory chamber heated with an infrared lamp at 200 to 400° C., which is provided next to it, and after the transfer, the gate 55 is closed again. The first spare room is 21
After introducing more nitrogen to reach atmospheric pressure, another substrate is introduced. Through this repetition, the first
The substrate in the preliminary chamber is introduced into the second preliminary chamber, and the substrate in the second preliminary chamber 24 is introduced into the first reaction chamber 25 with a gradual phase shift. Furthermore, after evacuation is performed in this first preliminary chamber to remove the atmosphere, adsorbed oxygen is removed in the second preliminary chamber.
Removing water by vacuum heating lowers the oxygen concentration in the semiconductor layer to the conventionally known level of 1 to 3 x ¹⁰ cm.
It was possible to further reduce the value to 1×10 to 5×10 ¹⁵ cm ⁻³ , typically 1/10 to 1/30, which is less than 1/3 of ^-3 .

Of course, in each reaction chamber, efforts are made to ensure that vacuum leaks from the outside are below 10 ^-8 torr.

As described above, in the first reaction chamber, SixC _1-x (0<x<1) having a P-type conductivity having an energy band width of 1.6 to 2.2 eV was formed on the surface to be formed.
After forming the substrate to a thickness of 200 Å or less, typically 30 to 150 Å, the first and second reaction chambers were evacuated, and the substrate having the surface to be formed was phase-shifted to the second reaction chamber 26. . At this time, the substrate installed in the second reaction chamber is placed in the third reaction chamber 17, the substrate in the third reaction chamber 27 is placed in the fourth reaction chamber 28, and the substrate in the fourth reaction chamber is placed in the third reaction chamber 17.
After completely closing the gate 56, the substrate in the third preparatory chamber is taken out through another gate 57.

In the second reaction chamber 26, a vertical cross-sectional view is shown in FIG. 2A, a P-type first semiconductor layer 44 is formed and an I-type second semiconductor layer 4 is formed.
5 is formed to a thickness of 100 to 2000 Å, typically 200 to 500 Å. When forming the second semiconductor layer, this I layer contains impurities that form the first semiconductor layer.
Since it is mixed in at a depth of 100 Å, it is formed at least 100 Å.
P-type impurity and N-type impurity are 5×10 ¹⁶ cm
Do not mix directly at concentrations higher than ^-3 .

This I-type semiconductor layer is extremely important for forming a depletion layer and promoting the movement of carriers there by drift toward the electrode.

Furthermore, after this, in the third reaction chamber 27,
The thickness of the N-type third semiconductor layer 46 is 0.1 to 0.6μ.
It was formed to a thickness of m. Further, in the fourth reaction chamber 28, an N-type fourth semiconductor layer 47 was formed to a thickness of 100 to 500 Å. This semiconductor layer also applies BSF (reverse depletion field) to minority carriers.
SixC _1-x (0<x1) with Eg of 1.8 to 2.5 eV was used. The I layer 45 and the N ⁻ layer 46 were made of the above-mentioned non-single crystal silicon and had a voltage of 1.5 to 1.8 eV.

After the four semiconductor layers as described above were laminated, an organic resin mold 49 made of epoxy, polyimide, etc. was overcoated to a thickness of 100 to 500 μm to improve the electrode 48 and moisture resistance.

In FIG. 2A, the substrate is a transparent substrate 40 made of glass, polyimide resin, etc.
A typical example in which B and P were added to Ni and Ni at a depth of 20 μm, or Al and Cu were provided in the bulk thereof, and a recessed auxiliary electrode 41 was provided. Furthermore, a transparent conductive film 43 is formed on this upper surface. This transparent conductive film
A two-layer film can be created by laminating ITO (indium oxide + 3 to 10% tin oxide), tin oxide, antimony oxide, or a mixture thereof.

This transparent conductive film is made of antimony oxide (Sb ₂ O ₃ or Bb ₂ O ₅ ) which is a V-valent transparent conductive film when the semiconductor in contact with it is a P-type semiconductor as in this example.
ITO is formed in a thickness of 50 to 200 Å so as to be in contact with the conductive film, and the ITO is placed on the underlying layer to improve the conductivity of this conductive film, which greatly contributes to improving the conversion efficiency of the photoelectric conversion device, especially increasing the current. Ta. When ITO is brought into contact with a P-type semiconductor, 5~
The one with a current density of 10mA/ ^cm2 is 13~
The output was extremely large at 20mA/cm ² . This is because antimony becomes a recombination center for holes in the P-type semiconductor, and the electrical series resistance at this interface can be lowered.

The energy band widths corresponding to FIG. 2A obtained as described above are provided in FIG. 2B with corresponding numbers.

As is clear from this drawing, the active semiconductor layer 41
.about.46 efficiently supplies holes, which are minority carriers in this case, to the P-type semiconductor layer 44 due to the high potential difference between 44 and 46. In particular, in order to make the depletion layer expand and have a high electric field strength in the intrinsic semiconductor layer 45 near the irradiation light, the N ^- type semiconductor layer 4
6 is provided, and the carriers generated by light irradiation in this 46 are caused by drifting minority carriers into the P-type semiconductor layer, including the aid of the BSF effect. As a result, conventionally known simple PIN semiconductors could not achieve conversion efficiency of 5 to 7%/ ^cm2 , but with the PIN ^- N structure, high conversion efficiency of 10 to 12% can be achieved. I was able to get it on AM1. Furthermore, even on a large-area board of 10 cm, the open-circuit voltage can be increased with the help of 41 auxiliary electrodes.
Practical conversion efficiency of 0.9 to 0.95V and short circuit current of 16 to 20 mA/cm ² and 7 to 10% could be obtained.

FIG. 3 shows a reference example in which the substrate 40 is conductive, for example made of stainless steel. On this upper surface, the first, second, third, and fourth marks are placed in the same manner as in Fig. 2A.
The semiconductor layers 44, 45, 46, and 47 are laminated and provided, and are provided by a transparent conductive film 43 of ITO, an auxiliary electrode 41, and a resin mold 49.

The corresponding energy band diagram at A-A′ is shown in the third diagram.
This is shown in Figure B. In this case, unlike Fig. 2A, the light is irradiated from above, so N47I46P ^- 4
It is set as 5P44. In this case, since the impurity concentration of P ^- is extremely low at 5 x 10 ¹⁶ to 1 x 10 ¹⁸ cm during film formation, it is possible to make 5 to 10 PPM (hydrogen dilution) in the cylinder due to the reaction between diborane and the cylinder. It's impossible. Therefore, in the present invention,
Another feature is that a cylinder containing 10 to 100 PPM of diborane added to the silane is used. In this way, a controllable P ^- type semiconductor layer 45 could be produced. In order to prevent P-type impurities from being mixed into this layer by autodoping from the first semiconductor layer 44, in the present invention, a first reaction chamber 25 for the P-type semiconductor layer 44 and ^a P- The second reaction chamber 26 for the type semiconductor layer is made independent. In particular, when carbon is added to the P-type semiconductor layer 44, it is extremely important to prevent this carbon from being partially (locally) mixed into the P ^- second semiconductor layer and preventing electrical conductivity. . Therefore, the second semiconductor layer 45 is mainly composed of silicon, germanium, or a mixture thereof, and contains 3×10 ¹⁷ cm ^-3 of carbon, oxygen, and nitrogen.
Efforts were made to prevent the electrical conductivity from worsening by mixing with the above concentration.

Thus, even in the case shown in Figure 3B, the second
As shown in the figure, we were able to obtain a conversion efficiency of over 10%.

For other manufacturing methods shown in Figure 3, see Figures 1 and 2.
This is similar to what was stated in the figure.

In the above description, the semiconductor device has one PIN ^- N junction. However, by repeating this further, PIN ^- NPIN ^- N or
PIN ^- NPIN junction and stacked series connection, front side
IN ^- The active layer is 1.6 to 1.8 eV with non-single crystal Si, and the back side is 1.0 to 1.6 eV with SixGe _1-x (0x1).
It may also be used to increase the open circuit voltage.

As is clear from the above explanation, in the present invention, the active semiconductor layer is made of IN ^- , and the impurity concentration is not simply made lower than that of the N semiconductor layer as in the past, but oxygen and carbon, which are current protection elements in the active semiconductor layer, are used. , the concentration when measured by nitrogen IMA is 3×
10 ¹⁷ cm ^-3 or less, furthermore, by avoiding the mixing of valence and valence impurities in the I layer on the light irradiation side, and by adding P ^- or N ^- , the lifetime of minority carriers was lengthened. Moreover, this I,
For the ^first time, ¹⁰ %
It is possible to create a large-area photoelectric conversion device with high conversion efficiency exceeding . In this respect, I believe that its industrial value is considerable.

[Brief explanation of drawings]

FIG. 1 shows an outline of a semiconductor device manufacturing apparatus used in the present invention. In FIG. 2, A shows a vertical sectional view of the photoelectric conversion device of the present invention, and B shows an energy band diagram corresponding to A. FIG. 3 shows a photoelectric conversion device shown as a reference example, and A shows a vertical sectional view thereof, and B shows an energy band diagram corresponding to A.

Claims (1)

[Claims] 1. A photoelectric conversion device provided by laminating non-single-crystal semiconductor layers, characterized in that the conductivity type of the non-single-crystal semiconductor layer is PIN ^- N from the light irradiation surface side.