JPH04316093A - Image reproduction device and its signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a reproduced image without spoiling its definition by displaying an image which is different in vertical/horizontal ratio from the screen of the image reproduction device while the image is scrolled. CONSTITUTION:A write timing decision circuit 12 writes data at a specific position among image data, outputted by an image decoding circuit, selectively in a frame memory and a read timing generating circuit 15 specifies >=2 read start places of an image to be read out of the frame memory and displayed on a display unit and makes a window display. When the image is displayed while scrolled, only image data at a part moving out of the screen are rewritten, so the frame memory does not require capacity larger than the display screen size and the size of the whole image which is scrolled and displayed is not limited to the capacity of the frame memory.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention decodes image data recorded on a medium such as an image file device or an image terminal, or encoded image data transmitted via a communication channel and displays it on a display screen. The present invention relates to an image reproducing device for displaying images. In particular, it relates to an image reproducing device that displays images of unspecified shapes, such as works of art such as paintings, sculptures, and buildings, as well as photographs thereof, on the entire screen of a display, and scrolls the images without losing the definition of the images. .

0002

2. Description of the Related Art When attempting to display an image on an image reproducing device, the image may not match the screen size and aspect ratio specific to the image reproducing device. In such cases, you can reduce the size of the image and display it with blank areas on the top and bottom or left and right sides of the display screen, or use the full screen size and move the image that cannot be displayed on the screen top and bottom or left and right. You had to scroll to view it or use some other method. In particular, the latter method is advantageous in order to sufficiently express the definition of the image.

[0003] For this reason, in conventional image reproducing apparatuses, as described in Japanese Patent Laid-Open No. 3-25494, for example, a frame memory larger than the capacity corresponding to the screen that can be displayed on the display is provided, and when attempting to display the image on the screen. The entire image to be displayed is once written in this frame memory, the image data is partially read out and displayed on the display, and scrolling is performed by changing the reading start position of the image data.

0004

[Problems to be Solved by the Invention] However, in such conventional image reproducing devices, if the image to be displayed is twice the aspect ratio of the screen, it is twice the aspect ratio, and if it is three times the aspect ratio, it is three times the aspect ratio. A frame memory with a large capacity is required, and while the amount of memory increases, there is a problem in that the absolute upper limit of the aspect ratio of an image that can be displayed by scrolling is limited by the memory capacity of this frame memory.

[0005] In order to store high-definition images such as high-definition images, a capacity of about 6 Mbytes is required for each screen, and in order to achieve high-speed operation, it is necessary to use video RAM or perform parallel-to-serial conversion processing. is essential, and reducing memory usage is economically important.

An object of the present invention is to provide an image reproducing apparatus that can reproduce an image having an aspect ratio different from that of the screen of the image reproducing apparatus while scrolling, without losing the definition of the image. The object of the present invention is to achieve this without increasing the capacity of the frame memory, and furthermore, to ensure that the range of images that can be scrolled is not limited by the capacity of the frame memory.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a frame memory for storing image data and supplying it to a display, and a readout start position of an image for reading out from the frame memory and displaying it on a display. A read address generation circuit that specifies two or more locations, a read timing generation circuit, an image decoding circuit that restores image data from data provided from outside the recording medium or the image reproducing device, and an image output from the image decoding circuit. A write timing determination circuit and a write address generation circuit are provided for selectively writing only data at a specific position out of the image data stored in the frame memory.

[0008]

[Operation] When displaying an image with a different aspect ratio than the screen of the image reproducing device on the display, the write timing determination circuit first selects the image data of the area that can be displayed on the display screen out of the entire image. Write to frame memory. Next, the readout start position of image data from the frame memory and its timing are moved in accordance with the scrolling direction. On the other hand, the image decoding circuit decodes the image data again, selects only the portion of the obtained image data that needs to be newly displayed on the screen by scrolling, and writes it into the frame memory. The area to be written at this time is to overwrite the part that has gone out of the display screen by scrolling, and display this part so that it is in contact with the image data that was originally stored in the frame memory, and to display the newly written part. Specify the reading start position and timing. By repeating the above series of operations, the displayed image can be scrolled.

[0009] In this way, since the image data of the part that moves off the screen by scrolling is sequentially rewritten, the capacity of the frame memory only needs to be equivalent to the screen size of the display, and the size of the entire image is The size is not limited by frame memory capacity.

0010

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an image reproducing apparatus according to the present invention. First, the components of the entire device will be explained. CPU1, system memory 2, hard disk I/F3, magneto-optical disk I/F5, keyboard I/F
7, a decoding circuit 9 and a frame memory I/F 10 are connected by a system bus 18, respectively. A hard disk 4, a magneto-optical disk 6, and a keyboard 8 are connected to the hard disk I/F 3, magneto-optical disk I/F 5, and keyboard I/F 7, respectively. The output data of the decoding circuit 9 is written into the frame memory 11, and the data read out from the frame memory 11 is converted into an analog video signal by the D/A converter 17 and displayed on the display 19. A write timing determination circuit 12, a write address generation circuit 13, a read address generation circuit 14, and a read timing generation circuit 15 are connected to the frame memory I/F 10. Clock generation circuit 16 generates a clock to be supplied to decoding circuit 9, D/A converter 17, read address generation circuit 14, and read timing generation circuit 15.

Next, the operation of each part will be explained.

The hard disk 4 stores a system program for the CPU 1 to control each peripheral device, a playback program describing a method for playing back images, etc., and these programs are loaded into the system memory 2 and executed. Encoded image data is recorded on the magneto-optical disk 6 in advance, and is read out in response to input instructions from the keyboard 8 according to the procedure prescribed by the reproduction program, and sent to the decoding circuit 9. The image data is restored from the sent and encoded data. Image data recorded on the magneto-optical disk 6 is usually subjected to encoding processing for data compression in order to increase the recordable capacity per disk and shorten the time required to read from the disk. The data compression method is DCT (
Discrete cosine transform), VQ (vector quantization), DPCM (differential pulse code modulation), etc. are often used. Although this embodiment will be described using DCT encoding as an example, the present invention is not limited to this compression processing method.

FIG. 2 shows an outline of the process of restoring compressed image data performed in the decoding circuit 9. When encoding an image using DCT, the image data is usually divided into square blocks and processing is performed for each block. FIG. 5A shows how image data is divided into blocks, and here it is assumed that the image is divided into adjacent blocks of 8×8 pixels and encoded. The encoded image data is recorded on the magneto-optical disk 6 one block at a time from the upper left block to the right.
When the rightmost block in the top row is reached, the blocks in the next row below are recorded in the same manner from left to right, finally reaching the bottom right block. The decoding circuit 9 decodes the input data in the order shown in FIG. 2(a), performs a data rearrangement process, and converts the image data in order for each line and outputs the data as shown in FIG. 2(b). . To rearrange the image data, for example, a memory such as a line buffer may be provided, and the order may be changed between writing and reading the restored data. The decoding circuit 9 outputs the image data as well as a data clock synchronized with the image data, and sends it to the write timing determination circuit 12.

The write timing determination circuit 12 is a CPU
1, it is determined whether or not to generate a write clock for the frame memory 11 from the clock output from the decoding circuit 9 based on the setting conditions given through the frame memory I/F 10, and the write clock is generated for the frame memory 11 according to the determination result. supply. The write clock is also sent to the write address generation circuit 13 and used to count up the write address of the frame memory 11. Further, the write address generation circuit 13 is given an address preset value from the CPU 1 through the frame memory I/F 10, and the write timing determination circuit 12
The write address is set to the preset value in accordance with the timing of the preset signal given from the . Note that the conditions for generating the write clock and how to set the preset value of the write address will be explained in detail later.

The read address generation circuit 14 counts the clocks generated by the clock generation circuit 16 and generates a read address for the frame memory 11. The read timing generation circuit 15 generates a read clock for the frame memory 11 based on the clock signal generated by the clock generation circuit 16, and also generates a read clock for the frame memory 11 based on the clock signal generated by the clock generation circuit 16.
A preset signal for the read address generated in step 4 is generated. Every time this preset signal is generated, the address generated by the read address generation circuit 14 is
The frame memory is reset to a preset value given through the frame memory I/F 10. The preset signal is generated at a timing such that the video signal read from the frame memory 11 and output from the D/A converter 17 has a speed matching the horizontal and vertical scanning frequencies of the display 19. Further, by generating a preset signal two or more times in one scanning period and giving different positions on the frame memory 11 as address preset values, a window display can be realized on the screen of the display 19. Note that although the synchronization signal for the display 19 is directly provided from the read timing generation circuit 15, the synchronization signal may be provided by being superimposed on the video signal.

Write timing determination circuit 12, write address generation circuit 13, read address generation circuit 1
4 and the read timing generating circuit 15 change their operating methods depending on the size of the image to be displayed on the screen of the display 19. In the following, cases in which the size of the image to be displayed is larger than the screen of the display 19 and cases in which it is not will be explained separately.

Information regarding the size of the image is recorded on the magneto-optical disk 6 as additional information to the image data or as part of the reproduction program on the hard disk 4.
Based on this information, the CPU 1 transmits information regarding the image reproduction method to each section through the frame memory I/F 10.

When displaying image data of the same size or smaller size than the screen of the display 19, the write timing determination circuit 12 determines that all data clocks supplied from the decoding circuit 9 are valid, and All image data restored in frame memory 1
Write it to 1. The write address preset signal is generated every time one scanning line of the image is written, and presets the horizontal address value generated by the write address generation circuit 13 to a predetermined setting value, and the vertical address is generated every time the write address is preset. is counted up by 1. If the image to be displayed is the same size as the screen, set the horizontal address to the value closest to the left edge of the screen, and if the width of the image size is smaller than the screen, the image may protrude from the screen. It is best to set it to an appropriate value so that it does not occur. This value may be determined by the user through input from the keyboard or written in the reproduction program recorded on the hard disk 4.

The read timing generation circuit 15 generates a read address preset signal every horizontal scanning period, and sets the horizontal value of the read address to the value indicating the leftmost end for each scanning period, and also sets the read address preset signal to the value indicating the leftmost end for each scanning period. Count up the address by 1 or by a predetermined number larger than that.

[0021] As described above, the image data read from the magneto-optical disk 6 and restored by the decoding circuit 9 is read out after being completely written to the frame memory 11.
The entire recorded image can be displayed on the screen of the display 19.

On the other hand, when attempting to display an image larger than the screen size that can be displayed on the display 19, first, out of the image data recorded on the magneto-optical disk 6, as much data as can be written into the frame memory 11 is displayed. is written, the image within the displayable range is displayed on the screen of the display 19, and then all parts of the image are sequentially displayed on the screen by scrolling the screen. The method of scrolling the screen in this manner will be explained below using FIG. 3.

FIG. 3 shows the image data (a) recorded on the magneto-optical disk 6, the data written in the frame memory 11 (b), and the screen displayed on the display 19 (c) over time. They are shown lined up from left to right along the line. This example shows a case where the size of the image that can be displayed on the screen of the display 19 is equal to the capacity of the frame memory 11, and the image to be displayed on the screen is laterally longer than the screen of the display 19. First, the portion 31a of the image data (a) that can be displayed on the display screen from the leftmost end is written into the frame memory 11. Since the data output from the decoding circuit 9 is a continuous data string for each horizontal scanning line as shown in FIG. To write to the memory 11, the write timing determination circuit 12 counts the data clock output from the decoding circuit 9, and when the number of write pixels in the horizontal direction reaches the number of pixel data to be written to the frame memory 11, the write clock of the frame memory 11 is counted. After that, the pixel data 31b on that scanning line is ignored and no writing to the frame memory 11 is performed. The write timing determination circuit 12 continues to count the clocks output from the decoding circuit 9, and when the image data moves to the next scanning line, it presets the horizontal address of the write address generation circuit 13 and sets one vertical address. It counts up and starts generating the write clock again. Thereafter, the same process is repeated for each line, and the image data is written into the frame memory 11 up to the bottom line. In this way, the image data 34 is written to the frame memory 11 as shown on the left side of FIG. 3(b), and the display 19
An image 37 shown in FIG. 3(c) appears on the screen.

Next, a procedure for scrolling the display screen to the left in accordance with input from the keyboard 8 of FIG. 1 or the description of the playback program recorded on the hard disk 4 will be described.

When scrolling the display screen, first, encoded data is read from the magneto-optical disk 6 and restored to image data by the decoding circuit 9, in the same way as when the first image data was written. Write timing judgment circuit 1
In step 2, the data clock is counted, and the output of the write clock is stopped until the count reaches the number of pixels in the horizontal direction of the image that has already been written to the frame memory 11, that is, the number of pixels that can be displayed on the display 19. Thereafter, a write clock is generated for a period of a fixed number of clocks given from the CPU 1 via the frame memory I/F 10, and then the generation of the write clock is stopped again until the pixel data on that line is completely restored. Write clocks are generated and stopped in the same way for the second and subsequent lines. As a result, of the image data output from the decoding circuit 9, only the portion 32b immediately to the right of the portion 32a already written to the frame memory 11 is selected and written to the frame memory 11.

Furthermore, the write timing determination circuit 12 generates a preset signal for the write address at the same time as or before the start of generation of the write clock, so that the address generated by the write address generation circuit 13 can be used if the address has already been written to the frame memory 11. preset to the address that indicates the leftmost part of the image data in the scroll direction on the screen. As a result, the image data 32
b is written into the portion 35a on the frame memory 11. On the other hand, the read timing generation circuit 15 counts the clock output from the clock generation circuit 16 and generates a preset signal twice per horizontal scanning period, and each preset signal is the read start timing of the area 35b in the frame memory 11. The read timing generation circuit 1 is transmitted from the CPU 1 through the frame memory I/F 10 so as to provide the reading start timing of the area 35a.
Set the preset signal generation timing in step 5. In this way, image data is read out from the frame memory 11 from the area 35a in the first period and then from the area 35b within one horizontal scanning period, and the screen 38 is displayed on the screen of the display 19.

Further, encoded data is read from the magneto-optical disk 6 and restored to image data by a decoding circuit 9. In the same way as described above, the write timing determination circuit 12 generates a write clock and the preset signal is set so that the image data portion 33b shown in FIG. The generation timing and the preset address value of the write address generation circuit 13 are reset from the CPU 1. At the same time, the generation timing of the read address preset signal generated by the read timing generation circuit 15 and the preset value of the read address generation circuit 14 are set such that the signal readout from the frame memory 11 is performed in areas 36c, 36a, and 36b within one scanning period. Settings are made from the CPU 1 so that the operations are performed in sequence. As a result, an image as shown at 39 in FIG. 3(c) appears on the screen of the display 19.

[0028] If you follow the above steps, display 1
The screen of 9 changes as shown in 37, 38, and 39, and by scrolling an image that is longer than the screen, the entire image can be viewed over time. In the example given above, the scroll display was divided into three stages, but smoother scrolling can be achieved by narrowing the area width of the data written to the frame memory 11 at a time and increasing the number of times the data is written. .

Although this example shows the case where the horizontal width of the image is larger than the screen of the display, the same process can be performed even when the image is larger in the vertical direction. At this time, CP
The vertical value of the write address is given as a preset value from U1, and the write timing determination circuit 12 counts the number of lines of the image output from the decoding circuit 9. Furthermore, if the address generated by the read address generation circuit 14 automatically returns to the first address after the final address of the frame memory 11, the read timing generation circuit 15 does not necessarily have to generate two addresses in one vertical scanning period.
This eliminates the need to generate multiple preset signals.

Furthermore, even if the image is larger both vertically and horizontally than the displayable pixels of the display 19, it can be processed in the same way. The direction of scrolling is not only from right to left as described above, but also vice versa, or starting from the center.

As described above, according to this embodiment, it is possible to realize scrolling display while rewriting the image data in the frame memory. Even large images can be displayed in their entirety without reducing their definition. Furthermore, it is effective not only when the size of the image is larger than the size that can be displayed on the screen, but also when displaying small images one after another, by exchanging them while scrolling. In this case, the image data read from the magneto-optical disk during scrolling may be different from the image written in the frame memory.

[0032] Depending on how the image reproducing device is used, there may be cases where it is desired to display the entire image on the screen for confirmation rather than scrolling the image. At this time, the data read from the magneto-optical disk 6 is transferred to the decoding circuit 9.
When restoring and writing to the frame memory 11, the write clock generated by the write timing determination circuit 12 may be thinned out at a constant ratio with respect to the data clock generated by the decoding circuit 9. This can be easily achieved by setting the determination conditions in the write timing determination circuit 12 as such.

[0033] When reading the encoded data from the magneto-optical disk, it is attempted to read out the data including the part that is not written to the frame memory, but this improves the efficiency of encoding due to the image encoding method. This is because it is impossible to directly extract only data at a specific position by using the horizontal correlation of the image and by making the code length variable. Normally, it is essential to incorporate the methods described above to increase the compression rate of image data.
Moreover, in this case, since the compression ratio is high, the writing speed to the frame memory often determines the overall speed rather than the reading speed from the magneto-optical disk, and the present invention is effective as a countermeasure against this problem. At this time, even if encoded data is divided and recorded into a plurality of files, the effects of the present invention are not affected, and the speed of screen scrolling does not depend on the file division method.

In the above example, the case where the capacity of the frame memory is exactly equal to one screen is explained, but the present invention may be applied to a case where the capacity of the frame memory is larger. In such cases, the number of images initially read from the magneto-optical disk is increased to the maximum that can be stored in the frame memory, and scrolling is performed by simply changing the read timing and position to reduce the number of accesses to the magneto-optical disk. be able to.

Furthermore, according to the present invention, it is possible to further provide a scrolling function within the window as described below.

FIG. 4 is a diagram illustrating a method for implementing the in-window scrolling function.

In-window scrolling is performed when the main image 41 as shown in FIG. 4(a) is stored on the magneto-optical disk 6.
is displayed by combining it with the window area 42 of the background image as shown in (b), and at this time, the window area 4 of the background image
The main image, which has an area larger than 2, is scrolled to display the entire image.

FIG. 4(c) shows changes in the contents of the image data written in the frame memory 11 during scrolling within the window, from left to right over time. (d) shows a screen displayed on the display 19 corresponding to (c) of the same figure. In this case, first, as shown in FIG. 4(c), the upper part 43 of the main image and the window area 42 of the background image are stored in the frame memory 11.
write to. The read timing generation circuit 15 counts the clocks generated by the clock generation circuit 16,
The timing at which the background image 42 is read out and the position at which the main image 43 is read out are switched, and the screen of the display 19 is displayed as shown in FIG.
The screen 47 shown on the left side of d) is displayed.

Next, the main image data is read from the magneto-optical disk 6 and restored by the decoding circuit 9. The write timing determination circuit 12 detects the timing at which the portion 44 immediately below the image portion 45 that has already been written to the frame memory 11 is restored and output, and sets the write clock so that this portion is written to the frame memory 11. occurs. Furthermore, by supplying a preset signal to the write address generation circuit 13, the main image written in the frame memory 11 can be rewritten in order from the top. At the same time, the preset timing of the main image readout address generated by the readout timing generation circuit 15 and the corresponding address preset value of the readout address generation circuit 14 are changed, and the screen 48 of FIG. 4(d) is displayed on the display 19. so that Thereafter, the procedure for changing the display position of the main image described above is repeated, and scrolling within the window is executed until the screen 49 of FIG. 4(d) appears on the display 19.

As described above, according to the present invention, the size of the main image to be scrolled when performing intra-window scrolling is not restricted by the capacity of the frame memory. The in-window scrolling function itself can be realized if the frame memory capacity is exactly one screen. In this case, first the background image is written into the frame memory, then the main image is written, and the timing of generation of the read address is adjusted while selectively rewriting only the main image portion. Furthermore, by providing a frame memory capacity for two screens, you can allocate memory areas for the main image and background image, and instantly switch between the window composite screen and the main screen or background image only screen. Many types of display can be performed, such as by moving the compositing position of the main image.

Although the image reproducing apparatus shown in FIG. 1 uses a hard disk as a recording medium for the system and reproduction program, the present invention does not care about the type of recording medium for the program. Furthermore, the image data recording medium may be a storage medium that can practically achieve a scrolling speed, such as a write-once optical disc or a CD-ROM. Furthermore, in addition to the keyboard, a pointing device such as a mouse or a tablet may be used as a means for specifying the playback screen. Also,
Although not shown, the screen may be automatically advanced by connecting to an audio playback device that can provide information on elapsed time.

Next, a second embodiment of the present invention will be described.

FIG. 5 is a block diagram showing the configuration of an image reproducing apparatus according to a second embodiment of the present invention. In FIG. 5, the same parts as in FIG. 1 are given the same numbers and their explanations will be omitted.

In FIG. 5, a network I/F 50 and a buffer memory 51 are provided instead of providing a recording medium for storing image data inside the device, and data is encoded from a mass storage device 52 outside the image reproduction device through a network 53. image data. The encoded data sent from the network 53 is temporarily stored in the buffer memory 51, and thereafter the data stored in the buffer memory 51 is sent to the decoding circuit 9 to restore the image data. The image reproducing apparatus shown in FIG. You can scroll images and realize window scrolling.

According to the present invention, by storing encoded data in a buffer memory, the amount of data passing through the network thereafter can be reduced. According to the configuration of FIG. 5, the size of an image that can be scrolled and displayed is limited by the capacity of the buffer memory 51, but since the buffer memory 51 stores data compressed by encoding, increasing the frame memory allows scrolling. It is much more economical than increasing the display image size.

[0046] In the above embodiment, the case of an image reproducing apparatus has been described, but it goes without saying that the present invention can be applied not only to a reproducing apparatus but also to the reproducing part of a recording/reproducing apparatus.

[0047]

As described above, according to the present invention, even if an image has a different aspect ratio from the display screen of an image reproducing device, it can be reproduced to the full screen without losing its definition, and the entire image can be viewed by scrolling. You can see it. Furthermore, when displaying while scrolling, the image data of the part that moves outside the screen is rewritten, so there is no need for a frame memory capacity larger than the display screen size, and the overall size of the image to be scrolled and displayed is It is also not limited by the capacity of frame memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image reproducing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an image restoration method in a decoding circuit.

FIG. 3 is a diagram illustrating a scrolling procedure.

FIG. 4 is a diagram illustrating scrolling within a window.

FIG. 5 is a block diagram showing the configuration of an image reproducing device according to a second embodiment of the present invention.

[Explanation of symbols]

9...Decoding circuit, 11...Frame memory, 12...Write timing determination circuit, 13...Write address generation circuit, 14...Read address generation circuit, 15...Read timing generation circuit.

Claims (7)

[Claims] Claim 1: A decoding circuit that decodes encoded image data A, a memory that stores image data D, and an address that indicates where in the memory the image data B output from the decoding circuit is written. In an image reproducing apparatus equipped with a write address generation circuit, the timing at which specific image data C among the image data B is output is determined, and the image data D in the memory is selectively identified by the image data C. An image reproducing device comprising: a write timing determination circuit that transmits data selection information for rewriting a position to the memory and the write address generation circuit. 2. A read timing generation circuit for generating a read timing signal for reading out two or more partial image data from the memory out of the image data D stored in the memory; It also includes a read address generation circuit that generates respective addresses for reading the partial image data from the memory, and reads the partial image data from the memory according to the read timing signal and the address, thereby generating the partial image data. 2. The image reproducing apparatus according to claim 1, wherein the image reproducing apparatus outputs a signal for displaying the data as one screen in which data is connected. 3. The image data C is selected by the output of the write timing determination circuit, a part of the image data D is rewritten by the selected image data C, and an address value generated by the read address generation circuit. 2. The scrolling of the displayed image is performed by repeatedly performing an operation of changing the display position of the output destination of the partial image data read from the memory and moving the display position on the screen. 2. The image reproducing device according to 2. 4. The data selection information is generated by the write timing determination circuit so as to thin out the image data B at regular intervals and write the reduced image data C into the memory. image reproduction device. 5. A buffer memory for temporarily storing the image data A is provided, and when scrolling, the image data A is stored in the buffer memory, and the image data A in the buffer memory is supplied to the decoding circuit to generate an image. The image reproducing apparatus according to claim 1, wherein the image reproducing apparatus performs data restoration. 6. A circuit for decoding encoded image data A, a memory for storing image data D, and generating an address indicating in which position in the memory the image data B output from the decoding circuit is to be written. In an image reproducing apparatus that includes a write address generation circuit that displays the image data B on a display device, the timing at which specific image data C of the image data B is output is determined, and 1. An image reproducing apparatus, further comprising a write timing determination circuit for transmitting data selection information for rewriting a specific position of image data D in the memory to the memory and the write address generation circuit. 7. A decoding circuit that decodes encoded image data A; and a decoding circuit that determines the timing at which specific image data C is output from among the image data B output from the decoding circuit, and determines the timing at which specific image data C is output. 1. A signal processing circuit for an image reproducing device, comprising a timing determination circuit that generates selection information for selection.