JPH04309012A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the margin attended with signal transmission by forming a final output stage of an output circuit of an ECL logic LSI with a differential amplifier circuit including a couple of differential transistors(TRs) in emitter common connection. CONSTITUTION:An output circuit 10 provided in an LSI1 at a sender side is provided with a same inverter circuit 11 as an input stage of a non-threshold logic(NTL) circuit comprising series connection of a collector resistor Rc, a TR Qi and an emitter resistor Re connected between power supply voltages Vcc and Vee and a differential amplifier circuit 12 comprising a couple of differential TRs Q1, Q2 whose emitters are connected in common, a constant current source CC connecting to the common emitter of the differential TRs Q1, Q2 and resistors Rc1, Rc2 connecting to collectors of the differential TRs Q1, Q2. Then the collectors of the TRs Q1, Q2 are connected to LSI signal output terminals Ta, Tb and a differential form output is obtained.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to signal transmission technology, and particularly to a technology that is particularly effective when applied to voltage-driven differential transmission, and for example, to a technology that is effective when applied to signal transmission between ECL logic LSIs. .

0002

[Prior Art] Conventionally, as a method for transmitting signals from one circuit to another in an LSI, for example, an internal bus method has been used, in which the potential of a signal line is changed to high and low levels, and a threshold voltage is applied on the receiving side. In comparison, there is a voltage drive method that detects the signal level, and a current drive method that uses a differential amplifier to drive a pair of signal lines in opposite directions.
No. 7698). On the other hand, as a signal transmission method between logic LSIs, MOSLSI generally uses a voltage drive method, and bipolar LSIs use a current drive method. In both cases, the signals transmitted are single-ended (differential) in order to save the number of pins. (not a moving signal). For example, E.C.
As shown in Figure 3, as a method for transmitting signals between ECL logic LSIs such as gate arrays whose basic logic gates are L gates and NTL gates, an emitter driven by a differential circuit (current switch) CS is used. A method was used in which the follower resistor Rf was an external resistor, connected near the receiving LSI as a terminating resistor matched to the characteristic impedance of the line, and current-driven by the output transistor Qo on the transmitting side. (Gan Sho 63-81645)
.

0003

SUMMARY OF THE INVENTION The present inventors have discovered that the conventional current-driven signal transmission described above has the following drawbacks. That is, (1) since the output circuit requires a reference potential (Vbb) as a logic threshold, the power supply voltage Vee is increased from -3V to -2V to lower the amplitude of the signal and increase speed. If you try to
The operating margin deteriorates due to variations. (2) Since the output signal is single-ended, the noise margin is low. Furthermore, in order to prevent this, the amplitude of the output signal must be increased, but increasing the amplitude of the signal increases the power consumption of the LSI and slows down the signal transmission speed. (3) Since the terminating resistor becomes an external resistor of the LSI, integration into a single chip is hindered, and the packaging density on a printed circuit board etc. is reduced. (4) If the resistance of the external pin provided on the package is large, a potential drop will occur in the transmission signal. That is what it is.

An object of the present invention is to provide a system in which signal transmission between ECL logic LSIs is performed using differential signals.
The objective is to improve the margin associated with signal transmission. Another object of the present invention is to reduce the power consumption and increase the speed of LSIs in a system in which signal transmission between ECL logic LSIs is performed using differential signals.

Another object of the present invention is to provide an ECL-based logic LSI.
The object of the present invention is to facilitate the integration of LSIs constituting the system into one chip in a system in which differential signals are used for signal transmission between the systems. Another object of the present invention is to
The purpose of this invention is to prevent potential drops in transmitted signals in a system in which signal transmission between SIs is performed using differential signals. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows. In other words, the final output stage of the output circuit of an ECL logic LSI is configured with a differential circuit including a pair of differential transistors whose emitters are commonly connected, and each collector terminal of the differential transistor pair is connected to an external output terminal. It is designed to output in differential format.

[0007]

[Operation] According to the above means, since differential signals are output,
The operating margin of the input/output circuit does not deteriorate due to slight fluctuations or variations in the reference voltage due to fluctuations in the power supply voltage, etc., and it has excellent noise resistance and can reduce amplitude. In addition, since it is driven by voltage from the collector terminal instead of current drive, there is no need to provide a termination resistor within the chip, making it easier to integrate into a single chip. Even if there is a difference, there is almost no potential drop, and the output signal level can be stabilized.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a transmission circuit to which the present invention is applied. The transmission circuit of this embodiment is shown as having a configuration in which two logic LSIs 1 and 2 mounted on a printed circuit board or the like are connected by transmission lines 3a and 3b made of twisted pair wires or the like. The output circuit 10 provided in the LSI 1 on the transmitting side has a power supply voltage Vcc-Vee.
An inverter circuit 11, which is the same as the input stage of an NTL circuit (non-threshold logic circuit) in which a collector resistor Rc, a transistor Qi, and an emitter resistor Re are connected in series, and a pair of differential transistors whose emitters are commonly connected. Q1, Q2 and this differential transistor Q1,
a constant current source CC connected to the common emitter terminal of Q2;
It is constituted by a differential circuit 12 consisting of resistors Rc1 and Rc2 connected to the collector sides of the differential transistors Q1 and Q2, and the collector terminals of the differential transistors Q1 and Q2 are connected to the signal output terminals Ta and Tb of the LSI. It is connected. In this embodiment, the potential of the node N1 of the inverter circuit 11 is applied to the base terminal of one transistor Q1 of the differential circuit 11, and the input signal Vin of the inverter circuit 11 is directly applied to the base terminal of the other transistor Q2. There is. Note that in FIG. 1, the capacitor Cs connected in parallel with the emitter resistor Re of the inverter circuit 11 is for speeding up, and can be omitted.

[0009] The output terminals Ta and Tb are connected to a transmission line l.
input terminals Tc and Td of the LSI on the receiving side via a and lb.
is connected. Further, an input circuit 20 consisting of a circuit of the same type as a known ECL gate circuit is connected to the input terminals Tc and Td. In addition, in FIG. 1, the symbol r
1, r2, r3, and r4 are the resistance values of the external output pins of the package.

The levels of the output signals Va and Vb transmitted from the output circuit 11 are determined by the constant current source CC of the differential circuit 12.
It is determined by the current value of and the values of collector resistors Rc1 and Rc2. In this embodiment, collector resistors Rc1, Rc2
The resistance value of the constant current source CC is set to a fairly low value of about 50Ω, and the current value of the constant current source CC is set to, for example, 4 mA, and low amplitude signals Va and Vb of 200 mV are output. Although not particularly limited, in this embodiment, the output signals Va,
As the amplitude of Vb decreases, the power supply voltage Vee of the differential circuit 12 decreases.
is −2, which is the same as the power supply voltage Vee of the inverter circuit 11.
It is assumed that the voltage is V. Therefore, the power consumption of the output circuit 10 of this embodiment is extremely low at 8 mW.

[0011] In the above embodiment, the input stage of the output circuit 10 is composed of the same inverter circuit 11 as the input stage of the NTL circuit, but instead of the inverter circuit, an ordinary NTL gate circuit with an emitter follower or an ordinary NTL gate circuit with an emitter follower is used. An SPL circuit as shown in FIG. 2 may also be used. The circuit in Figure 2 uses a push-pull circuit consisting of a pull-up transistor and a pull-down transistor instead of the emitter follower of a normal NTL circuit, and adds a so-called active pull-down circuit to change the output from high level to low level. The switching speed has been increased.

That is, in place of the emitter resistor between the emitter terminal of the emitter follower transistor Q21 constituting the output stage of the NTL circuit and the power supply voltage terminal Vtt, a pull-down transistor Q22 is connected, and a transistor constituting the input stage 11 is connected. A CR differentiator circuit (Rd, Cd) is connected to the emitter terminal of Qi to detect a change in the level of node N1, and when the output falls, the output of the differentiator circuit temporarily turns on the pull-down transistor Q22 to set the low level. This speeds up the changes to . By using such a high-speed circuit, complementary signals necessary for driving the next-stage differential circuit 12 can be easily obtained. In addition, in FIG. 2, a constant voltage Vb is connected in series with the resistor Rd constituting the CR differential circuit, and a constant voltage Vb is connected to its base terminal.
The transistor Q31 to which 1 is applied is a transistor provided to provide a bias point for the output transistor Q22.

As explained above, the above embodiment is an EC
The final output stage of the output circuit of the L-based logic LSI is formed by a pair of differential transistors whose emitters are commonly connected, a resistor connected to the collector terminal of the differential transistor, and a resistor connected to the common emitter terminal of the differential transistors. It is configured with a differential circuit consisting of a constant current source, and each collector terminal of the differential transistor pair is connected to an external output terminal to output in a differential format. Since the operating margin does not deteriorate and the noise resistance is excellent, it is possible to reduce the amplitude. Furthermore, since the amplitude is low, the power consumption of the entire system can be reduced. Furthermore, since it is driven by voltage from the collector terminal rather than by current, there is no need to provide a termination resistor within the chip, making it easier to integrate into a single chip. Even if there is a voltage drop, there is almost no potential drop, and the output signal level can be stabilized.

[0014] The invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say. For example, in the above embodiment, the input stage of the output circuit 10 is configured with an inverter circuit of the same type as the input stage of the NTL circuit, an ordinary NTL gate circuit with an emitter follower, or an SPL circuit as shown in FIG. , it is also possible to use ECL gates instead of these.

[0015] In the above explanation, the invention made by the present inventor will be mainly explained in relation to the logic L
Although we have explained the case where it is applied to signal transmission between SIs,
The present invention is not limited thereto, but can be used for signal transmission between chips in wafer scale LSI.

[0016]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below. In other words, in a system that uses differential signals to transmit signals between ECL logic LSIs, it is possible to improve the margin associated with signal transmission, reduce power consumption and speed up the system, and
can be easily integrated into one chip, and potential drops in transmitted signals can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a signal transmission circuit using a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the input stage of the signal output circuit.

FIG. 3 is a circuit diagram showing an example of a conventional current-driven signal transmission circuit.

[Explanation of symbols]

1 Transmitting side LSI 2 Receiving side LSI 3a, 3b Transmission line 10 Output circuit 12 Final output stage 20 Input circuit Q1, Q2 Differential transistor CC constant current source

Claims (3)

[Claims] Claim 1: The final output stage of an output circuit that transmits a signal to the outside is composed of a pair of differential transistors whose emitters are commonly connected, a resistor connected to the collector terminal of the differential transistor, and the pair of differential transistors. and a constant current source connected to the common emitter terminal of the differential transistor pair, and each collector terminal of the differential transistor pair is connected to an external output terminal to output a differential format signal. A semiconductor integrated circuit characterized by: 2. The semiconductor integrated device according to claim 1, wherein an inverter circuit comprising a base input transistor, its collector resistor, and its emitter resistor is provided as an input stage before the final output stage. circuit. 3. A stage preceding the final output stage includes an inverter circuit including a base input transistor and its collector resistance and emitter resistance, a push-pull circuit including a pull-up transistor and a pull-down transistor, and a push-pull circuit in the inverter circuit. 2. The semiconductor integrated circuit according to claim 1, further comprising a circuit comprising level detection means for detecting a change in level and driving a pull-down side transistor of said push-pull circuit as an input stage.