JPH04307646A - High speed addressing system with production of logical-real coincident space - Google Patents

Abstract

PURPOSE:To attain a high addressing speed by omitting the conventional address converting process if an address belongs to a logical-real coincident area when an addressing operation is carried out for production of a logical-real coincident space. CONSTITUTION:In regard of a computer having a virtual space, the coincidence is secured between the logical and reel addresses in a proper space between logical addresses in an ASG state for acquisition of a logical-real coincident space. Then, a program, a control table, etc., which are resident in a memory and also frequently referred to and updated are allocated into the logical-real coincident space in an OS initialization state. When an address converting operation is carried out, a fact whether a logical address belongs to the logical- real coincident space or not (1). If so, the logical address is turned into a real address as it is (2). If not, the logical address is converted into a reel address by an address conversion mechanism (3).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for accelerating addressing of a computer having a virtual space management function.

0002

[Background Art] Conventionally, conversion from a logical address to a real address before prefix conversion is always performed using an address translation buffer when an entry in the address translation buffer can be used, or by using a segment table and a page table when an entry cannot be used. It was done.

[0003] The conventional addressing method described above always uses an address translation buffer or segment table when converting addresses, even for addressing programs and control tables that reside in memory and are frequently referenced and updated. , it was necessary to refer to the page table, which had the disadvantage of wasting time for address translation.

0004

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed addressing method that creates a logical-actual matching space and uses logical addresses as real addresses for that space.

[0005]

[Means for Solving the Problems] According to the present invention, in a computer having a virtual space, at the time of ASG, a space between an appropriate logical address and a logical address is made into a logical-real matching space by matching the logical address with the real address, and the OS During initial setup, programs, control tables, etc. that reside in memory and are frequently referenced and updated are allocated to the logical-actual matching space, and the range of the logical-actual matching space is notified to the hardware, and address conversion occurs. In doing so, the hardware determines whether the logical address to be translated belongs to the logical-real matching space;
If the address belongs to the logical-actual matching space, a high-speed addressing method is provided which is characterized by omitting the conventional address conversion process and using the approximate logical address as the real address as it is.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

[0007] The flow of processing when implementing the present invention is described by SG
, software, and hardware.

FIG. 1 shows logical addresses of an embodiment of the present invention.
This is the configuration of ACR0 and ACR1.

Referring to FIG. 1, the logical address of the computer of this embodiment consists of three parts: a segment number, a page number, and an intra-page relative address. Also, ACR0, ACR
1 (address control register) is 32 each.
The last 28 bits of the bit length are all zeros, and is a register for notifying the hardware of the maximum value of the logical matching space.

In this embodiment, logical and actual matching spaces are determined based on segment numbers.

[0011] At the time of ASG, the minimum segment number and maximum segment number of the logical and actual matching space for matching the logical address and the real address, and the program, control table, etc. to be allocated to the logical and actual matching space are determined. At this time, programs, control tables, etc. allocated to the logical-actual matching space must reside in memory and be referenced and updated frequently.

[0012] When initializing the OS, the software sets the minimum segment number of the logical and real matching space determined at the time of SG to ACR0.
, load the maximum segment number into ACR1, add 1 to ACR1, load the above program, control table, etc. into memory, and change the addressing mode to logical address mode.

The operation of the hardware when address translation occurs will be explained with reference to the drawings.

FIG. 2 is a block diagram showing the flow of processing when implementing the present invention.

FIG. 3 is a schematic diagram of an adder that executes logical and actual coincidence determination processing.

Referring to FIG. 2, in this embodiment, when address translation occurs, it is determined whether the approximate logical address belongs to the logical-actual matching space (1). If the approximate logical address belongs to a space where logic and reality match, the approximate logical address becomes the real address as is (2). If the approximate logical address does not belong to the logical-actual matching space, it is converted into a real address by the address translation mechanism (3).

Referring to FIG. 3, it is determined whether the object belongs to the logical-actual matching space as follows.

1. Output ACR0 to the L path of the adder and the logical address R path.

2. Instruct the adder to subtract.

3. The adder executes logical address -ACR0.

4. Receive the result CC from the adder.

5. When the CC of the result is 1, it is determined that the result belongs to the logical-actual inconsistency space.

6. When CC is other than 1, output ACR1 to the L path of the adder and to the logical address R path.

7. Instruct the adder to subtract.

8. Adder executes logical address -ACR1.

9. Receive the result CC from the adder.

When the CC of the result is 1, it is determined that it belongs to the logical-actual matching space, and when it is other than 1, it is determined that it belongs to the logical-actual mismatching space.

From the above explanation, the logical and real matching space can be determined very quickly by hardware.

[0029]

[Effect of the invention] Evaluate the effect of the invention quantitatively.

[0030] Let N be the time required for address translation in the conventional address translation process, α be the time required for logical and actual matching determination, and x be the probability that an address belongs to the logical and actual matching space during address translation. If the above is executed, the time required for address conversion will be xα+(1-x)(α+N).

Conventionally, it is N, so the ratio is as follows.

Since α/N is almost zero, x (the probability that an address belongs to the logical-real matching space during address conversion)
A sufficient effect can be obtained by increasing the value.

Generally, in order to increase x, it is necessary to tune the size of the logical-actual matching space, the program control table allocated to the logical-actual matching space, etc. for each system.

As is clear from the above description, the present invention creates a logical-actual matching space, so when addressing, if the approximate address belongs to the logical-actual matching interval, the conventional address conversion process is omitted. This speeds up addressing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of logical addresses ACR0 and ACR1 in an embodiment of the present invention.

FIG. 2 is a block diagram showing the flow of processing when implementing the present invention.

FIG. 3 is a schematic diagram of an adder that executes logic-actual coincidence determination processing.

[Explanation of symbols]

(1) Determine whether the approximate logical address belongs to the logical-actual matching space in Figure 2. (2) If the approximate logical address belongs to the logical-actual matching space, the approximate logical address is directly equivalent to the real address. Become(
3) If the approximate logical address does not belong to the logical-actual matching space, it is converted to a real address by the address translation mechanism.

Claims (1)

[Claims] Claim 1: In a computer having a virtual space, S
At G time, the space between the appropriate logical address and the logical address is made to match the logical address and the real address to make it a logical-real matching space. Allocate programs, control tables, etc. to be used in the logical and actual matching space, notify the hardware of the range of the logical and actual matching space, and when address conversion occurs,
The hardware determines whether the logical address to be translated belongs to the logical-actual matching space, and if it belongs to the logical-actual matching space, the conventional address translation process is omitted and the approximate logical address is used as the real address as it is. A high-speed addressing method characterized by comprising: