JPH04304076A - Video signal processor - Google Patents

Abstract

PURPOSE:To enable the video signal processing without sticking a black or a white trimming at the contour part by raising the slope itself without sticking a chute to the edge part. CONSTITUTION:When the video signal from an input terminal 1 is supplied to an edge detection circuit 12 and the output is supplied to an absolute value circuit 13. The signal delayed for a picture element is outputted from the edge detection circuit 12 and is supplied to a hold circuit 17. The output from the absolute value circuit 13 is supplied to a maximum value position detection circuit 14 and the output is supplied to a clock control circuit 16 with the clock signal from a clock input terminal 11 after the output is inverted in an inversion circuit 15. The output from the clock control circuit 16 and the signal delayed for a picture element from the edge detection circuit 12 are supplied to the hold circuit and the output signal is outputted from an output terminal 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for compensating for edge portions of a video signal in a color television receiver.

0002

2. Description of the Related Art Conventionally, in color television signal transmission systems, because the transmission band is limited, the sharpness of images reproduced by a television receiver is reduced. for example,
In the NTSC system, the luminance signal band is 0 to 4.2[
MHz]. For this reason, even when shooting with an ideal image pickup tube, the signal when the luminance signal changes between black and white will not be sharper than a certain value on the rising and falling slopes of the signal on the receiver, and the contours will appear on the screen. appears slightly blurred.

[0003] In order to improve such image blur,
Contour compensation is performed by creating a second-order differential using a delay line and adding it to the original signal.

FIG. 3 shows a block diagram of this conventional video signal processing device, in which 1 indicates a video signal input terminal;
21 and 22 are one-pixel delay lines, 23, 24, and 25 are multipliers, 26 is an adder, 27 is a gain controller that changes the contour compensation level, 28 is an adder, and 2 is an output terminal. (FIG. 4) shows operating waveforms at each part a to i of this circuit.

The operation of the circuit will be explained below with reference to FIGS. 3 and 4. First, in FIG. 3, the video signal input from the input terminal 1 is transferred to the delay line 21
supplied to. The output of the delay line 21 is sent to the delay line 22 and the multiplier 2.
4 and adder 28. The output of delay line 22 is supplied to multiplier 25. For example, input terminal 1 (point a)
If a video signal waveform as shown in FIG. 4(a) is input, the waveforms at points b and c will be as shown in FIG. 4(b) and (c). The waveforms at points a, b, and c are respectively multiplier 2
3, 24, and 25. The coefficient of each multiplier is Ka=
-1, Kb=2, and Kc=-1, waveforms shown in FIGS. 4(d), (e), and (f) are obtained at points d, e, and f. These three waveforms are added to adder 26, resulting in g
At the point, a waveform obtained by second-order differentiation of the original signal as shown in FIG. 4(g) is obtained. The output of the adder 26 has its amplitude adjusted by a gain controller 27 with an arbitrary gain, and is added to the adder 28 . For example, if the gain is 1/2,
At point h, a waveform shown in FIG. 4(h) is obtained. The output of the gain controller 27 is added to the adder 28 together with the output of the delay line 21, and at point i, the waveform shown in FIG. 4(i) is obtained and output from the output terminal 2.

In the conventional video signal processing device configured as described above, a waveform with sharp edges is obtained.
Contour compensation is performed.

[0007]

[Problems to be Solved by the Invention] However, the above configuration has the problem that undershoots and overshoots are added to the edge portions, resulting in white or black borders being attached to the outline portions of the image. was.

In view of the above, the present invention provides a video signal processing device that performs video signal processing by increasing the slope of the edge portion itself, instead of processing the video signal by attaching a chute to the edge portion. The purpose is to

[0009]

[Means for Solving the Problems] The present invention includes: an edge detection circuit that detects an edge portion from a video signal supplied as an input; an edge signal control circuit that controls a signal of the edge portion detected from the output; A video signal processing device comprising: a clock signal control circuit that controls a clock signal at an edge portion from the output; and a hold circuit that controls a video signal using the clock signal generated by the circuit.

0010

[Operation] With the above-described configuration, the present invention allows the slope itself to stand up without adding a chute to the edge portion, so that video signal processing can be performed without adding white or black borders to the outline portion of the image.

[0011]

Embodiment (FIG. 1) shows a block diagram of a video signal processing apparatus in an embodiment of the present invention. (FIG. 1), 1 is a video signal input terminal, 11 is a clock input terminal, 12 is an edge detection circuit, 10 is an edge signal control circuit,
13 is an absolute value circuit, 14 is a maximum value position detection circuit, 15 is an inversion circuit (for example, a NOT circuit), 16 is a clock control circuit (for example, an AND gate), 17 is a hold circuit (for example, a D flip-flop), and 2 is an output terminal. It is. In this circuit, first, a video signal input from an input terminal 1 is supplied to an edge detection circuit 12, and its output is supplied to an absolute value circuit 13. In addition, the edge detection circuit 12
A signal delayed by one pixel is output from , and is supplied to the hold circuit 17 . The output of the absolute value circuit 13 is supplied to the maximum value position detection circuit 14, and after being inverted by the inverting circuit 15, the output is supplied to the clock control circuit 16 together with the clock signal input from the clock input terminal 11. The output of the clock control circuit 16 and the video signal delayed by one pixel from the edge detection circuit 12 are supplied to a hold circuit 17, and its output signal is outputted from the output terminal 2.

The operation of the video signal processing apparatus of this embodiment configured as described above will be explained below.

FIG. 2 shows operating waveforms at each part a to i of this circuit. For example, if the video signal waveform shown in (Fig. 2(a)) is input from the input terminal 1, the edge portion of this signal is detected by the edge detection circuit 12, and at point b, the video signal waveform shown in (Fig. 2(b)) is input. The waveform is output. This waveform is supplied to the absolute value circuit 13, and the absolute value is taken (FIG. 2(c)). Further, the edge detection circuit 12 outputs a signal delayed by one pixel, and the hold circuit 17 outputs a signal delayed by one pixel.
is being supplied to. The output waveform from the absolute value circuit 13 is determined by the maximum value position detection circuit 14 to be the maximum value or more than a certain threshold value, and its position is detected ((FIG. 2(d)).Furthermore, it is inverted by the inversion circuit 15 and At the point (Figure 2(e))
The waveform shown is obtained. This output waveform is input to the clock control circuit 16 together with the clock signal input from the clock input terminal 11 (FIG. 2(f)), and at point g (
A pulse signal shown in FIG. 2(g) is output. According to this controlled clock signal, the video signal delayed by one pixel from the edge detection circuit 12 (FIG. 2(h)) is controlled by the hold circuit 17, and is output as the waveform shown in FIG. 2(i). Output from terminal 2.

As described above, according to this embodiment, a new clock signal can be obtained by detecting the edge portion of the input video signal by the edge detection circuit and controlling the clock input signal based on this. By providing a hold circuit for controlling the video signal using this controlled clock signal, the slope of the edge portion of the video signal can be increased, and video signal processing without shoots can be performed. As a result, a clear image without white or black borders can be obtained.

Note that a hold circuit based on analog processing may be used as the hold circuit.

[0016]

As explained above, there is provided an edge detection circuit that detects an edge portion from a video signal supplied as an input, an edge signal control circuit that controls a signal of an edge portion detected from the output, and the output By providing a clock signal control circuit that controls the clock signal at the edge portion of the video signal and a hold circuit that controls the video signal using the clock signal generated by the circuit, the slope of the edge portion of the video signal is increased. Video signal processing without shooting can be performed. As a result, it is possible to obtain a clearer, more natural image without white or black borders around the outline, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video signal processing device in an embodiment of the present invention.

FIG. 2 is an operational waveform diagram of the same embodiment.

FIG. 3 is a block diagram of a conventional video signal processing device.

FIG. 4 is an operational waveform diagram of a conventional example.

[Explanation of symbols]

10 Edge signal control circuit 12 Edge detection circuit 16 Clock control circuit 17 Hold circuit

Claims (2)

[Claims] 1. An edge detection circuit that detects an edge portion from a video signal supplied as an input, an edge signal control circuit that controls a signal of the edge portion detected from the output, and a clock signal at the edge portion from the output. 1. A video signal processing device comprising: a clock signal control circuit for controlling a video signal; and a hold circuit for controlling a video signal using a clock signal generated by the circuit. 2. The video signal processing device according to claim 1, wherein the clock signal control circuit deletes the clock signal at an edge portion.