JPH04302895A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a large capacity DRAM without sharply increasing the chip area and to improve a production yield of the peripheral circuit section. CONSTITUTION:Plural peripheral circuit sets 71 and 72 are provided as a peripheral circuit section 7 of the DRAM chip. Each of the sets 71 and 72 are divided into plural blocks Pij which can be replaced by the corresponding block of the other set and also by selecting the combination of the block Pij, which operates normally, a normally operating peripheral circuit section is configured.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (DRAM) with integrated dynamic memory cells, and more particularly to improvements in peripheral circuitry.

0002

BACKGROUND OF THE INVENTION DRAM is the most suitable for increasing capacity among semiconductor memory devices, and currently samples of 16 Mbit DRAM using 0.5 μm design rule are being shipped.
64M using 0.35-0.4μm design rule
Bit DRAM is in the prototype stage. As the degree of integration continues to advance, it is expected that 4GM bit DRAMs using the 0.1 μm design rule will appear in the early 21st century.

[0003] In a DRAM of 4 Mbit level or higher where the design rule is 0.1 μm or less, the gate length is 0.1 μm or less.
A MOS transistor with a size of less than μm is used, and the number of impurities in its channel portion is on the order of 10 2 . As a result, the threshold voltage deviates significantly from the set value due to statistical fluctuations, and the transistor no longer operates normally. When the contact portion is also less than 0.1 μm square, the probability that its resistance becomes infinite increases due to fluctuations in the number of impurities.

In a DRAM chip, it is the peripheral circuit section, not the core section such as the memory cell array section, row decoder, column decoder, sense amplifier, etc., that is most affected by such a decrease in the yield of MOS transistors. The reason for this is that the same circuits are often repeated in the memory cell array section and core circuit section, so while it is possible to replace a defective section with a normally functioning section with a slight increase in area using so-called redundant circuit technology, the peripheral circuit section This is difficult because it is essentially random logic. In other words, if we try to apply redundancy technology to the peripheral circuit section, multiple sets of peripheral circuit sections are required, and if there is a defective transistor at even one place in a set, that set is considered defective and must be replaced with another set. , if the capacity is increased, the chip area will increase significantly.

FIG. 7 shows this situation. FIG. 7 shows how the yield of the peripheral circuit section changes for each generation when a plurality of sets of peripheral circuits are provided. The horizontal axis is 1
This is the failure rate of peripheral circuits in a set, and corresponds to the generation of DRAM. According to this, at the 16 Gbit level, the failure rate of one peripheral circuit is as high as 40%, so a yield of 90% or more cannot be ensured unless there are three or four sets or more of peripheral circuits.

Moreover, since the area of one set of peripheral circuits relative to the chip is as large as about 8%, increasing the number of sets by this amount leads to an increase in the chip area of 20 to 30% (see the broken line in FIG. 5). As a result, the value obtained by dividing the area of the peripheral circuit section by the operating probability of the peripheral circuit, that is, the value proportional to the cost of the peripheral circuit, is only about 75% compared to the case where there is no redundancy in the peripheral circuit (Figure 6 ).

[0007]

[Problems to be Solved by the Invention] As described above, in a large capacity DRAM with a design rule of 0.1 μm, the yield of the peripheral circuit section decreases due to the decrease in the yield of MOS transistors that constitute the peripheral circuit, and it is necessary to increase the number of peripheral circuit sections. Although providing a set slightly improves the yield, there is a problem in that the chip area increases significantly.

The present invention provides a DRA that improves the yield of peripheral circuitry without significantly increasing the chip area.
The purpose is to provide M.

[Configuration of the invention]

0010

[Means for Solving the Problems] A DRAM according to the present invention is provided with a plurality of sets of peripheral circuit sections, each set is divided into a plurality of blocks that can be replaced with corresponding blocks in other sets, and The present invention is characterized in that a peripheral circuit section that operates normally is constructed by selecting a combination of blocks that operate normally.

[0011]

According to the present invention, one set of peripheral circuits is divided into a plurality of blocks, and each block can be replaced with another set. Therefore, within one set, 1
Compared to conventional redundant circuit systems in which the entire set is considered defective even if a transistor is defective in one location, it is possible to improve the yield of peripheral circuits without significantly increasing the chip area.

0012

Embodiments Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 shows the overall configuration of a DRAM chip according to an embodiment of the present invention.

As is well known, the memory cell array 1 is composed of one transistor/one capacitor dynamic memory cells arranged in a matrix. In the memory cell array 1, a plurality of word lines and bit lines are arranged to cross each other, and the memory cells are driven by the word lines and exchange data with the bit lines. The row decoder 2 selects a word line, and the address buffer 3 (including a partial decoder) takes in an external address and generates an input signal for the row decoder 2.

A sense amplifier 4 is provided at the end of the bit line of the memory cell array 1 for amplifying read data, and also generates a column selection signal for selectively transmitting the data on the bit line to the data input/output line. A column decoder 5 is provided. The data input/output circuit 6 is a buffer circuit that exchanges data between the data input/output line and the data input/output pin.

The peripheral circuit section 7 receives a row address strobe signal /RAS and a column address strobe signal /C.
It is controlled by external control signals such as AS and write enable signal /WE, and sequentially generates signals that drive the address buffer 3, row decoder 2, sense amplifier 4, column decoder 5, and data input/output circuit 6. Its basic configuration is a clock generator using an inverter chain.

The peripheral circuit section 7 is composed of a plurality of peripheral circuit sets, each of which is divided into a plurality of blocks.

FIG. 2 shows a specific example of the peripheral circuit section 7 composed of a plurality of sets. In the illustrated case, the peripheral circuit section 7 includes a first peripheral circuit set 71 and a second peripheral circuit set 72 .

The first peripheral circuit set 71 is divided into five blocks P11, P12, . . . , P15. The first block P11 receives the row address buffer drive signal (φIN) with a certain delay after /RAS input (φIN).
This is the part that generates out1). The second block P12 is a portion that generates a row decoder drive signal (φout2) with a certain delay after the row address buffer 3 is activated. The third block P13 is a portion that generates a word line drive signal (φout3) with a certain delay after the row decoder 2 is activated. The fourth block P14 outputs a signal (
This is the part that generates φout4). The fifth block P15 is a RAS system operation end signal (φout5)
This is the part that generates.

The second peripheral circuit 72 is similarly divided into five blocks P21, P22, . . . , P25.

In the block Pij shown above, i is the set number and j is the block number, and between the first and second peripheral circuit sets 71 and 72, those with the same block number j have the same function. and can be substituted between sets.

First and second peripheral circuit sets 71 and 72
A test circuit 8 is provided in order to test the quality of each block Pij in advance. Each block P
In order to connect ij individually to the test circuit 8, switch circuits SWiI, SWiO and SWTI, SWTO are used.
is provided.

First and second peripheral circuit sets 71 and 72
Each block P can be selected to configure a desired peripheral circuit by selecting one of the two corresponding blocks
Fuse SWijI,
SWijO is provided. Fuse SWijI
, SWijO connects blocks that operate normally to the output terminals of the drive signals φout1 to φout5, and disconnects unnecessary portions according to the test results by the test circuit 8, so that blocks that do not operate normally are disconnected. These fuses SWijI and SWijO may not be actual fuses, but the test circuit 8 may have their functions.

Specifically, for example, blocks P12 and P15
, P24 does not operate normally, φIN-P11-
φout1-P22-φout2-P13-φout3
The connections -P14-φout4-P25-φout5 constitute a peripheral circuit that operates normally. As a result, the timing of the clock generated from the peripheral circuit section is
The result will be as shown in Figure 4.

In this embodiment, each block Pij is designed to have a dimension that has an amplification function, and when the number of sets increases by one, the DRAM chip area increases by about 9%.

FIG. 5 shows the relationship between the number of peripheral circuit sets and the increase in chip area and the operation probability of the peripheral circuit section according to this embodiment, and FIG. 6 shows the relationship between the number of peripheral circuit sets and the cost of the peripheral circuit section. . In these figures, the case where a peripheral circuit set is provided using a conventional redundant circuit system is indicated by a broken line. As is clear from FIG. 5, according to this embodiment, even if the number of peripheral circuit sets is the same as the conventional one, the operating probability of the peripheral circuit section, that is, the yield, is significantly improved.

Furthermore, as is clear from FIG. 6, in this embodiment, when there are two sets of peripheral circuits, the value proportional to cost is the minimum (the value is 68), and the total area of the peripheral circuit section at that time is , 9% of the entire DRAM chip area
×2=18[%]. In contrast, in the conventional example, 3
The set is the smallest (its value is 75), and the total area of the peripheral circuit section at that time is 8 [%] x 3 = 24 [%], so in this example, the chip is 6% smaller than the conventional one. A cost reduction of 7% can be achieved based on area.

FIG. 3 shows the configuration of a peripheral circuit section according to a second embodiment of the present invention. The parts corresponding to the embodiment in FIG. 2 are shown in FIG.
The same reference numerals will be used to omit the detailed explanation. In this embodiment, the peripheral circuit section consists of three sets 71, 72 and 73. The fact that each peripheral circuit set is composed of five blocks Pij is the same as in the previous embodiment, but in this embodiment, each block Pij itself is not in the dimension that has the amplification function, but is composed of two blocks. Operation becomes possible only when connected in parallel. Therefore, the quality of each block Pij is checked in advance by the test circuit 8, and the peripheral circuit is constructed using two normally operating blocks among the three corresponding blocks.

For example, blocks P12, P24, P15
If it does not operate normally, the following connection is made in this embodiment. Blocks in parentheses indicate blocks connected in parallel.

[0030]φIN-(P11/P21)-φout1
-(P22/P32)-φout2-(P13/P23
)-φout3-(P14/P34)-φout4-(
P25/P35)-φout5 Also according to this example,
Almost the same effects as in the previous embodiment can be obtained.

[0031]

As described above, according to the present invention, the peripheral circuit set is divided into blocks, the quality of each block is determined, and the final peripheral circuit is constructed by combining them. Although the number is the same as the conventional one, the yield of the peripheral circuit section is significantly improved compared to the conventional DRA.
You can get M.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a DRAM of the present invention.

FIG. 2 is a diagram showing the configuration of a peripheral circuit section of the first embodiment.

FIG. 3 is a diagram showing the configuration of a peripheral circuit section of a second embodiment.

FIG. 4 is a diagram showing the timing of an output clock obtained by a peripheral circuit section.

FIG. 5 is a diagram showing the relationship between the number of sets, chip area, and peripheral circuit operation probability according to the first embodiment.

FIG. 6 is a diagram showing the relationship between the number of sets and peripheral circuit cost according to the first embodiment.

FIG. 7 is a diagram showing the yield of DRAM peripheral circuits using conventional redundant circuit technology.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...Memory cell array, 2...Row decoder, 3...Address buffer, 4...Sense amplifier, 5...Column decoder, 6...Input/output circuit, 7...Peripheral circuit section, 71, 72, 73...Peripheral circuit set, 8...Test Circuit, Pij…block. SWijI, SWijO...Fuse, SWijI,S
WiO, SWTI, SWTo...Switch.

Claims (3)

[Claims] 1. A memory cell array in which word lines and bit lines are arranged to cross each other, and dynamic memory cells are arranged in a matrix and are driven by the word lines and exchange data with the bit lines; A row decoder that selects a word line, an address buffer that generates an input signal for the row decoder, a sense amplifier that amplifies data read to the bit line, and selectively transfers data on the bit line to a data input/output line. A column decoder that generates a column selection signal for transmission, a data input/output circuit that exchanges data between the data input/output line and the data input/output pin, and an external control signal that controls the address buffer and row. A peripheral circuit section that sequentially generates signals for activating a decoder, a sense amplifier, a column decoder, and a data input/output circuit, and a plurality of sets of the peripheral circuit section are provided, and each set corresponds to a corresponding block in the other set. What is claimed is: 1. A dynamic semiconductor memory device comprising: a peripheral circuit section which is divided into a plurality of blocks that can be replaced with each other; and a peripheral circuit section that operates normally is configured by selecting a combination of blocks that operate normally. 2. The peripheral circuit section is configured of an inverter chain, and includes a block that generates a row address buffer drive signal in response to an /RAS input, a block that generates a row decoder drive signal in response to an output of this block, and this block. It is divided into a block that receives the output of this block and generates a word line drive signal, a block that receives the output of this block and generates a sense amplifier activation signal, and a block that receives the output of this block and generates a RAS system operation end signal. 2. The dynamic semiconductor memory device according to claim 1, further comprising a fuse for selecting and connecting an arbitrary block across a plurality of sets at the input/output terminal of each block. 3. The dynamic semiconductor memory device according to claim 1, further comprising a test circuit for determining the quality of each block.