JPH042978B2 - - Google Patents
Info
- Publication number
- JPH042978B2 JPH042978B2 JP59183926A JP18392684A JPH042978B2 JP H042978 B2 JPH042978 B2 JP H042978B2 JP 59183926 A JP59183926 A JP 59183926A JP 18392684 A JP18392684 A JP 18392684A JP H042978 B2 JPH042978 B2 JP H042978B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- request
- data
- cache memory
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 claims description 191
- 238000012546 transfer Methods 0.000 claims description 13
- 230000010365 information processing Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 25
- 238000012545 processing Methods 0.000 description 24
- 230000008569 process Effects 0.000 description 10
- 230000006870 function Effects 0.000 description 8
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 238000001125 extrusion Methods 0.000 description 3
- 238000011010 flushing procedure Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 239000003607 modifier Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59183926A JPS6162149A (ja) | 1984-09-03 | 1984-09-03 | メモリ制御装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59183926A JPS6162149A (ja) | 1984-09-03 | 1984-09-03 | メモリ制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6162149A JPS6162149A (ja) | 1986-03-31 |
JPH042978B2 true JPH042978B2 (fr) | 1992-01-21 |
Family
ID=16144224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59183926A Granted JPS6162149A (ja) | 1984-09-03 | 1984-09-03 | メモリ制御装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6162149A (fr) |
-
1984
- 1984-09-03 JP JP59183926A patent/JPS6162149A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6162149A (ja) | 1986-03-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA1124888A (fr) | Hierarchie de memoire multiniveau integree pour systeme de traitement de donnees avec capacite amelioree d'ecriture canal a memoire | |
EP0077451B1 (fr) | Sous-système de mémoire à antémémoire court-circuitable | |
EP0072179B1 (fr) | Effacement d'adresses invalides dans une mémoire cache | |
JP4316016B2 (ja) | 複数のシステムバスを有するコンピュータシステムにおいてメモリコヒーレンスを維持するためのシステムおよび方法 | |
US5201041A (en) | Cache bypass apparatus | |
US6122712A (en) | Cache coherency controller of cache memory for maintaining data anti-dependence when threads are executed in parallel | |
US5802582A (en) | Explicit coherence using split-phase controls | |
EP0303661B1 (fr) | Unite de traitement centrale pour systeme de traitement de donnees numeriques comprenant un mecanisme de gestion a tampon d'ecriture | |
US4912631A (en) | Burst mode cache with wrap-around fill | |
JP5039913B2 (ja) | ロッキング・キャッシュを用いる直接的保存 | |
US20030028728A1 (en) | Cache memory control device | |
JPH0576060B2 (fr) | ||
CA2182841C (fr) | Systeme multiprocesseur et methode de synchronisation des processeurs | |
EP0159713B1 (fr) | Dispositif de commande pour la mixtion de portions de données dans une antémémoire | |
EP0533427B1 (fr) | Système de commande de mémoire d'ordinateur | |
US5717894A (en) | Method and apparatus for reducing write cycle wait states in a non-zero wait state cache system | |
EP0567355B1 (fr) | Procédé et dispositif d'exploitation d'un système d'ordinateur multiprocesseur in antémémoires | |
US6490662B1 (en) | System and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module | |
EP0375864A2 (fr) | Contournement d'antémémoire | |
US6021466A (en) | Transferring data between caches in a multiple processor environment | |
US5696938A (en) | Computer system permitting mulitple write buffer read-arounds and method therefor | |
US5535358A (en) | Cache memory control circuit and method for controlling reading and writing requests | |
JPH042978B2 (fr) | ||
US5636365A (en) | Hierarchical buffer memories for selectively controlling data coherence including coherence control request means | |
JPH0353658B2 (fr) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |