JPH042961B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention converts a user program in machine language in a programmable controller into a relay ladder circuit diagram having an equivalent sequence control function and outputs it to a display device. -Relates to a circuit diagram output device for a user program in a programmable controller that realizes sequence control in a controller.

The conventional circuit diagram output device for user programs in this type of programmable controller is
Before converting to a circuit diagram, check the machine language user program for grammatical errors, and display a message saying ``grammar error exists'' for parts that contain grammatical errors that cannot be converted to relay ladder circuit diagrams. However, the unfinished ladder schematic for that part was not displayed.

Therefore, from the display of the relay electrical ladder circuit diagram that includes such an error message, it is possible to determine how the syntax error is being committed and how to correct the syntax error by correcting the intended user program. Should I make a modification to
The problem was that it was very difficult to understand.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to automatically and rationally correct a machine language user program containing grammatical errors, and to transfer the corrected user program to a relay computer. It outputs to the display device in the form of a ladder circuit diagram, and also displays instructions added for correction in a way that can be distinguished from other instructions. An object of the present invention is to provide a circuit diagram output device for a user program in a programmable controller, which makes it easy to see what examples exist.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

First of all, the user program of the programmable controller targeted by one embodiment of the circuit diagram output device described below is composed of the following instructions.

(1) Data read command: Pushes down the data of the 1-bit accumulator to the stack register, and reads the 1-bit data of the specified number into the accumulator. Below is this data reading command
It is called LD command.

(2) Logical operation instruction... Performs a logical operation on the 1-bit data of the specified number and the data of the accumulator,
Store the result in the accumulator. Some of these logical operation instructions include AND
It includes an instruction and an OR instruction that performs a logical sum.

(3) Stack operation instruction: Performs a logical operation on the 1-bit data obtained by pulling up the stack register and the data in the accumulator, and stores the result in the accumulator. These stack operation instructions include an ANDLD instruction that performs logical product, and an ORLD instruction that performs logical sum.

(4) Data output command: Transfers the data of the accumulator to the data area of the specified number, and pulls up the data from the stack register to the accumulator. Below is this data output command
It is called an OUT command.

A machine language user program consisting of a combination of the above instructions expresses a sequence control function equivalent to an arbitrary relay ladder circuit diagram, and the programmable controller performs the above sequence control by repeatedly executing the user program at high speed. It is something that will be realized.

The circuit diagram output device of the present invention converts the user program composed of the above-mentioned machine language into a relay ladder circuit diagram having an equivalent sequence control function, and outputs the converted circuit diagram to a CRT display device or the like. A schematic electrical configuration of this circuit diagram output device is shown in FIG. This circuit diagram output device includes a central processing unit 1 consisting of a microcomputer,
RAM 3, and an operating device 4 consisting of a keyboard or the like that provides various inputs to the central processing unit 1;
A display device 5 for displaying a relay electrical ladder circuit diagram on a CRT or the like is provided. A programmable controller 2 is connected to the central processing unit 1 mentioned above. The central processing unit 1 reads a machine language user program from the programmable controller 2 and stores it in the input table 31 of the RAM 3. This input table 3
The user program stored in 1 is checked for grammatical errors and corrected using an edit table 32, LD stack 34, and work area 35, and the corrected machine language user program is stored in an output table 33. Then, the modified user program stored in the output table 33 is converted into circuit diagram data of a relay ladder circuit diagram, and the data is displayed on the display device 5. At that time, the instruction added for modification is displayed in a different display form from other instructions.

FIGS. 2A to 2D are flowcharts showing the structure of a processing program executed by the central processing unit 1 for checking for grammatical errors and correcting them. Prior to a detailed explanation of this flowchart, the main points of the method of checking and correcting grammar errors of the present invention will be explained.

When the above LD instruction is executed by the programmable controller 2, meaningful data is taken into the accumulator, and the data received in the accumulator is pushed down to the stack. Therefore, for example, if the LD instruction is repeated twice, there will be two meaningful data: 1 bit in the stack and 1 bit in the accumulator.

When the above stack operation instruction is executed by the programmable controller 2, the first bit of the stack register is pulled up, a logical operation is performed on the data in the accumulator, and the result is stored in the accumulator. Therefore, the meaningful data stored in the stack register by the stack operation instruction is reduced by one bit.

When the above-mentioned OUT instruction is executed by the programmable controller 2, the data in the accumulator is transferred to another area, and the data is pulled up from the stack register to the accumulator. Therefore, the meaningful data stored in the accumulator is decreased by one due to the OUT instruction.

When the above logical operation instruction is executed by the programmable controller 2, a logical operation is performed on the data in the accumulator and data from another area, and the result is stored in the accumulator.
Therefore, logical operation instructions neither increase nor decrease the number of meaningful data in the accumulator.

As mentioned above, the meaningful data stored in the accumulator and stack, which is increased by the LD instruction and decreased by the stack operation instruction and the OUT instruction, will be referred to as significant data in the following explanation.

To execute the above logic operation instruction, there must be significant data in the accumulator. In other words, a logical operation instruction requires at least one piece of significant data.

In order to execute the above stack operation instruction, the stack and the accumulator must each have significant data. That is, a stack operation instruction requires at least 2 bits of significant data.

To execute the above OUT instruction, significant data must be stored in the accumulator. In other words, the OUT instruction requires at least one bit of significant data.

In this embodiment, when the following conditions occur in a machine language user program,
This is defined as a syntax error.

(a)...The number of significant data is 0 when the logical operation instruction is executed (b)...The number of significant data is 0 when the OUT instruction is executed Case (c)...If the number of significant data is less than 2 when the stack operation instruction is executed (d)...If the number of significant data does not become 0 as a result of executing the OUT instruction (e)... When the last instruction of the program is not an OUT instruction In the device of this invention, the user program in machine language is checked in order from the beginning, and if any of the syntax errors (a) to (e) above are detected, Correct the error by adding an LD or OUT instruction as appropriate.

(A)...When the syntax error in (a) above is detected, insert an LD instruction immediately before the logical operation instruction.

(B)...When the grammar error in (b) above is detected,
Insert the LD instruction just before the OUT instruction.

(C)...When the syntax error in (c) above is detected, insert one or two LD instructions immediately before the stack operation instruction.

(A)...When the grammar error in (d) above is detected,
Insert the OUT instruction immediately before the LD instruction before the OUT instruction. If the significant data does not become 0 even after adding one OUT instruction, an OUT instruction is further inserted immediately before the previous LD instruction.

(E)...When the syntax error in (e) above is detected, add an OUT instruction to the end of the program, and if the addition does not reduce the number of significant data to 0, perform the same process as in (D) above. Add more OUT instructions by

In this embodiment, a grammatical error in a machine language user program is defined as described above, and the detected grammatical error is corrected as defined above.

Next, I will give an example of the above grammar error and its correction. FIG. 3A is an example of a machine language user program containing a grammatical error, and FIG. 3B is a machine language user program in which the grammatical error has been corrected. In the following explanation, the LD instruction or OUT instruction inserted to correct a syntax error will be referred to as a dummy LD instruction or a dummy OUT instruction.
For these dummy instructions, an X is written in the operand area.

In the example program in Figure 3A, address 1
The two LD instructions at address 2 reduce the number of significant data to 2, and the OUT instruction at address 3 reduces the number of significant data by one, but one significant data still remains. In other words, address 3
The syntax error (d) above is detected when the OUT instruction is checked. (D) above to fix this
When the processing is done, as shown in Figure 3B,
A dummy OUT instruction “OUT・X” is inserted immediately before the “LD26” instruction. This results in
By executing the "OUT27" instruction, the number of significant data is corrected to zero.

Further, in FIG. 3A, one significant data is required to execute the "AND28" instruction at address 4, but that significant data is already absent, so the syntax error (a) above is detected. This syntax error is corrected by processing (A) above. In other words, the third
As shown in Figure B, a dummy LD command "LD.X" is inserted immediately before the "AND28" command. As a result, the number of significant data becomes 1.

Also, "ORLD" at address 5 in Figure 3A.
To execute an instruction, two pieces of significant data are required. However, at this time, the number of significant data is one, so the above-mentioned (c) grammatical error is detected. This syntax error is corrected by the processing in (C) above.
That is, as shown in FIG. 3B, a dummy LD instruction "LD.X" is inserted immediately before the "ORLD" instruction. Also, by adding this modification,
Significant data becomes 1 after execution of the "ORLD" instruction.

Also, as shown in Figure 3A, the last of this program does not end with the OUT instruction, so the above (e)
syntax errors are detected. This syntax error is corrected by processing (E) above. In other words, as shown in Figure 3B, at the end of the program, a dummy
OUT command "OUT・X" command is added. With this modification, the number of significant data becomes 0 after the last OUT instruction is executed, so no more OUT instructions are added.

Then, as shown in FIG. 3B, the modified user program in machine language is converted into a relay ladder circuit diagram having the same sequence control function as that program by a well-known disassembly process.
It is displayed on the display screen of the display device 5. The relay ladder circuit diagram is shown in FIG. 3C. In the circuit diagram of FIG. 3C, those marked with X are circuit elements corresponding to the dummy LD instruction or OUT instruction. In this way, the dummy LD or OUT instructions added to correct syntax errors are displayed in a way that they can be distinguished from other instructions.

In this way, a user program containing a grammatical error like the one shown in Figure 3A cannot be converted into a relay electrical ladder circuit diagram using well-known disassembly processing.
After correcting grammatical errors as shown in FIG. 3B, it can be displayed as a relay ladder circuit diagram as shown in FIG. 3C by a well-known disassembly process.
As a result, users are better able to recognize and correct grammatical errors if they are displayed in the form of a ladder circuit diagram as shown in Figure 3C, rather than simply being informed that there is a ``grammatical error.'' This is a very convenient translation.

Next, the processing contents of each step in the flowchart of FIGS. 2A to 2B showing a system program for performing each of the above-mentioned processes will be explained.

FIG. 2A is a flowchart showing the overall outline of the above system program, and FIG. 2B is a flowchart showing the overall outline of the system program.
A flowchart showing the details of the dummy LD instruction creation routine at step 110 in Figure A, and Figure 2C is the second step.
The dummy shown in steps 115 and 107 in Figure A
Detailed flowchart of the OUT instruction creation routine,
FIG. 2D is a detailed flowchart of the modification program editing routine shown in step 108 of FIG. 2A.

Step 100...Clears the program counter PC for addressing the machine language user program transferred to the input table 31,
Define the first instruction of the user program.

Step 101: The command specified by the program counter PC is read from the input table 31 and stored in the editing table 32. Below is this step 101
The command read in is called the main command.

Step 102: Determine whether or not this command is an LD command.

Step 111: Determine whether this instruction is a logical operation instruction.

Steps 114 and 205: Determine whether or not this instruction is a stack operation instruction.

Steps 103, 201, 207...Push one record including this command to the LD stack 34.

Steps 113, 303...Pull one record from the LD stack 34.

Steps 104, 203, 209...The OUT instruction addition pointer of the latest record of the LD stack 34 is set to the storage address in the edit table 32 of the instruction included in that record.

Steps 202, 208...The LD instruction addition pointer of the latest record of the LD stack 34 is set to the storage address in the edit table 32 of the instruction included in that record.

Step 112: The OUT instruction addition pointer of the latest record in the LD stack 34 is updated to the storage address in the edit table 32 of the instruction (on the user program) following the instruction included in that record.

Step 105...Increment the program counter PC by 1.

Step 106: It is determined whether the data in the input table 31 specified by the program counter PC is after the last instruction of the user program, that is, whether the user program has been processed to the end.

Steps 200 and 301... It is determined whether the LD stack 34 is empty.

Step 206: Determine whether only one record is stored in the LD stack 34.

Steps 204, 210...The LD instruction addition counter added to the instruction in the edit table 32 specified by the LD instruction addition pointer of the latest record of the LD stack 34 is incremented by 1.

Step 302: The OUT instruction addition counter added to the instruction in the edit table 32 specified by the OUT instruction addition pointer of the latest record of the LD stack 34 is incremented by 1.

Step 400: Specify the first record of the edit table 32 and read it. This designated record will be referred to as the main record in the following explanation.

Step 401: Determine whether the LD instruction addition counter of this record is 0 or not.

Step 402: A dummy LD instruction is set in the output table 33.

Step 403...The LD instruction addition counter of this record is decremented by 1.

Step 404: Set the command of this record in the output table 33. Step 405: Determine whether the OUT command addition counter of this record is 0. Step 406: Set a dummy OUT command in the output table 33.

Step 407...The OUT instruction addition counter of this record is decremented by 1.

Step 408: Specify the next record in the edit table 32.

Step 409: Determine whether all records in the edit table 32 have been read.

Step 109: Convert the modified user program stored in the output table 33 into display data of a relay ladder circuit diagram, and display the circuit diagram on the display device 5. At this time, the dummy LD instruction and the dummy OUT instruction are displayed so that they can be distinguished from other instructions.

Although one embodiment of the present invention has been described above in detail, the present invention is not limited to the above embodiment, and the present invention is not limited to the above embodiment. Depending on the method, various grammatical error detection methods and grammatical error correction methods can be implemented. Furthermore, various methods can be used to display the dummy LD command and OUT command added for correction differently from other commands.

As described above, the programmable computer according to the present invention
According to the user program circuit diagram output device in the controller, if a machine language user program contains a grammatical error, the grammatical error is automatically corrected according to a certain rule, and the corrected user program is is displayed on the display in the form of a relay ladder circuit diagram, and data read commands and data output commands added for correction are displayed in a form that can be distinguished from other commands, making it easy to recognize program errors. As well as providing guidelines for correction,
Useful for making corrections.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a circuit diagram output device according to the present invention, and FIG. 2 shows a system for checking and correcting grammatical errors in a machine language user program.
A flowchart of a system program for converting and displaying relay ladder circuit diagram data, FIG. 3A is a diagram showing an example of a user program in machine language containing a grammatical error, and FIG. 3B is a flowchart of a system program for converting and displaying relay ladder circuit diagram data.
FIG. 3C is a diagram showing a program after modifications have been made to the program shown in the figure, and FIG. 3C is a diagram showing a relay ladder circuit diagram converted from the modified program in FIG. 3B. 1...Central processing unit, 2...Programmable
Controller, 3... RAM, 4... Operating device,
5...Display device.

Claims (1)

[Scope of Claims] 1. In a circuit diagram output device for a user program in a programmable controller that converts a user program in machine language into a relay electrical ladder circuit diagram having an equivalent sequence control function and outputs it to a display device, 1 Push down the bit accumulator data to the stack register and
An LD instruction that reads bit data into the accumulator, a logical operation instruction that performs a logical operation on 1-bit data of a specified number and the data in the accumulator, and stores the result in the accumulator, and a stack register. 1 obtained by pulling up
A stack operation instruction that performs a logical operation on bit data and data in the accumulator and stores the result in the accumulator, and a stack operation instruction that transfers the data in the accumulator to a data area with a specified number and stores the result from the stack register. Checks the machine language user program consisting of the OUT instruction that pulls up data to the umulator, and sequentially checks the machine language user program consisting of counting means for sequentially calculating the number of significant data stored in a mulrator and a stack; and, when a logical operation instruction is executed, if the count value of the counting means is 0, immediately before the logical operation instruction; means for inserting an LD instruction; means for inserting an LD instruction immediately before the OUT instruction if the count value of the counting means is 0 when the OUT instruction is executed; means for inserting one or two LD instructions immediately before the stack calculation instruction when the count value of the counting means is less than 2 when the count value of the counting means is executed; If the count value does not become 0, insert an OUT instruction before the LD instruction immediately before that OUT instruction, and
If the count value of the counting means does not become 0 just by adding the OUT instruction, there is also a means to insert the OUT instruction immediately before the previous LD instruction, and if the last instruction of the program is not the OUT instruction, the last instruction of the program and means for adding an OUT instruction if the count value of the counting means does not become 0 due to the addition, 1. A circuit diagram output device for a user program in a programmable controller, characterized in that the output device outputs a user program into a circuit diagram in a programmable controller, the output device outputting the command to a display device in a display format that allows the command to be distinguished from other commands.