JPH04291940A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To eliminate the misjudgment of a 'non-write operation' to be a 'write operation' which is caused when write operations and erasure operations are repeated at a nonvolatile memory. CONSTITUTION:According to the number of write operations and erasure operations at a main-body cell, write operations and erasure operations are executed at a reference cell. Thereby, the difference in an electric characteristic between the main-body cell and the reference cell is eliminated and the write operations can be performed in a short time. As a result, the time for a test can be shortened, the performance of the title memory as a chip can be enhanced and the cost of the memory can be reduced.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable and erasable nonvolatile memory, and is particularly suitable for determining whether a cell is "1" or "0" with a greater margin.

0002

[Prior Art] E2 PROM is used in a wide range of fields as a writable and erasable nonvolatile memory.
and programmable Random
Similar to Access Memory), it has write characteristics, erase characteristics, and data retention characteristics, and also has E2
Endurance peculiar to P-ROM
) Characteristics are also important.

The write/erase characteristic is determined by the high potential voltage Vpp (~
20V) as a parameter, it shows the write or erase time dependence of ΔVth, and the data retention characteristic is how long the cell data is retained, that is, the natural emission of electrons from the floating gate. or
This is the time dependence of the value of ΔVth when electrons are naturally injected.

[0004] Furthermore, the endurance characteristic indicates how many times it can operate normally when erasing and writing are repeated, and for the E2 P-ROM cell, when erasing and writing are repeated, This shows how many times the system can operate normally, and the curve is shown in Figure 1.

Moreover, the erase/write cycle is normally guaranteed to be 10,000 times (104 times), and the data retention time is guaranteed to be 10 years in the normal operating temperature range (-40° C. to 80° C.).

As described above, in a programmable and erasable nonvolatile memory such as an EP-ROM cell, writing and erasing are repeatedly performed, but the "1" and "1" of the read cells constituting the main cell are 0", and specifically, this is often done by comparing the cell current of a reference cell.
The advantage of this method is that it is possible to prevent effects such as non-uniformity of cell current caused by variations in gate length that occur during the manufacturing process.

The cell current characteristics before and after writing are shown in FIG. 2. The characteristics before writing are 60 μA when VG = 5V, as shown in FIG. This is done by injecting hot electrons generated by applying a high voltage to 5 or electrons generated by breakdown into the floating gate 3, and the electrons generated at this time are transferred to the gate insulator layer 2 under the floating gate 3 and around the cell It is also captured in an insulator layer (not shown) (see FIG. 5, which shows the state after writing).

On the other hand, the cell current characteristics after writing are mainly affected by the electrons held in the floating gate 3, which causes the threshold voltage to rise and shift as shown in 2 in FIG. 2, resulting in a cell current of 2. .

On the other hand, EPROM is erased by ultraviolet irradiation, but as shown in FIG. 3b, electrons injected and held in the floating gate 3 are given energy from the ultraviolet rays and then released by diffusion. The captured electrons remain as they are, resulting in the state shown in FIG. 5, where the number 2 in FIGS. , 6 is the source.

Therefore, the cell current characteristics after erasing do not completely return to their original state, but shift slightly to the positive side due to the influence of electrons captured in the gate insulator layer, and the cell current also decreases to 55μ.
Become A.

[0011] Since hot electrons generated each time a normal write operation is trapped in the oxide layer, the amount of characteristic shift increases as the number of writes increases.

In order to investigate in the test process whether writing and erasing can be performed normally for the main cell, all cells are in the state shown in FIG. is as shown in Figure 4. To determine whether a cell is "1" or "0", the cell current takes the margin of the reference cell current, and when it is less than that, it is considered to be an off state cell, and if it is The design is such that the cell is considered to be in the on state when the cell is turned on.

For example, when designing with a margin of 20%, the current value of the reference cell is 60 μA, so cells with a current value of 48 μA or less are considered to be off cells.

[0014]

[Problems to be Solved by the Invention] Normally, the margin of reference cell current in nonvolatile memory takes into account variations in the processing process, so if the main cell's typical value is 55 μA, the margin is 20%. Approximately 1
This decreases to 30%, and depending on processing variations, some cells may be considered off cells even though they are on cells.

Changes in cell current characteristics after writing and erasing depend on the writing and erasing circuits, so as the number of times increases, the margin becomes smaller and, depending on variations, the number of defective products increases.

The present invention was developed in view of the above-mentioned circumstances, and aims to eliminate the erroneous determination of "non-write" → "write" that occurs due to writing and erasing.

[Configuration of the invention]

[0018]

[Means for Solving the Problem] In a non-volatile memory, the cell potential of a read cell formed on a semiconductor chip is compared with the cell potential of a reference cell provided on the same chip to determine whether it is "1" or "0". , the nonvolatile memory according to the present invention is characterized in that writing and erasing are performed one or more times in the reference cell.

[0019]

[Operation] Writing and erasing is also performed on the reference cell in accordance with the number of times of writing and erasing on the main cell, thereby eliminating the difference in electrical characteristics between the two.

[0020]

[Embodiment] An EPROM according to an embodiment of the present invention will be described with reference to FIGS. 8, 9a to 9d, and 10.
As is clear from the figure, the silicon chip 10 has a main cell region 1.
1. It is composed of a reference cell 12 and a peripheral circuit (not shown), and its structure is based on the usual two-layer polysilicon system as shown in FIGS. 9a to 9d.

That is, a field oxide layer 14 is formed on a P-type silicon wafer 13 (denoted as wafer because it has not been subjected to a breaking process) by an element isolation process using a so-called selective oxidation method using silicon nitride (see FIG. 9a). rear,
A B ion implantation process for adjusting the threshold voltage is performed in the transistor channel region constituting the EPROM cell and the peripheral circuit to form a B ion layer 15 (see FIG. 9B).

Next, the P-type silicon wafer 13 is oxidized to form a gate oxide layer 16 with a thickness of 25 nm corresponding to the regions where the cell region and transistor region are to be formed, and a first polyimide layer 16 with a thickness of 300 nm is then deposited on the entire surface. silicon layer 17
Cover.

Next, by maintaining the P-type silicon wafer 13 in an oxygen atmosphere, an interpolysilicon oxide layer 18 with a thickness of 50 nm is overlaid near the surface of the first polysilicon layer 17, and then an interpolysilicon oxide layer 18 with a thickness of 300 nm is deposited. Two polysilicon layers 19 are deposited (see FIG. 9b), and P is introduced into the first and second polysilicon layers 17 and 19 by means such as diffusion to adjust the resistance value to a predetermined value.

Subsequently, the first and second polysilicon layers 17 and 19 and the interpolysilicon oxide layer 18 are patterned by a known photolithography method using a photoresist to form portions corresponding to the cell gate 20 and the transistor gate 21. The cross-sectional view shown in FIG. 9c is obtained by ablating the remaining portions, but the portions corresponding to the peripheral transistors are previously ablated.

Here, as an impurity introduction step for each active element, the source 22 and drain 23 for cells and the sources 24 and drains 25 of peripheral transistors are formed by ion implantation and diffusion of N-type impurities such as As.

Furthermore, for example, Al, Al-Si, Al-
A wiring layer (not shown) is provided by depositing Si--Cu or the like to function as an EPROM.

Through these steps, the main cell region 11 for storing data and the "
The refinement cells 12 are formed using "1" and "0" as the determination criteria, but in reality, the main cell region 11 and the refinement cells 12 are formed in an array on a silicon wafer.

[0028] EPRO formed through such a process
The test process for M is performed as follows.

First, the main cell region 1 is formed in an array.
1 is erased using ultraviolet light or electrical means to release electrons from the floating gate, and then all cells are written. is injected into the floating gate.

At this time, writing is performed by applying a high voltage equivalent to that of the main cell to the reference cell, injecting electrons into the floating gate, and finally, all the cells are erased again and the reference cell is also erased.

Each test process of erasing and writing is performed on all cells.
Pass/fail is determined by checking ``1'' and ``0'', and a chip that passes all tests is considered a non-defective product.

Furthermore, when a cell is once erased and rewritten in a state of actual use as a nonvolatile memory, the reference cell is also written and erased in accordance with the number of times.

For example, in the ultraviolet erasing type, writing is performed on the reference cell immediately before erasing the main cell, and since erasing is performed all at once, the reference cell is written and erased once in this process.

In electrically erasable nonvolatile memory,
Similarly, the reference cell may be written immediately before the main cell is erased, or the reference cell may be written and erased independently after the main cell is written.

Alternatively, a method may be used in which the reference cell is rewritten once for every number of times the main cell is rewritten.

As described above, the above embodiment is an example of a single non-volatile memory, but it can also be applied to a non-volatile memory integrated with logic such as a microcomputer, and has the advantage that writing and erasing of the reference cell can be easily controlled. .

[0037]

[Effect of the invention] By using the present invention, writing and
The yield of the erase test (test to check whether the cell has been correctly erased) after erasing or its repetition is improved, and the margin of the criteria for determining whether the cell is "1" or "0" can be reduced, and the write characteristics can be improved. can be improved.

To explain this with reference to FIG. 6, where the horizontal axis is the write time and the vertical axis is the cell current, when the write time is 0, a cell current of 60 μA flows as the center value in the erased state, but there are many cells. Taking into consideration that there will be variations in the case and that the cell current will decrease due to repeated programming and erasing, a certain margin, for example 20%, will be taken from 60 μA to 48 μA.
Using μA as a criterion, a cell with a cell current greater than this is considered a "0" cell, and a cell with less than this is considered a "1" cell.

Then, writing is performed for a time until the cell current of all cells to be written becomes 48 μA or less, including variations, but it takes 100 μs.

On the other hand, when writing/erasing is also performed on the reference cell as in the present invention, there is no need to take into account the decrease in cell current due to repeated writing/erasing, so the 10% margin (54 μA) is used as the standard. can do.

FIG. 9 shows the relationship between the cell current (μA) on the vertical axis and the write time (μsec) on the horizontal axis, and the behavior of the write time is clarified depending on how the margin is taken. ing.

Next, Table 1 below illustrates the relationship between margin setting and writing time.

[0043]

[0044] In this way, the write time for which the cell current of all write cells is less than this can be shorter than that of the conventional technology, that is, the write can be performed in a short time, and the actual write time is shortened, and the test The time required was shortened, improving the performance of the chip and reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the endurance characteristics of E2 P-ROM.

FIG. 2 shows the voltage-current characteristics of a nonvolatile memory cell; 1 shows the characteristics of the cell before writing, 2 shows the characteristics after writing, and 3 shows the characteristics of the cell after writing.

FIG. 3a is a cross-sectional view showing the principle of cell writing. FIG. 3b is a cross-sectional view showing the cell erasing principle.

FIG. 4 is a cross-sectional view illustrating the charged state of a cell before writing.

FIG. 5 is a cross-sectional view illustrating the charged state of a cell after writing.

FIG. 6 is a cross-sectional view showing the charged state of the well after erasing.

FIG. 7 is a plan view showing the entire semiconductor chip.

FIG. 8a is a cross-sectional view after formation of a selective oxide layer on a semiconductor chip. FIG. 8b is a cross-sectional view showing the state after the ion implantation process for adjusting the threshold value into the transistor channel region, the polysilicon deposition process, and the oxidation process. FIG. 8c is a cross-sectional view showing the state after gate formation. FIG. 8d is a cross-sectional view showing the state after forming sources and drains for cells and peripheral transistors.

FIG. 9 is a curve diagram showing the relationship between cell write time and cell current.

[Explanation of symbols]

11: Main cell area, 12: Reference cell, 13: Semiconductor wafer, 14: selective oxide layer, 15: ion implantation layer, 20, 21: Gate, 22, 24: sauce, 23, 25: Drain.

Claims (1)

[Claims] Claim 1: In a non-volatile memory that determines "1" and "0" by comparing the cell potential of a read cell formed on a semiconductor chip with the cell potential of a reference cell provided on the same chip, the reference cell Writable/erasable nonvolatile memory characterized by being written/erased more than once