JPH04290436A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device manufacturing method which facilitates formation of a layer insulating film suitable for levelling the surface of a wiring layer having unevenness without causing leakage. CONSTITUTION:A compression stress insulating film 16 having a thickness not less than 100nm is formed on a wiring layer 14 having unevenness and a PSG film 18 having a thickness not larger than 300nm is formed on the compression stress insulating film 16 by using tetraethyl orthosilicate and ozone to level the surface.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an insulating film is formed to planarize an uneven wiring layer. In recent years, in semiconductor devices, demands for higher integration and higher speed of elements have become increasingly severe. For this reason, multilayer wiring is often used, but in order to have multiple wiring layers, it is necessary to flatten the uneven wiring layer.

0002

[Prior Art] In conventional semiconductor device manufacturing methods, organic SOG or inorganic SOG is used to reduce the level difference in wiring layers.
There are two methods: a method of forming an interlayer insulating film and planarizing it, and a method of forming and planarizing an oxide film using TEOS (tetraethyl orthosilicate, Si(OC2H5)4)) and O3 (ozone), which have excellent coverage. Proposed. However, in the planarization method using an oxide film formed by TEOS and O3, leaks are likely to occur because cracks appear in the formed oxide film and the quality of the oxide film itself is inferior to that of conventional oxide films. was a problem.

0003

[Problems to be Solved by the Invention] As described above, in the conventional method, the oxide film formed by TEOS and O3 is effective for flattening the step, but it is difficult to prevent leakage due to the occurrence of cracks and film quality. There was a problem in that it was not possible to use it as an interlayer insulating film of an actual semiconductor device because it was easy to cause this.

An object of the present invention is to provide a method for manufacturing a semiconductor device suitable for forming an interlayer insulating film suitable for flattening an uneven wiring layer without causing leakage.

[0005]

[Means for Solving the Problems] The above object is to form a compressive stress insulating film on an uneven wiring layer, and to form a PSG film on the compressive stress insulating film using tetraethyl orthosilicate and ozone to form a surface of the compressive stress insulating film. This is achieved by a method for manufacturing a semiconductor device characterized by flattening the surface.

[0006] The above object is to form a compressive stress insulating film on an uneven wiring layer, and to apply PSG on the compressive stress insulating film using tetraethyl orthosilicate and ozone.
This is achieved by a method for manufacturing a semiconductor device, which comprises forming a film, forming an SOG film on the PSG film, and then etching and planarizing the PSG film and the SOG film.

[0007]

[Operation] According to the present invention, after forming a compressive stress insulating film on an uneven wiring layer, a PSG film is formed using tetraethyl orthosilicate and ozone to flatten it, so that cracks do not occur in the PSG film. It is possible to flatten an uneven wiring layer without causing any unevenness.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. After about 700 nm of metal is deposited by sputtering on the portion covered with the insulating film 12 on the semiconductor substrate 10, it is patterned by photolithography to form the wiring layer 14 (FIG. 1(a)). Large irregularities are formed in the wiring layer 14 by patterning.

Next, a compressive stress insulating film 16 having a compressive stress of about 100 nm is formed on the entire surface (FIG. 1(b)).
. As the compressive stress insulating film 16, a film such as an oxide film, a nitride film, an oxynitride film, etc., on which a force in a compressive direction acts on the underlying layer is used. The compressive stress insulating film 16 is made of laminated PSG.
In order to prevent cracks in the film, it is desirable that the film thickness is 100 nm or more and 500 nm or less.

Next, TEOS (tetraethyl orthosilicate, Si(OC2H5)4)) and O3 (ozone)
is used to deposit non-doped PS on the compressive stress insulating film 16.
A PSG film 18 made of G is grown to a thickness of about 300 nm. By doing so, the narrowly spaced portions of the wiring layer 14 are buried and planarized (FIG. 1(c)). The semiconductor device thus formed was subjected to an accelerated load test by performing nitrogen annealing at 450°C for 3 hours and then at 500°C for 30 minutes. No abnormality occurred. Therefore, according to this embodiment, the uneven wiring layer 14 can be flattened without cracking the PSG film 18. Note that the thickness of the PSG film 18 on the convex portion of the wiring layer 14 is 300 mm.
If it is less than nm, the PSG film 1 can be
The film thickness of No. 8 is about 1.2 μm, which is not too thick and does not cause cracks.

A method of manufacturing a semiconductor device according to a second embodiment of the present invention will be explained with reference to FIGS. 2 and 3. Components that are the same as those in the first embodiment are given the same reference numerals and their explanations will be omitted. After about 700 nm of metal is deposited by sputtering on the portion covered with the insulating film 12 on the semiconductor substrate 10, it is patterned by photolithography to form the wiring layer 14 (FIG. 2(a)). In this embodiment, there are parts where the intervals between the patterned wiring layers 14 are wider than in the first embodiment.

Next, a compressive stress insulating film 16 having a compressive stress of about 100 nm is formed on the entire surface (FIG. 2(b)).
. Next, TEOS (tetraethyl orthosilicate, S
Using i(OC2H5)4) and O3 (ozone), P made of non-doped PSG is deposited on the compressive stress insulating film 16.
Grow the SG film 18 to about 1000 nm (FIG. 2(c))
. Even if the PSG film 18 is formed, as shown in FIG. 2(c), the widely spaced portions of the wiring layer 14 are not planarized and fine irregularities remain.

Next, an SOG film 20 is formed by applying SOG to a thickness of about 300 nm over the entire surface, and the fine irregularities of the PSG film 18 are flattened (FIG. 3(a)). Next, the SOG film 20 and PS
Under etching conditions such that the G film 18 has approximately the same etching rate, the final thickness on the wiring layer 14 is approximately 300 nm.
Etch back until the thickness becomes less than m. By doing so, even the wide-spaced portions of the wiring layer 14 are buried and almost completely flattened (FIG. 3(b)). Note that if the thickness of the PSG film 18 on the convex portions of the wiring layer 14 is set to 300 nm or less, the thickness of the PSG film 18 on the concave portions of the wiring layer 14 will be about 1.2 μm, which will prevent cracks from becoming too thick. Does not occur.

As described above, according to this embodiment, the wiring layer 14
Even if there are parts with wide intervals, the PSG film 18 can be flattened without causing cracks. The present invention is not limited to the above embodiments, and various modifications are possible. for example,
In the first and second embodiments described above, non-doped PSG, which is not doped with impurities, was used in the PSG film, but TEOS
When forming the PSG film 18 using PH3 and O3,
TMP (trimethylphosphite, P(OCH3)3
), TMOP (PO(OCH3)3), or other phosphorus sources may be used to form a PSG film doped with phosphorus.

In addition, in the second embodiment, SOG was used to flatten the fine irregularities, but if the etching rate is the same as that of the PSG film and the fine irregularities can be flattened, other materials such as resist may be used. May be used.

[0016]

As described above, according to the present invention, an uneven wiring layer can be flattened without causing cracks in the PSG film.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

10...Semiconductor substrate 12...Insulating film 14...Wiring layer 16...Compressive stress insulation film 18...PSG film 20...SOG film

Claims (2)

[Claims] 1. A compressive stress insulating film is formed on the uneven wiring layer, and a PSG film is formed using tetraethyl orthosilicate and ozone on the compressive stress insulating film to flatten the surface. A method for manufacturing a semiconductor device. 2. A compressive stress insulating film is formed on the uneven wiring layer, a PSG film is formed using tetraethyl orthosilicate and ozone on the compressive stress insulating film, and an SOG film is formed on the PSG film. A method for manufacturing a semiconductor device, characterized in that the PSG film and the SOG film are then etched and planarized.