JPH04290246A - Element isolation method of integrated circuit - Google Patents

Abstract

PURPOSE:To provide the element isolation method, of an integrated circuit, which corresponds to the very small width of a trench and by which a latch-up is not caused by the trench when an element isolation operation is performed by the trench. CONSTITUTION:Trenches 33, 35 which are deeper than the depth of a well are made in an element isolation region whose width is very small. After the inside of the trench has been oxidized or the moment it is oxidized, the upper part of the trench are closed by an interlayer insulating film 31. Thereby, an element isolation operation which does not cause a latch-up is realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit element isolation method, and more particularly to an integrated circuit element isolation method using trench isolation.

0002

2. Description of the Related Art Conventionally, in an integrated circuit such as a CMOS having a MOS transistor, etc., due to its parasitic thyristor structure, as the miniaturization progresses, the region corresponding to the base width becomes narrower, and carrier injection characteristics improve. As a result, latch-up is likely to occur. Therefore, various latch-up countermeasures have been taken in the past. One of the measures against this latch-up is element isolation using trench isolation.

In the conventional device isolation method, the P-type well and the N-type well are separated only by the device isolation film on the surface of the substrate. Due to the formation of parasitic thyristors, the occurrence of parasitic thyristors is unavoidable, and latch-up cannot be completely prevented. However, various studies have shown that it is possible to obtain latch-up-free devices by forming trenches between these wells so that their depth is greater than the depth of the wells. This is becoming clearer.

In the process of actually forming trench isolation, reactive ion etching (hereinafter referred to as "
By forming vertical grooves using a technique called "RIE", isolation regions with large aspect ratios can be easily realized. FIG. 4 shows the structure of an isolation region using conventional trench isolation. In this structure, a groove 104 is dug in an element isolation region between a P-type well 102 and an N-type well 103 on a substrate 101 by reactive ion etching (RIE), and impurity ions for channel stop are implanted into the groove. to form a channel stop region 105, and an oxide film 106 is formed inside the trench by thermal oxidation or vapor phase growth.
(After depositing a Si3 N4 film if desired) polysilicon is deposited by LPCVD with good step coverage, or a BPSG film is flowed in to fill the inside of the trench with an insulator 107, and then the substrate surface is etched back by RIE. After planarization is performed using the nitride film 108, an element isolation region is formed.

The dimensions of such a trench are, for example, a groove width of 1 μm and a groove depth of about 1 to several μm, and because of its high aspect ratio, it is useful for miniaturization of elements.
When further miniaturization is achieved, it is necessary to consider the structure of the trench itself. For example, when the trench width is 1 μm or less, it is considered difficult to fill with polysilicon by LPCVD or to fill with a BPSG film by flowing down.

[0006]

[Problems to be Solved by the Invention] The present invention provides a device isolation method for integrated circuits in which latch-up does not occur when trenches are used to isolate devices, and the groove width of the trenches is minute. The purpose is to

[0007]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention is directed to an integrated circuit element isolation method in which elements are isolated by grooves, in which grooves of minute width and deeper than the well depth are dug in element isolation regions. , provides a device isolation method for integrated circuits, which is characterized in that after oxidizing the inside of the trench, the upper part of the trench is closed with an interlayer insulating film.

[0008] Preferably, the width of the groove is 0.5 μm or less.

More preferably, the interlayer insulating film is made of a material that flows at a temperature that causes thermal oxidation.

More preferably, the upper part of the trench is closed with the interlayer insulating film at the same time as the thermal oxidation.

[0011]

[Operation] The present invention has been devised to miniaturize the element isolation region. In this way, when forming a micro-width trench in an element isolation region, after digging the trench and oxidizing the inside of the trench, the top of the trench is covered with an interlayer insulating film without filling the inside of the trench with an insulator such as polysilicon. It is blocked.

[0012] By setting the depth of the groove to be equal to or greater than the depth of the well, it is possible to substantially achieve latch-up freedom.

Further, when the groove width is 0.5 μm or less, the upper part of the groove can be effectively closed by the interlayer insulating film. The interlayer insulating film may be formed in two steps, in which an oxide film is formed on the inner wall of the trench and then closed, or in one step, in which an oxide film is formed on the inner wall of the trench and then closed. In a two-step thermal oxidation process, an oxide film is first formed in a relatively short period of time to prevent the interlayer insulating film from fluidizing, and then the interlayer insulating film is made to flow and the trench opening is covered with the interlayer insulating film. It is desirable to do so. Also, if it is done in one step,
The oxidation temperature, atmosphere, and interlayer insulating film are selected so that the time required to obtain the desired thermal oxidation film thickness and the time required to close the trench opening are equal to or longer, satisfying the above conditions. If such a selection is made, the flow of the oxide film and the interlayer insulating film can be performed at the same time, and only one process is required.

The extent to which the interlayer insulating film covers the opening of the trench is sufficient as long as the airtightness within the trench is maintained even during etching after the fluidization step (for example, etchback used to planarize the interlayer). Therefore, in order for the interlayer insulating film to cover the trench opening, it is necessary to increase the thickness of the interlayer insulating film depending on the size of the trench opening.

Thermal oxidation temperature is the temperature at which silicon is oxidized, and is, for example, within the range of 850 to 1100° C., and the time required for oxidation varies depending on the temperature, so a desired time is not particularly specified. Furthermore, examples of interlayer insulating films suitable for use in the present invention include BPSG films and PSG films. The temperature range for fluidizing these interlayer insulating films varies depending on each interlayer insulating film, but for example, if the interlayer insulating film contains 2.3% by weight or more of boron and phosphorus, 5.
In the case of a BPSG film containing 6% by weight or more, 850°C
The above allows efficient fluidization. The oxidation temperature, oxidation atmosphere, and fluidization temperature of the interlayer insulating film are selected depending on whether the oxidation is performed in two stages or in one stage as described above. Further, the temperature may be kept constant at a predetermined temperature under predetermined thermal oxidation conditions, or may be maintained according to a predetermined temperature program.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the integrated circuit element isolation method of the present invention will be described below.

A first method of covering the upper part of the trench with an interlayer insulating film in the method of the present invention will be explained with reference to FIG. FIG. 1 is a cross-sectional view of an element in main steps for explaining an embodiment of the present invention.

The manufacturing method in the first example will be explained in order. First, as shown in FIG. 1A, a P-type well 13 and N-type wells 15 and 17 in contact with it are formed in a substrate 11 made of ordinary single crystal silicon, and ions are implanted for threshold adjustment. After that, the main surface of the substrate 11 is coated with a thickness of 10 mm.
After forming a gate oxide film 19 with a thickness of about 0 Å by thermal oxidation, a gate material film 21 with a thickness of about 1500 to 3000 Å is deposited on the entire surface of the substrate 11 .

Next, referring to FIG. 1B, the gate material film 21 is patterned using a photoresist. A gate electrode layer 23 is formed.

Referring to FIG. 1C, an N-type dopant, for example, arsenic ions, is implanted using a mask having openings corresponding to the source/drain regions and also using the gate electrode layer 23 as a mask. 1× at energy 35KeV
Source/drain regions 27 and 29 are formed by ion implantation to a dose of 10<15> to 3*10<15>/cm<2>. Also, a P-type dopant, for example BF2, is added using a mask.
1 x 1015 to 3 x 10 at an implantation energy of 40 KeV
Boron ions are implanted to a dose of 15/cm2 to form a P+ layer 25 for contact with the P-type well.

Referring to FIG. 2(d), the source/drain regions 27 and 29 and the P+ well contact
After layer 25 is formed, e.g. Si(OC2H5)
An oxide film containing boron and phosphorus (B
A PSG film) 31 is deposited. The thickness of this oxide film is 7,000 to 15,000, depending on the impurity concentration in the oxide film.
It should be about Å.

Referring to FIG. 2E, a resist (not shown) is applied, and an opening of a predetermined width is formed in the resist at or near the well boundary using lithography technology.
Using this resist as a mask, the oxide film 31 and gate oxide film 19 are removed by reactive ion etching (RIE), and then the exposed well boundary region of the substrate 11 is removed by reactive ion etching to increase the depth. 2μm
Trenches 33 and 35 with a width of about 0.5 μm are formed.

Referring to FIG. 2(f), in order to form an oxide film 37 inside the trench, the temperature is increased to 90°C in a water vapor atmosphere.
An oxide film 37 is formed by leaving the trench at 0° C. for 2 to 6 minutes, and then processing is performed in a nitrogen atmosphere at the same temperature to close the upper part of the trench with the oxide film 31. In this case, the top of the trench is
The oxide film 31 around the trench opening flows due to the heat, and they come together over the trench opening to close it.

A second example of the element isolation method of the present invention will be explained below with reference to FIG. In the figure, (a) to (c) show cross-sectional views of the element in main steps. In this example, (
When the gate material film 21 is patterned after the step a), the gate material film 21 is left on or adjacent to the well boundary region. Here, this film is referred to as a step film and is designated by reference numerals 41 and 43.

In this way, the gate electrode layer 23 and the step film 4
As described above, an oxide film 31 such as a BPSG film is formed on the entire surface of the substrate on which 1 and 43 are formed ((a in FIG. 3).
)reference).

Referring to FIG. 3B, in the region corresponding to the well boundary, the sloped portions of the oxide film 31 formed on the step films 41 and 43 are removed by reactive ion etching. , followed by forming a trench in the substrate.

Referring to FIG. 3(c), in order to form an oxide film inside the trench, the temperature is 900° C. in a water vapor atmosphere.
The trench is left for 2 to 6 minutes to form an oxide film, and then processed in a nitrogen atmosphere at the same temperature to close the upper part of the trench with an oxide film 31. In this case, in the upper part of the trench, the oxide film 31 around the opening of the trench flows due to heat, and these pieces come together and close the trench opening.

In this second example, the step films 41, 43
is formed, and a step is created in the oxide film 31 thereon, and due to the step in the oxide film 31, the surface position of the oxide film above the step covers the oxide film below, sandwiching the trench hole. Then, the upper part of the trench is closed.

As described above, according to the present invention, after forming a trench and oxidizing the inside of the trench, the upper part of the trench is closed with an interlayer insulating film without filling the inside of the trench with an insulating material, so that the width of the trench can be made smaller than the conventional width. In addition, if the insulating film filled inside the trench contains impurities as in conventional methods, it is possible to take measures to prevent the adverse effects of impurities in the insulator on the substrate surrounding the trench, for example. There is no need to take measures such as providing a nitride film.

Although the embodiments of the present invention have been described using two examples, the present invention is not limited to the above embodiments, and various methods can be considered.

[0031]

[Effects of the Invention] As can be understood from the above explanation, in the present invention, when forming a micro-width trench in an element isolation region, the trench is dug, the inside of the trench is oxidized, and then the inside of the trench is made of polysilicon or the like. By closing the upper part of the groove with an interlayer insulating film without filling it with an insulator, there is no need to fill the inside of the groove with insulator, and there is no possibility of incomplete filling of the insulator.
Further, the step of filling the insulator can be omitted. Furthermore, since the groove is filled with air as an insulator, by maintaining sufficient insulation and making the groove depth greater than or equal to the well depth, latch-up free can be almost achieved.

Furthermore, when filling the inside of the groove with, for example, a BPSG film, a nitride film must be formed on the oxide film in order to prevent boron ions and phosphorus ions from diffusing. Another advantage of this method is that the nitride film can be omitted.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a device showing main steps (a) to (c) of a first embodiment of the integrated circuit device isolation method according to the present invention.

FIG. 2 is a cross-sectional view of a device showing main steps (d) to (f) showing a first embodiment of the integrated circuit device isolation method according to the present invention.

FIG. 3 is a cross-sectional view of a device showing main steps (a) to (c) showing a second embodiment of the integrated circuit device isolation method according to the present invention.

FIG. 4 is a cross-sectional view showing a conventional trench structure.

[Explanation of symbols] 11 Substrate 13 P-type well 15, 17 N-type well 19 Gate oxide film 21 Gate material film 23 Gate electrode layer 25 P+ layer 27, 2 for contact of P-type well
9 Source/drain region 31 Oxide film 33, 35 Trench 37, 39 Oxide film 41, 43 Step film

Claims (4)

[Claims] Claim 1: In an integrated circuit element isolation method in which elements are isolated by a groove, a groove with a minute width or more than the depth of a well is dug in an element isolation region, and after the inside of the groove is oxidized, the upper part of the groove is covered with an interlayer insulating film. A device separation method for integrated circuits characterized by occlusion. 2. The device isolation method for an integrated circuit according to claim 1, wherein the width of the groove is 0.5 μm or less. 3. The device isolation method for an integrated circuit according to claim 1, wherein the interlayer insulating film is made of a material that flows at a temperature that causes thermal oxidation. 4. A device isolation method for an integrated circuit according to claim 3, wherein the upper part of the trench is closed with the interlayer insulating film at the same time as the thermal oxidation.