JPH04280641A - Semiconductor device - Google Patents

Abstract

PURPOSE:To abate the noise in the title semiconductor device having high electron mobility transistor for amplyfying high-frequency signals. CONSTITUTION:Within the title semiconductor device having a field-effect transistor 1 wherein a channel is to be formed on a heterojunction surface, the regional layer 4 at least between a gate electrode 6 and a source electrode 7 out of the second semiconductor layers 3, 4 to be heterojunctioned on the opposite surface of the first semiconductor layer 5 where the gate electrode 6 and the source electrode 7 of the field effect transistor 1 are formed is formed of the semiconductor material in higher electron affinity than that in the other regional layer 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high electron mobility transistor for amplifying a high frequency signal.

[0002] With the recent spread of satellite communications, there is a demand for lower noise reception systems. There is a need for further reduction in noise in signal amplification elements used in the first stage of receiving antennas.

0003

[Prior Art] GaAs MESFETs are used as transistors for amplifying high-frequency signals, and high electron mobility transistors (HEMTs) utilize two-dimensional electron gas that accumulates at the heterojunction interface.
Further noise reduction has been achieved by using the Mobility Transistor (Mobility Transistor).

In HEMT, for example, as shown in FIG. 4, an i-GaAs layer b and an n-AlGaAs layer c are epitaxially grown on a semiconductor insulating GaAs substrate a.
- It is constructed by forming a gate electrode g in Schottky contact with the AlGaAs layer c, and a source electrode s and a drain electrode d in resistive contact on both sides thereof.

[0005] Then, the i-GaAs layer b and the n-AlGa
The two-dimensional electron gas generated at the interface of the As layer c is moved between the source electrode s and the drain electrode d, and the concentration of the two-dimensional electron gas is changed by the voltage applied to the gate electrode g to operate the FET.

[0006]

However, since two-dimensional electron gas moves with a certain degree of randomness while being scattered by lattice vibrations, etc., there is a problem in that noise is generated.

The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device that can reduce HEMT noise.

[0008]

[Means for Solving the Problems] The above problems are solved in a semiconductor device having a field effect transistor 1 in which a channel is formed on a heterojunction surface, as illustrated in FIG.
Of the second semiconductor layers 3 and 4 that are heterojunctioned to the opposite surface of the first semiconductor layer 5 forming the gate electrode 6 and source electrode 7 of the electrode effect transistor 1, at least the gate electrode 6 and the source electrode This is achieved by a semiconductor device characterized in that the region layer 4 between the regions 7 and 7 is formed of a semiconductor material having a higher electron affinity than the other region layers 3.

[0009]

[Function] According to the present invention, at least the gate electrode 6 of the second semiconductor layers 3 and 4 that is heterojunctioned to the opposite surface of the first semiconductor layer 5 that contacts the gate electrode 6 and the source electrode 7 The region layer 4 between the source electrode 7 and the source electrode 7 is formed of a semiconductor material having a higher electron affinity than the other region layers 3.

For this reason, the source electrode 7 and the drain electrode 8
When a voltage is applied between them, electrons at the interface between the first semiconductor layer 5 and the second semiconductor layers 3 and 4 flow along their bonding surfaces. The concentration of the two-dimensional electron gas under the gate electrode 6 is controlled by the voltage applied to the gate electrode 6.

In this case, the second semiconductor layer formed under the first semiconductor layer 5 has a region layer 4 having a high electron affinity on the source electrode 7 side with the edge of the gate electrode 6 as a boundary, In addition, since the region layer 3 with a small electron affinity is provided on the gate electrode 6 side, the concentration of two-dimensional electron gas in the region layer 4 with a large electron affinity is high, and the concentration of the two-dimensional electron gas is high at the junction surface of the region layers 3 and 4. A potential barrier is formed and a diffusion potential is generated.

Therefore, the region layer 4 with high electron affinity
When electrons flow from the small area layer 3 toward the small area layer 3, only those electrons having energy above a certain level exceeding the potential barrier are selected and reach the bottom of the gate electrode 6.

As a result, compared to a HEMT having a conventional structure, the disorder of the movement of the two-dimensional electron gas that reaches the bottom of the gate electrode 6 is reduced, and the noise of the device due to this is reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (a) Description of a first embodiment of the present invention FIG. 1 is a sectional view of an apparatus showing an embodiment of the present invention.

In FIG. 1, reference numeral 1 indicates semi-insulating GaAs.
In the HEMT formed on the substrate 2, i-GaA is used in the range from the gate region to the drain region on the GaAs substrate 2.
An s layer 3 is formed, and an i-InGaAs layer 4 is laminated in the range from the edge of the gate region to the source region, and silicon is doped on the i-GaAs layer 3 and the i-InGaAs layer 4. The n-AlGaAs layer 5 is formed such that the bonding surface between the n-AlGaAs layer 5 and the i-InGaAs layer 4 coincides with the bonding surface between the n-AlGaAs layer 5 and the i-GaAs layer 3.

A gate electrode 6 made of tungsten silicide (WSi) is in Schottky contact with the n-AlGaAs layer 5 in the gate region, while a gate electrode 6 made of tungsten silicide (WSi) is in Schottky contact with the n-AlGaAs layer 5 in the source and drain regions.
A source electrode 7 and a drain electrode 8 made of i/Au are in resistance contact.

Next, the operation of the above embodiment will be explained.

In the embodiments described above, n-AlGaA
s layer 5, i-InGaAs layer 4, and n-AlGaAs
The layer 5 and the i-GaAs layer 3 are in a heterojunction, and a two-dimensional electron gas is generated at their interface. When a voltage is applied between the source electrode 7 and the drain electrode 8, the electrons are released along their junction surface. It flows. The concentration of the two-dimensional electron gas under the gate electrode 6 is controlled by the voltage applied to the gate electrode 6.

In this case, under the n-AlGaAs layer 5, there is an i
-InGaAs layer 4 is formed, and i-GaAs layer 3 is formed on the gate electrode 6 and drain electrode 8 side,
The i-InGaAs layer 4 has a larger electron affinity than the i-GaAs layer 3 and has a higher concentration of two-dimensional electron gas.

For this reason, the i-InGaAs layer 4 and the i-G
A potential barrier is formed at the junction surface of the aAs layer 3, and a diffusion potential is generated.

Therefore, from the i-InGaAs layer 4
- When two-dimensional electrons flow toward the GaAs layer 3 , only electrons with energy above a certain level exceeding the potential barrier are selected, reach the gate electrode 6 , and flow to the drain electrode 8 .

As a result, the randomness of the movement of the two-dimensional electron gas that reaches the bottom of the gate electrode 6 is reduced, so that the noise of the device caused by this is reduced.

Next, the manufacturing process of the above-mentioned embodiment device will be briefly explained based on FIG. 2.

First, as shown in FIG. 2A, an i-GaAs layer 3 and an n-Al layer are formed on a semi-insulating GaAs substrate 2.
GaAs layers 5a are epitaxially grown in sequence. The thicknesses of these layers 3 and 5a are, for example, 5000 Å and 500 Å, respectively.
The thickness is approximately 00 Å.

Next, W is deposited on the n-AlGaAs layer 5a.
A Si film is laminated and patterned by photolithography to leave a band shape, which is used as the gate electrode 6.

Next, the gate electrode 6 and the n
- After covering the AlGaAs layer 5a with the SiO2 film 9, the n-AlGaAs layer 5a and the i-GaAs layer 3 exposed from the SiO2 film are removed by reactive ion etching or the like (FIG. 2(B)).

Then, G exposed on one side of the gate electrode 6
An i-InGaAs layer 4 is epitaxially grown on the aAs substrate 2, and an n-AlGaAs layer 5b is further grown (FIG. 2(C)). In this case, the film thickness is controlled so that the top surface of the i-InGaAs layer 4 and the top surface of the i-GaAs layer 3 are aligned.

Here, n-AlG on the i-GaAs layer 3
n-AlGa on the aAs layer 5a and the i-InGaAs layer 4
The As layer 5b is integrated to form the n-AlGaAs layer 5 shown in FIG.

After this, using the lift-off method, AuG
A source electrode 7 and a drain electrode 8 made of e/Ni/Au are formed at intervals on both sides of the gate electrode 6 (FIG. 2(D)).

The device of the first embodiment is thus completed.

(b) Description of other embodiments of the present invention In the embodiments described above, the i-InGaAs layer 4 was formed so as to be bonded to the GaAs substrate 2, but as shown in FIG. A recess may be formed in the GaAs layer 3a on one side, and the i-InGaAs layer 4a and the n-AlGaAs layer 5 may be laminated therein.

Further, in the above manufacturing process (FIG. 2), the n-AlGaAs layer 5a and i
- After etching the GaAs layer 3, i-In is added here.
A GaAs layer 4 and an n-AlGaAs layer 5b are grown.

However, when forming an InGaAs layer, for example, 1×10 15 /cm 2 is required, regardless of film growth.
The i-InGaAs layer 4 can also be formed by implanting In ions into the i-GaAs layer 3 at the above dose. According to this, the i-InGaAs layer 4 and the G
There is no need to control the alignment of the upper surface of the aAs layer 3.

Furthermore, in the above embodiment, the source electrode 7
Although the i-InGaAs layer 4 is formed in the region extending from to the edge of the gate electrode 6, the semiconductor material thereof is not limited to this, and may have a higher electron affinity than the semiconductor layer (3) below the gate electrode 6. It is fine as long as it is large.

[0035] Note that the region formed of a semiconductor material having a large electron affinity need only exist at least in the region between the gate electrode and the source electrode.

[0036]

Effects of the Invention As described above, according to the present invention, the second semiconductor layer which is heterojunctioned to the surface opposite to the first semiconductor layer which contacts the gate electrode and the source electrode, has at least one contact with the gate electrode. The region layer between the source electrodes is formed of a semiconductor material having a higher electron affinity than other region layers.

Therefore, the second semiconductor layer formed under the first semiconductor layer has a region layer having a large electron affinity on the source electrode side with the edge of the gate electrode as a boundary, and Because it has a region layer with low electron affinity on the side, the concentration of two-dimensional electron gas in the region layer with high electron affinity is high, and a potential barrier is formed at the junction surface of these region layers, generating a diffusion potential. do.

[0038] Therefore, when electrons flow from a region layer with a large electron affinity to a region layer with a small electron affinity, only electrons with energy above a certain level exceeding the potential barrier are selected and reach the bottom of the gate electrode. ,
The randomness of the movement of the two-dimensional electron gas is reduced, and it becomes possible to reduce the noise of the device caused by this.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an apparatus according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the manufacturing process of the device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a device according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing an example of a conventional device.

[Explanation of symbols]

1 HEMT 2 GaAs substrate 3 i-GaAs layer 4 i-InGaAs layer 5 n-AlGaAs layer 6 Gate electrode 7 Source electrode 8 Drain electrode

Claims (1)

[Claims] 1. A semiconductor device having a field effect transistor (1) in which a channel is formed on a heterojunction surface, comprising:
Of the second semiconductor layers (3, 4) that are heterojunctioned to the opposite surface of the first semiconductor layer (5) forming the gate electrode (6) and source electrode (7) of the electrode effect transistor (1) , characterized in that at least the region layer (4) between the gate electrode (6) and the source electrode (7) is formed of a semiconductor material having a higher electron affinity than other region layers (3). Semiconductor equipment.