JPH04280510A - Control method for rds receiver - Google Patents

Abstract

PURPOSE:To always obtain an excellent reception state by extracting an AF data which can obtain an electric field strength more than a setting level in an AF data list stored in a memory when the reception state is deteriorated so as to switch a reception frequency. CONSTITUTION:Radio data information relating to a program content of a broadcast station being received is stored in a memory 15 to form an AF data list of the same network station as that of the broadcast station currently being received. The channel selection is implemented by controlling a reception frequency data deciding a frequency division ratio of a programmable frequency divider of a PLL circuit 2a based on a channel selection command from an operation section 1. On the other hand, a level detection circuit 19 detects a reception signal level based on a signal level of an IF amplifier 3. A station detection circuit 20 outputs a station detection signal when an IF signal level is a set level or over and a detection output of a detector 4 is within a prescribed level range. Each output signal of the circuits 19, 20 is fed to a controller 14. Thus, the reception is changed quickly.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to a method of controlling a radio data system receiver (hereinafter referred to as an RDS receiver).

0002

[Background technology] When a broadcast station broadcasts, broadcast-related information such as information related to the program content is transmitted as data by multiplex modulation, and the receiving side demodulates the data and uses the desired information There is a radio data system (RDS) that allows radio listeners to select program content and provide that service to radio listeners.

[0003] In this radio data system, F
The subcarrier is 57KHz, which is the third harmonic of the 19KHz stereo pilot signal outside the frequency band of the M modulation wave, and this subcarrier is filtered and biphase coded to broadcast program content, etc. A radio data signal is amplitude-modulated using a data signal indicating information related to the radio signal, and this amplitude-modulated subcarrier is frequency-modulated to a main carrier and then broadcast.

As is clear from FIG. 6 showing its baseband coding structure, a radio data signal has 104
A group of bits is repeatedly multiplexed and transmitted. 1
Each group consists of four blocks of 26 bits each, and each block consists of a 16 bit information word and a 10 bit check word. In Figure 7, block 1 includes program recognition (PI) representing the network.
) code, and block 2 contains the traffic program recognition (TP) code.
Block 3 code and Traffic Announcement Recognition (TA) code
Block 4 contains frequency (AF) data of a group of network stations broadcasting the same program, and Block 4 contains program service name information (PS) data such as broadcasting station name and network name. are placed respectively. Also, each group has 4 groups depending on its content.
Types are classified into 16 types (0 to 15) by bit, and two versions, A and B, are defined for each type (0 to 15), and these recognition codes are stored in block 2. It is located. In addition, network station A
F data is transmitted only in type 0A group, and PS data is transmitted in type 0A and 0B groups.

By the way, in the case of a vehicle-mounted receiver, the reception condition of the broadcast waves being received may deteriorate as the vehicle travels. However, when one RDS broadcast is received, the AF data of a group of network stations broadcasting the same program can be obtained as described above.
It is desirable to be able to listen to broadcast programs on the same network in good reception conditions by using the same network. Therefore, the AF data of a group of network stations broadcasting the same program is stored in memory in advance, and the field strength of the RDS broadcast wave being received drops below a set level for a predetermined period of time. At that time, the AF data of one of the network stations broadcasting the same program is selectively read out from the memory, and the AF data is actually received at the frequency indicated by the AF data, and the AF data is received at the frequency indicated by the AF data, and the AF data is received at the frequency indicated by the AF data. JP-A-64-55916 discloses a control method that immediately shifts to reception of the RDS broadcast wave when an RDS broadcast wave with an electric field strength of 1 is received, and is already known.

However, in this control method, the received R is determined by the AF data read from the memory.
If the received signal level of the DS broadcast wave is simply below the set level, the reception will immediately shift to that RDS broadcast wave, and the AF data will be read from the memory and used for other RDs.
Since the received signal level of the S broadcast wave is not detected, the reception does not necessarily shift to the reception of the RDS broadcast wave, which provides the best reception condition.

[0007]

[Object of the Invention] Therefore, the object of the present invention is to
An object of the present invention is to provide a control method for an RDS receiver that can shift to reception of RDS broadcast waves that provide the best reception condition when the reception condition of the broadcast waves deteriorates.

[0008]

[Structure of the Invention] A control method for an RDS receiver according to the present invention is a method for controlling an RDS receiver equipped with a memory storing frequency data of a group of stations on the same network. The first step is to generate a frequency check signal in accordance with the reception status, and in response to the frequency check signal, new frequency data of one of the network stations to which the broadcasting station of the broadcast wave currently being received belongs is generated. A second step of selectively reading out from the memory and switching the reception frequency to the frequency indicated by the read frequency data 1, and whether or not the reception signal level at the reception frequency switched in the second step is higher than the set level. After the determination, the third step returns to the second step until all frequency data are read from the memory, and in the third step, it is determined that the received signal level is higher than the set level. and a fourth step of selecting one frequency data with the highest received signal level from all the frequency data and switching the receiving frequency to the frequency indicated by that one frequency data. It is a feature.

[0009]

Effect of the Invention In the RDS receiver control method of the present invention, when the reception condition of the RDS broadcast wave currently being received deteriorates, an electric field higher than a set level is selected from the frequency data list stored in the memory. Only the AF data from which the strength can be obtained is first extracted, and from the extracted AF data, one AF data with the highest received signal level is selected, and that one AF data The receiving frequency is switched to the frequency indicated by . Therefore, when the reception condition of RDS broadcast waves deteriorates, the RDS of the frequency that provides the best reception condition with the field strength above the set level is selected from the AF data list.
You can quickly shift to receiving broadcast waves.

0010

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the RDS receiver to which the control method of the present invention shown in FIG.
A desired station of the M multiplex broadcast waves is selected by the front end 2, converted to an intermediate frequency (IF), and then supplied to the FM detector 4 via the IF amplifier 3. The front end 2 obtains the local oscillator signal to the mixer 2b using a PLL synthesizer method using a PLL circuit 2a including a programmable frequency divider, and the frequency division ratio of the programmable frequency divider is determined by the controller 14, which will be described later. The configuration is such that the channel selection operation is performed by being controlled by. The detection output of the FM detector 4 is supplied to an MPX (multiplex) demodulation circuit 5,
In the case of stereo broadcasting, the audio signals are separated into L (left) and R (right) channels.

[0011] Furthermore, by passing the detection output of the FM detector 4 through the filter 6, a 57 KHz subcarrier amplitude-modulated by the bi-phase coded data signal, that is, a radio data signal is extracted. PLL circuit 7
It is demodulated by For example, as the PLL circuit 7,
The circuit disclosed in Japanese Patent No. 3-87052 is used. The demodulated output from this PLL circuit 7 is a digital (D)P
The signal is supplied to an LL circuit 8 and a decoder 9. In the D-PLL circuit 8, a clock for data demodulation is generated based on the demodulated output of the PLL circuit 7. The generated clock is supplied to the gate circuit 10. The lock detection circuit 11 is disclosed in, for example, Japanese Patent Laid-Open No. 63-87039 and Japanese Patent Laid-Open No. 63-87.
This circuit is disclosed in Publication No. 040, and detects that the D-PLL circuit 8 is locked and generates a high-level lock detection signal, and detects the unlocked state of the D-PLL circuit 8 and generates a low-level lock detection signal. Generates an unlock detection signal. The output signal of the lock detection circuit 11 is supplied to the gate circuit 10 to
- When the PLL circuit 8 is unlocked, the gate circuit 10 is controlled to be in an open state. The output signal of the lock detection circuit 11 is also supplied to the controller 14, and is also supplied as a lock range switching signal for switching and controlling the lock ranges of the PLL circuit 7 and the D-PLL circuit 8. When the lock state of the D-PLL circuit 8 is detected, by narrowing the lock range of the PLL circuit 7 and the D-PLL circuit 8, the clock for data demodulation is always kept as a stable clock without being affected by external influences. We are trying to supply it. In the decoder 9, the biphase coded data signal which is the demodulated output of the PLL circuit 7 is decoded in synchronization with the clock generated by the D-PLL circuit 8.

As shown in FIG. 6, the output data of the decoder 9 is in groups of 104 bits each consisting of 4 blocks of 26 bits. The signal is supplied to the detection circuit 12. In the group, block synchronization & error detection circuit 12, one
1 assigned to each 0-bit checkword
Group and block synchronization is performed based on the 0-bit offset word, and error detection of the 16-bit information word is performed based on the check word. The error-detected data is then error-corrected in the next-stage error correction circuit 13 and then supplied to the controller 14.

[0013] The controller 14 is constituted by a microcomputer, and is configured to collect code information of each block in radio data that is sequentially input in groups, that is, information related to the program content of the broadcasting station currently being received. radio data information (
The above-mentioned PI code, AF data, PS data, etc.) are taken in and stored in the memory 15. By this operation, the AF data list (
AF data f(1), f(2)...f(n)) are formed. Also, based on a channel selection command from the operation unit 16, a reception frequency data is used to determine the frequency division ratio of a programmable frequency divider (not shown) of a PLL circuit 2a that constitutes a part of the front end 2.
The channel selection operation is performed by controlling the data value. The received frequency data value is, for example, a count value of a counter.

On the other hand, the level detection circuit 19 is connected to the IF amplifier 3.
The received signal level (field strength) is detected based on the IF signal level at . In addition, the station detection circuit 20 detects that the IF signal level in the IF amplifier 3 is equal to or higher than the set level and the FM
When the detection output of the so-called S-curve characteristic in the detector 4 is within a predetermined level range, a station detection signal is output. Each output signal of the level detection circuit 19 and the station detection circuit 20 is supplied to the controller 14.

Note that the memory 15 stores received frequency data, P
It consists of a non-volatile RAM into which data such as I-codes and AF data are written, and a ROM into which programs and data are written in advance. Next, the operation of the processor of the controller 14 is shown in FIG.
This will be explained according to the flowchart shown in ~FIG. 4.

When the processor detects that the same program follow button (not shown) on the operation unit 16 has been operated, it enters the same program follow mode. In this same program following mode, the lock detection routine and electric field strength detection routine shown in FIGS. 2 and 3 are executed at predetermined timings. In the lock detection routine, the processor first resets the measured value T of the timer and the counted value C of the counter to initial values (for example, both are 0) (step S1). This timer and counter are formed by executing steps such as steps S1 to S4. The measured value T of the timer is increased by a unit time T1 (step S2), and it is determined whether a lock detection signal is supplied from the lock detection circuit 10 (step S3). If the lock detection signal is not generated but the unlock detection signal is generated, it is assumed that the D-PLL circuit 8 is in the unlocked state due to the generation of multi-pulses, and 1 is added to the count value C of the counter. (Step S4), the timer measurement value T overflows.
It is determined whether or not it has been performed (step S5). That is, it is determined whether the measured value T of the timer has reached the set time TMAX. On the other hand, the lock detection signal is
If it is supplied from the source, step S5 is executed immediately. If T<TMAX, the process moves to step S2. Although not shown, if T<TMAX, step S2 is executed after determining whether the unit time T1 has passed.

If T≧TMAX in step S5, the received signal level Vs outputted from the level detection circuit 19 is taken in (step S6), and the reference value Cr corresponding to the received signal level Vs is searched from the data map. settings (step S7). A data map for searching the reference value Cr is stored in the memory 15 in advance. Next, it is determined whether the count value C of the counter is greater than the reference value Cr (step S8). C>Cr
If so, the flag F1 is set to 1 to indicate that the D-PLL circuit 8 is in the unlocked state frequently and the influence of multi-pulses is large (step S9), and the AF check routine is executed (step S10). ). C≦Cr
If so, since the influence of the multi-pulse is relatively small, the flag F1 is reset to 0 (step S11), and this routine ends. Note that setting the flag F1 to 1 results in generation of the first frequency check signal.

On the other hand, in the electric field strength detection routine, the processor takes in the received signal level Vs output from the level detection circuit 19 (step S21), and determines whether the received signal level Vs is smaller than the set level Vr. (Step S22). If Vs < Vr, it is determined whether the low level (low electric field) reception state has continued for a predetermined time t1 or more (step S23). Vs
If the low level reception state of <Vr continues for a predetermined time t1 or more, flag F2 is set to 1 to indicate that the currently received broadcast wave is in the low level reception state (step S24), and the AF check routine is executed. (Step S25). If Vs≧Vr, it is not a low level reception state, so the flag F2 is reset to 0 (step S
26), end this routine.

In the AF check routine, as shown in FIG. 4, it is first determined whether the flag F1 is equal to 1 (step S31). If F1 = 1, D-P
Since the frequency of the unlocked state of the LL circuit 8 is high, the setting level V1 is set to a predetermined level VA (step S32).
). If F1 = 0, it is determined whether the flag F2 is equal to 1 (step S33). If F2 = 1,
Since the currently received broadcast wave is in a low level reception state, the set level V1 is set to the predetermined level VB (step S34).
, F2 = 0, this routine ends. Note that the predetermined level VA is higher than the predetermined level VB. Also,
Setting flag F2 to 1 results in generation of the second frequency check signal.

After executing step S32 or S34, the variable m is made equal to 1 (step S35), and the variable u is made equal to 0 (step S36). Then, 1 AF data f(m) is read out from each AF data f(1), f(2), ... f(n) of the AF data list written in the memory 15, and the PLL circuit 2a is set to the frequency divider (step S37). As a result, the receiving frequency changes to the broadcasting frequency of the currently received broadcasting station and another broadcasting station on the same network. Next, A of 1 in the AF data list
The reception signal level Vs at the new reception frequency based on the F data f(m) is taken in (step S38), and it is determined whether the reception signal level Vs is greater than the set level V1 (step S39). Although not shown, step S38 is executed after a period of time has elapsed from the setting of AF data to the stabilization of the receiving frequency by executing step S37. If Vs≦V1, the process moves to step S43, which will be described later. Vs > V1
If so, the PI code representing the network of the receiving broadcasting station of the AF data f(m) is imported (step S40).
, add 1 to variable u (step S41), set AF data f(m) to check AF data cf(u), set received signal level Vs to received signal level Vs(u), and import Memory 1 with PI code as PI(u)
5 (step S42). Next, it is determined whether the variable m has reached the number n of AF data in the AF data list (step S43). If m<n, 1 is added to the variable m (step S44), and the process moves to step S37. By repeating this operation, from each AF data f(1), f(2)...f(n) in the AF data list, all A
F data, that is, check AF data is written into the memory 15. When m=n, all AF data f(
1) , f(2) ... Step S for f(n)
Since the received signal level has been checked in step S39, the process advances to step S45. The value of variable u at this time is Vs
It shows the number of AF data for which a received signal level of >V1 was obtained.

In step S45, it is determined whether the variable u is equal to 0 or not. If u=0, there is no other broadcasting station that is broadcasting the same program as the currently received broadcasting station and from which a received signal level of Vs > V1 can be obtained, so the process moves to step S58, which will be described later. If u≠0, the maximum level value VMAX is made equal to the initial value (for example, 0) (step S46), and the variable w is made equal to 1 (step S4).
7), the currently received broadcast station (same program tracking mode) from the memory 15.
The program reads out the PI code of the broadcasting station (which was being received immediately before the broadcast station) (step S48), and reads out the PI code PI(w) from the memory 15 (step S49). and,
It is determined whether the PI code of the currently received broadcasting station and the PI code PI(w) match (step S50). P.I.
If the codes do not match, the process moves to step S55 described later, and if the PI codes match, the received signal level Vs(w) is read from the memory 15 (step S51),
It is determined whether the received signal level Vs(w) is greater than the maximum level value VMAX (step S52). Vs
If (w)≦VMAX, the process moves to step S55, and if Vs(w)>VMAX, the level maximum value VM
The received signal level Vs(w) is set to AX (step S53), and the variable w is set to the selection number x (step S5).
4). After executing step S54, it is determined whether the variable w has reached the variable u (step S55). If w<u, 1 is added to the variable w (step S56), and step S
Return to 49. If w=u, it is determined whether the maximum level value VMAX is equal to the initial value (step S57). If the maximum level value VMAX is equal to the initial value, the PI code PI(w) that matches the PI code of the currently received broadcasting station
The same program following mode was not detected.
In order to return to reception of the currently received broadcast wave that was being received immediately before the mode was turned on, read the received frequency data in the memory 15 and press
Set in the frequency divider of the LL circuit 2a (step S58),
This routine ends in order to shift from the same program following mode to the normal reception mode. If the maximum level value VMAX is not equal to the initial value, check AF data cf that obtains the maximum level value VMAX as the received signal level.
(x) is read from the memory 15 and set in the frequency divider of the PLL circuit 2a (step S59), the received frequency data in the memory 15 is updated to check AF data cf(x) (step S60), End this routine. Therefore, the broadcast wave is received at the frequency determined by the check AF data cf(x). In other words, the broadcast wave with the highest electric field strength among the broadcast stations broadcasting the same program as the currently received broadcast wave received immediately before entering the same program tracking mode is received, and the broadcast wave of that frequency is selected. becomes the new currently received broadcasting station, and the same program tracking mode ends.

[0022] In addition, during the period when the same program following mode is entered and the reception frequency changes to a frequency in the AF data list other than the frequency of the currently received broadcasting station, a mute circuit (not shown) operates to mute the audio signal. The output is cut off and the same program following mode is set.
When the mode is finished, the mute state is canceled. Further, in the above-described embodiment, check AF data that provides a received signal level of Vs > V1 is written in the memory 15, but in step S39, Vs > V1 is determined.
If V1 is determined, the current receiving broadcasting station and PI code
If the PI codes match, the received signal level Vs reaches the maximum level VMAX.
Check AF data to obtain the AF data with the highest electric field strength among the broadcast stations broadcasting the same program as the currently received broadcast wave. It is also possible not to write data to the memory 15.

Furthermore, if it is known in advance that the PI codes of the broadcasting stations corresponding to each AF data in the AF data list of the same network stations stored in the memory 15 are the same; For example, it is not necessary to determine whether the PI code of the currently received broadcasting station matches the PI code PI(w) in step S50. In the embodiment of the present invention described above, the frequency data of the same network station group is stored in the memory by obtaining AF data from the RDS broadcast waves being received. Frequency data of the same network station group for each station may be stored in memory.

Furthermore, in the above embodiment, the AF data that provides a good reception condition is selected according to the received signal level, but the invention is not limited to this, and it is also possible to detect the noise level as well as the received signal level. AF data that provides a good reception condition may be selected depending on the received signal level and noise level.

[0025]

As described above, in the RDS receiver control method of the present invention, when the reception condition of the currently received RDS broadcast wave deteriorates, the AF data list stored in the memory is selected from a set level or higher. AF day where electric field strength of
First, only the AF data is extracted, and the 1st AF data with the highest received signal level is selected, and the receiving frequency is switched to the frequency indicated by the 1st AF data.
It is possible to quickly shift to reception of RDS broadcast waves at a frequency at which the best reception condition can be obtained with an electric field strength equal to or higher than a set level.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an RDS receiver to which a control method of the present invention is applied.

FIG. 2 is a flow diagram showing a lock detection routine.

FIG. 3 is a flow diagram showing an electric field strength detection routine.

FIG. 4 is a flow diagram showing an AF check routine.

FIG. 5 is a flow diagram showing a continuation of the AF check routine of FIG. 4;

FIG. 6 is a diagram showing a baseband coding structure of a radio data signal.

FIG. 7 is a diagram showing the format of a type 0A group.

[Explanation of symbols of main parts]

1 Antenna 2 Front end 4 FM detector 5 Multiplex demodulation circuit 8 Digital PLL circuit 9 Decoder 14 Controller

Claims (3)

[Claims] Claim 1: A method for controlling an RDS receiver equipped with a memory storing frequency data of a group of stations on the same network, the method comprising: generating a frequency check signal according to the reception state during reception of broadcast waves; The first step is to selectively read frequency data of a new one of the network station group to which the broadcasting station of the broadcast wave belongs from the memory according to the frequency check signal, and a second step of switching the reception frequency to the frequency indicated by the frequency data;
Determine whether the received signal level at the received frequency switched in the process is higher than the set level, and after making the determination,
A third step returns to the second step until all frequency data are read from the memory, and all frequency data whose received signal level is determined to be higher than the set level in the third step is and a fourth step of selecting one frequency data with the highest received signal level from the data and switching the receiving frequency to the frequency indicated by the one frequency data. control method. 2. In the first step, a first frequency check signal is generated according to the unlocked state of a digital PLL circuit that generates a clock for demodulating the radio data signal extracted from the FM detection output, and the first frequency check signal is A second frequency check signal is generated in response to a decrease in a received signal level of a broadcast wave, and the set level is different when the first frequency check signal is generated and when the second frequency check signal is generated. The method of controlling an RDS receiver according to claim 1. 3. The method of controlling an RDS receiver according to claim 1, wherein the setting level is set higher when the first frequency check signal is generated than when the second frequency check signal is generated.