JPH04278951A - Mask for producing semiconductor device and production of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the mask for producing semiconductor devices which can simultaneously and easily resolve patterns with high accuracy on respective regions if there is a difference in height between a memory cell region of a DRAM, etc., and a peripheral circuit region and the semiconductor device. CONSTITUTION:This mask for producing the semiconductor devices is constituted by having a light transparent mask substrate 1 formed with recessed parts 2 and projecting parts 4 on one surface to be a main surface and light shielding film patterns 5 formed on the recessed parts 2 and projecting parts 4 on the main surface of the substrate 1, forming the recessed parts 2 on the main surface of the mask substrate 1 in the regions corresponding to the high regions of the substrate surface to be exposed and forming the projecting parts 4 on the main surface of the mask substrate 1 in the regions corresponding to the low regions of the substrate surface to be exposed. This process is so constituted as to execute projection exposing by using the above-mentioned mask and disposing the main surface of the mask and the semiconductor substrate surface having the rugged parts so as to face each other.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a mask for manufacturing a semiconductor device and a method for manufacturing a semiconductor device, particularly for pattern formation in cases where there is a difference in height between a memory cell area and a peripheral circuit area, such as in a DRAM, at the same time, easily and easily. The present invention relates to a mask for manufacturing semiconductor devices that can be performed with high precision, and a method for manufacturing semiconductor devices using the mask.

As semiconductor ICs become more highly integrated, the width of internal wiring constituting circuits has become extremely narrow, and improving the precision of wiring pattern formation is essential to increasing the reliability and manufacturing yield of the ICs. extremely important, especially DRAM
In semiconductor devices such as those in which the memory cell region and the peripheral circuit region are different in height, there is a strong demand for a manufacturing method that improves the pattern formation precision of both the high and low regions that are formed at the same time.

0003

2. Description of the Related Art FIG. 3 is a schematic cross-sectional view showing the main parts of a DRAM. In the figure, 51 is a p-type silicon (Si) substrate,
52 is a field oxide film, 53 is a gate oxide film, 54A
, 54B, 54C, and 54D are first, second, third, and fourth word lines formed of poly-Si, metal silicide, etc., 55 is an n+ type source region of a transfer transistor for writing and reading data, 56A, 56B is an n+ type drain region of the first and second transfer transistors, 57 is a first interlayer insulating film, 58 is a bit line formed of poly-Si, metal silicide, etc., 59 is a second interlayer insulating film, 60A , 60B are fin-shaped first and second charge storage electrodes made of poly-Si or the like, 61 is a dielectric film, 62 is a counter electrode made of poly-Si or the like,
63 is the third interlayer insulating film, 64A, 64B, 64C
, 64D, 64E, 64F are aluminum (A
l) Wiring pattern, 65 is a memory cell area, and 66 is a peripheral circuit area.

As DRAMs become more highly integrated and their cell areas are reduced, it becomes difficult to ensure sufficient storage capacity. Therefore, as shown in FIG. 3, the memory cell is made into a stack type, and the charge storage electrodes 60A,
If 0B or the like is formed into a fin shape, the storage capacity can be significantly increased.

[0005]

[Problems to be Solved by the Invention] However, even if this fin structure is used, if the cell area is further reduced,
The number of fins has to be increased, and as a result, the heights of the charge storage electrodes 60A, 60B, etc. become larger. And these charge storage electrodes 60A, 60B
etc. are formed only in the memory cell area 65, so the height difference (h) between the memory cell area 65 and the peripheral circuit area 66 where logic etc. are formed becomes extremely large, and the Al wiring arranged in each area becomes extremely large. Patterns 64A to 64F,
And in the projection exposure process when forming an Al wiring pattern (not shown) arranged across those areas,
The above height difference (h) substantially reduces the depth of focus of the exposure device, making it difficult to resolve high and low parts at the same time, especially patterns such as the above Al wiring patterns 64A to 64F. In highly integrated DRAMs and the like where the width is reduced, fatal defects such as wire breaks are likely to occur.

[0006] Therefore, the present invention aims to provide a semiconductor substrate having a high region and a low region. Also, a mask for manufacturing semiconductor devices that can simultaneously resolve patterns with high precision, and a mask that can be used to resolve high and low regions of a semiconductor substrate and patterns disposed across these regions. The object of the present invention is to provide a method for manufacturing a semiconductor device that can be formed with high precision.

[0007]

[Means for Solving the Problem] The above problem is to provide a light-transmitting mask substrate in which concave portions and convex portions are formed on one main surface, and a light-transmitting mask substrate having concave portions and convex portions formed on the main surface of the mask substrate. a light-shielding film pattern, the concave portion of the main surface of the mask substrate is formed in a region corresponding to a high region of the surface of the substrate to be exposed, and the convex portion of the main surface of the mask substrate is formed in a region corresponding to a high region of the surface of the substrate to be exposed. A resist film formed on a thin film for patterning a thin film formed on the entire surface of a semiconductor substrate having a high region and a low region. When performing projection exposure of a pattern through a mask, a first region of the main surface of the mask substrate corresponding to a high region of the semiconductor substrate is formed in a concave shape, and a first region of the main surface of the mask substrate corresponding to a low region of the semiconductor substrate is formed into a concave shape. A semiconductor device according to the present invention, in which projection exposure is performed by using the mask in which the second region of the surface is formed in a convex shape, and arranging the main surface of the mask and the surface of the semiconductor substrate having the concave and convex portions to face each other. The problem is solved by the manufacturing method.

[0008]

[Operation] Normally, in a projection exposure apparatus used in manufacturing semiconductor devices, light passes through a mask, passes through a reduction lens, and is imaged onto a semiconductor substrate. At this time, the distances between the mask (principal surface having a pattern) and the lens, and between the lens and the semiconductor substrate (surface to be exposed) are set so that the lenses are in focus. Therefore, if the distance between the mask and the lens is shifted, the imaging plane will also shift, and the optimal distance between the lens and the semiconductor substrate will also change.

At this time, if the distance between the mask and the lens is increased, the optimal distance between the lens and the semiconductor substrate will be shortened, and if the distance between the mask and the lens is decreased, the optimal distance between the lens and the semiconductor substrate will be decreased. and the relationship is proportional with a negative proportionality coefficient.

As is clear from the above, the problems with the prior art are, for example, in the DRAM manufacturing process.
The cause is that the distance between the peripheral circuit area surface and the lens is not the same as the distance between the memory cell area surface and the lens, and exposure was performed with the distance between the lens and the mask constant.

Therefore, in the mask according to the present invention, the distance between the lens and the mask region for the memory cell region on the main surface of the mask and the distance between the lens and the memory cell region surface forming a convex portion on the semiconductor substrate surface are commensurate with the distance between the lens and the semiconductor substrate surface. In order to simultaneously secure a distance between the peripheral circuit area surface in the concave portion of the substrate surface and the lens and the mask area for the peripheral circuit area on the mask main surface, the semiconductor layer is placed on the main surface of the mask in advance. Concave areas and convex areas are formed in correspondence with convex areas and concave areas on the substrate surface, and a light shielding film pattern is formed on the main surface of the mask. Therefore, by one exposure, it is possible to accurately form thin film patterns in both the memory cell region and the peripheral circuit region, which have different heights.

[0012]The difference in height between the concave and convex regions formed on the mask surface is the same as the difference in height between the convex and concave regions formed on the semiconductor substrate in the case of a same-magnification projection. 1
times, 5 times for 1/5 reduction projection, and 10 times for 1/10 reduction projection.

[0013]

EXAMPLES The present invention will be specifically explained below with reference to illustrated examples. 1A to 1C are cross-sectional views of a manufacturing process of an embodiment of a mask according to the present invention, and FIG. 2 is a cross-sectional view of an exposure process of an embodiment of a method of manufacturing a semiconductor device according to the present invention. . Identical objects are indicated by the same reference numerals throughout the figures.

Refer to FIG. 1(a), for example, a DR according to the present invention used for 1/5 reduction projection exposure.
When forming a mask for AM production, normal coating,
After an exposure and development process, a film with a thickness of 5 μm is formed on the peripheral circuit region mask region 4 corresponding to the peripheral circuit region of the semiconductor substrate on the main surface 1S of the light-transmissive quartz substrate 1, for example.
A resist pattern 3 of about m is formed, and then heated at 200°C.
A certain amount of heat treatment is performed to form a tapered portion 3T at the end of the resist pattern 3.

Referring to FIG. 1(b), carbon tetrafluoride (CF4), for example, is added to the etching gas.
The entire principal surface 1S of the quartz substrate is etched until the resist pattern 3 is completely removed by a reactive ion etching means using a quartz substrate. When this etching is completed, on the main surface 1S side of the quartz substrate 1, a protrusion-shaped peripheral circuit region mask region 4 having a width corresponding to the width of the resist pattern 3 is formed. A depth of about 5 μm (d) in the area where it did not exist
A recessed memory cell region mask region 2 is formed. Note that the interface between the memory cell region mask region 2 and the peripheral circuit region mask region 4 is formed by the resist pattern 3.
A gentle taper part 4T corresponding to the tapered part 3T at the end
It is formed with

Referring to FIG. 1(c), next, the concave-shaped mask area 2 for the memory cell area and the convex-shaped mask area 2 for the peripheral circuit area are formed on the main surface 1S of the quartz substrate 1 by sputtering or the like as usual. Mask area 4
For example, about 1000 Å thick chromium (
Cr) film (light shielding film) 5 is formed, and then this C film is formed as usual.
A resist film for electron beam exposure (not shown) is formed on the r film 5, and after performing pattern drawing exposure with an electron beam, development is performed to form a resist pattern (not shown), and then this resist pattern is used as a mask, for example. C by reactive ion etching treatment using chlorine gas
The R film 5 is selectively etched, and then the resist film is removed to form a DRAM on the memory cell region mask region 2 having the concave shape and the peripheral circuit region mask region 4 having the convex shape on the main surface 1S of the quartz substrate 1. Cr corresponding to the wiring pattern of
Film patterns 5A to 5M are formed.

The projection exposure mask for forming a wiring pattern of, for example, a DRAM according to the present invention thus formed is formed in a convex shape on a semiconductor substrate, as shown in FIG. 1(c). A memory cell region mask region corresponding to the memory cell region is formed in a concave shape, a peripheral circuit region mask region corresponding to the peripheral circuit region formed in a concave shape on the semiconductor substrate is formed in a convex shape, A Cr film pattern 5 corresponding to the wiring pattern of the DRAM is formed on the main surface of each of the concave-shaped memory cell region mask region 2 and the convex-shaped peripheral circuit region mask region 4.

In projection exposure in the manufacturing process of semiconductor devices, reduction projection exposure is usually performed at a reduction rate of 1/5 or 1/10, so that the heights of the memory cell area and peripheral circuit area of the semiconductor substrate are reduced. If the difference is 1 μm,
The difference in height between the mask area 2 for the memory cell area and the mask area 4 for the peripheral circuit area in the mask is about 5 μm when reduced by 1/5 and 10 μm when reduced by 1/10.
Formed to a certain degree.

Furthermore, in the case of the mask according to the present invention, although the surface on which the light-shielding film is formed is not planar, the size of the pattern is small because the exposure of the pattern is performed by electron beam lithography and is used for the reduction projection. However, since the size of the pattern is 5 to 10 times larger than that of the pattern formed on the semiconductor substrate, a decrease in exposure accuracy due to insufficient depth of focus during pattern exposure does not pose a problem.

FIG. 2 is a schematic cross-sectional view showing an example of reduction projection exposure when patterning wiring of a DRAM using the mask shown in the above example. As shown in this figure, when performing reduction projection exposure using the mask according to the present invention, the mask 6 and the semiconductor substrate 7 are placed at predetermined positions where the lenses on both sides of the reduction projection lens 8 are brought into focus. Place them in parallel and facing each other. The semiconductor substrate 7 at this time is
Memory cells and peripheral circuit elements (not shown) are formed on the main surface side, an insulating film 9 having contact holes (not shown) is formed on the surface where these elements are formed, and a wiring material such as aluminum (Al) is formed on this insulating film 9. A layer 10 is deposited, and a resist film 11 is applied thereon.As previously explained with reference to FIG. 3, the memory cell region 12 is formed to be approximately 1 μm higher than the peripheral circuit region 13. Accordingly, the surface of the resist film 11 is also formed so that the surface on the memory cell region 12 is higher than the surface on the peripheral circuit region 13 by about 1 μm.

In this state, images of the Cr film patterns 5C to 5K on the memory cell region mask region 2 of the mask 6 having the structure of the above embodiment are transferred to the memory cell region 12 of the semiconductor substrate 7.
When an image is formed on the upper resist film 11 with best focus, the Cr patterns 5A, 5B, and 5 on the mask area 4 for the peripheral circuit area of the mask 6 are formed due to the characteristics of the projection lens.
The imaging planes (best focus planes) of L and 5M are shifted backward by 1 μm to reflect the 5 μm difference in distance between the mask pattern and the lens (they become closer), and the resist film 11 on the peripheral circuit area 13 of the semiconductor substrate 7 is shifted backward by 1 μm. The image is focused on the top with best focus. Therefore, exposure is carried out for a predetermined time in this state, and thereafter, although not shown, normal resist development is carried out to form a resist pattern reduced to 1/5 of the Cr film patterns 5A to 5M, and this resist pattern is used as a mask for normal resist development. The Al layer 10 is selectively etched by the dry etching means described above to form an Al wiring pattern on the memory cell region 12 and the peripheral circuit region 13 of the semiconductor substrate 7.

In the projection exposure method shown in the above embodiments, by using the mask having the structure according to the present invention, it is possible to improve the performance of a semiconductor device such as a DRAM in which a certain area is formed higher than other areas. , it is possible to simultaneously expose a pattern on high and low areas with best focus. Therefore, even when the width of the pattern is significantly reduced, it is possible to simultaneously perform high-precision pattern projection on high and low regions. This eliminates the possibility of wire breakage due to blurring of focus.

[0023]

As described above, according to the present invention, fine patterns can be reliably formed with high precision simultaneously in high and low regions of a substrate surface having a large difference in height using a projection exposure method. Therefore, defects such as disconnections can be prevented from occurring in wiring patterns formed over the entire surface of semiconductor devices, such as highly integrated DRAMs, which have regions with widely different heights, and their yields and reliability can be improved. I can figure it out.

[Brief explanation of the drawing]

[Fig. 1] A cross-sectional view of the manufacturing process of one embodiment of the mask according to the present invention

FIG. 2 A schematic cross-sectional view of an exposure process according to an embodiment of the method for manufacturing a semiconductor device according to the present invention.

[Figure 3] Schematic cross-sectional diagram showing the main parts of DRAM

[Explanation of symbols]

1 Quartz substrate 2 Mask area for memory cell area 3 Resist pattern 3T, 4T taper part 4 Mask area for peripheral circuit area 5A~5M Cr film pattern 6 Mask 7 Semiconductor substrate 8. Reduction projection lens 9 Insulating film 10 Al layer 11 Resist film 12 Memory cell area 13 Peripheral circuit area

Claims (3)

[Claims] 1. A light-transmitting mask substrate having concave portions and convex portions formed on one main surface, and a light-shielding film pattern formed on the concave portions and convex portions of the main surface of the mask substrate. death,
The concave portion of the main surface of the mask substrate is formed in a region corresponding to a high region of the surface of the substrate to be exposed, and the convex portion of the main surface of the mask substrate is formed in a region corresponding to a low region of the surface of the substrate to be exposed. A mask for semiconductor device manufacturing characterized by: 2. In order to pattern a thin film formed on the entire surface of a semiconductor substrate having high regions and low regions, a resist film formed on the thin film is subjected to projection exposure of a pattern through a mask. A first region of the main surface of the mask substrate corresponding to a high region of the semiconductor substrate is formed in a concave shape, and a second region of the main surface of the mask substrate corresponding to a low region of the semiconductor substrate is formed in a convex shape. 2. A method of manufacturing a semiconductor device, comprising performing projection exposure using the mask according to claim 1, with the main surface of the mask and the surface of the semiconductor substrate facing each other. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a memory cell is formed in a high region of the semiconductor substrate, and a peripheral circuit element is formed in a low region of the semiconductor substrate.