JPH04277845A - Invalidating system for cache error - Google Patents

Abstract

PURPOSE:To invalidate a cache memory without affecting the bus cycle of a processor. CONSTITUTION:At a data processor equipped with the cache memory between a processor 1 and a main storage device 6 which are connected by a bus, a bus arbiter 7 is provided to arbitrate the right of a bus master, and an invalid processing part 13 is provided to make the cache memory invalid by possessing the right of the bus master when cache error is generated while having a bus master function with higher priority order than the processor 1. When the cache error is generated, the right of the bus master is possessed, the access of the relevant processor is inhibited and afterwards, the cache memory is made invalid.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved method for invalidating a cache error in a cache system.

In recent years, cache systems have become popular in order to increase the processing speed of data processing devices. When an error occurs in this cache system, the reliability of the cache system decreases, so the cache is separated, but it is necessary to do this without affecting the bus cycle of the processor.

0003

2. Description of the Related Art FIG. 3 is a diagram showing an example of a cache system. As one method for increasing the speed of a data processing device, as shown in FIG.
A method is adopted in which a high-speed memory (consisting of a cache memory 2 and a static memory SRAM) is placed between the main storage device 6 and a part of the data in the main storage device 6 is stored in the cache memory 2 and accessed at high speed. .

[0004] This cache memory 2 is
The cache control unit 15 has a data area whose address is, for example, lower-order data among the addresses output from the
Data read/write is performed by an SRAM control signal output from the SRAM control signal.

[0005] The TAG memory unit 9 includes a TAG memory that stores upper data using the lower data of the addresses output from the CPU 1 as an address.
The high-order data output from the address is compared with the data accessed by the low-order data and output from the TAG memory, and if they match, a HIT signal is output.

When accessed by the CPU 1, the cache control unit 15 outputs data from the cache memory 2 to the data bus if a HIT signal is output, and outputs data from the cache memory 2 to the data bus.
If the IT signal is not output, cache memory 2
Assuming that there is no corresponding data, the gate 4 is opened, the data from the main memory 6 is bypassed to the CPU 1, and the data is stored in the cache memory 2 by the SRAM control signal.

[0007] In this way, data once read from the main memory device 6 is stored in the cache memory 2, and when the data is accessed again, it is configured to be read from the cache memory 2 at high speed. ing. Note that block transfer is normally performed to the cache memory 2, so that even if a subsequent address is output, data still exists in the cache memory 2.

[0008] In the above-described cache system, high reliability is required as well as high speed, and the parity checker generator PC/PG 3 generates parity and performs a parity check on the read data. If a parity error is detected at the time of HIT, a cache parity error signal CPERR is sent to the cache control unit 15. Similarly, parity is generated for the address data stored in the TAG memory section 9 by the parity generator PG8, and if a parity error is detected by the parity checker PC10, a tag parity error signal TP is generated.
ERR is sent to the cache control unit 15.

[0009] When these cache errors occur, erroneous data is read into the CPU 1, so error processing is performed. On the other hand, if these errors occur, the reliability of the cache system decreases, so the cache control unit 15 disconnects (invalidates) the cache system.

[0010] This disconnection is performed by, for example, setting the valid information "1" set in the valid/invalid register 14 provided in the cache control unit 15 to "0". Access enable signal CAE is negated. As a result, the next access to the cache memory 2 is prohibited, the gate 4 is opened, and the data output from the main storage device 6 is read into the CPU 1.

[0011]

[Problem to be Solved by the Invention] When a cache error (cache parity error and tag parity error) occurs, it is necessary to perform invalidation processing before the next access, as shown in the diagram explaining the problem in FIG. desired. This is possible on slow systems, but on fast systems, invalidation processing cannot be performed before the next access, and there is a possibility that cache memory access and invalidation processing overlap, resulting in processing inconsistencies. There is. For this reason, it is conceivable to perform invalidation processing using an error interrupt, but since the program requires multiple steps, an unreliable cache will be used during that time.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide an invalidation method in the event of a cache error, which invalidates a cache system without affecting processor access.

[0013]

[Means for Solving the Problems] Corresponding functional parts will be extracted from the configuration diagram of an embodiment in FIG. 1 and explained. 1 is a processor CPU, 6 is a main storage device, 2 is a cache memory, and 13 is an invalidation processing unit, which has a bus master function with a higher priority than CPU 1. When a cache error occurs, it acquires bus master rights and uses the cache memory. 2
Performs invalidation processing.

[0014]

[Operation] When a cache error occurs, the invalidation processing section 13 requests bus mastership, and after acquiring the bus mastership, performs invalidation processing. During the invalidation process, CPU 1 cannot access cache memory 2 because it has acquired bus mastership rights, so there is no conflict in processing due to contention, and the CPU 1 can quickly access cache memory 2 without using cache memory 2 whose reliability has deteriorated. Can perform invalidation processing.

[0015]

Embodiment FIG. 1 is a block diagram of one embodiment, and FIG. 2 is a time chart. In Figure 1, 7 is a bus arbiter;
Bus mastership requests from the processor CPU1 and the invalidation processing unit 13 are arbitrated based on priorities. Reference numeral 13 denotes an invalidation processing unit, which has a bus master function with a higher priority than the CPU 1, and when a cache error occurs, acquires bus mastership and performs invalidation processing. The same reference numerals represent the same objects throughout all other figures.

[0016] In the cache system configured as above,
An example of the invalidation process operation will be described with reference to FIG. Clock CL
During the period T0 defined by K, access from CPU1 is started and address ADDRESS is output. At T1, an address strobe signal AS indicating that the address has been determined is output. Also, TAG memory section 9
A HIT signal is output from the cache memory 2 indicating that data corresponding to the corresponding address is stored in the cache memory 2. At T2, data SRAMDATA corresponding to the address from cache memory 2 is transferred to CPU1.
A data response signal STERM (bus control signal as shown) is output from the cache control unit 15 to the CPU 1. PC/PG 3 or PC 10 for T3
A parity error is detected and a CPERR signal or TPERR signal is output to the cache control unit 15. Also, CPU1 uses AS by the STERM signal.
Negate the signal and end the bus cycle.

At T4, the CPERR signal or TPE
In response to the RR signal, the invalidation processing unit 13 of the cache control unit 15 outputs a bus mastership request signal BUSREQ to the bus arbiter 7, requesting bus mastership. At this time, if CPU1 has switched the address and started the next access, the AS signal is asserted at T5. The bus arbiter 7 recognizes this BUSREQ signal, but does not output the bus permission signal BUSGT because the bus cycle of the CPU 1 has started.

[0018] At T7, the AS signal is negated, and the CPU1
When the bus cycle is completed, the bus arbiter 7
At T8, the CPU 1 recognizes the end of the bus cycle and outputs a BUSGT signal to the cache control unit 15.
Notify them that they may use the bus.

At T9, the cache control unit 15
Knowing that the bus was acquired by the SGT signal, BG
It outputs an ACK signal to notify the bus arbiter 7 that the cache control unit 15 is using the bus. Also B
The BUSREQ signal is negated by the USGT signal. Also, at T11, the BUSG
T signal is negated. At T12, the cache control unit 15 has acquired the bus mastership, so the CPU 1
is guaranteed not to have bus access. Then, it clears the valid/invalid register 14 and negates the cache access enable signal CAE, which is an internal signal, to invalidate the cache.

At T14, since the bus mastership is released, the CPU 1 outputs an address and starts accessing. However, since the cache memory 2 is disabled, no data is output from the cache memory 2, and data is output from the main storage device 6 to the CPU 1 at T17.

As described above, since the cache control unit 15 has the bus master right, acquires the bus master right, and performs the invalidation process, there is no access from the CPU 1 during that time, and in the worst case, the invalidation process is performed after one bus cycle. It can be carried out. As a result, invalidation can be performed without using a cache with reduced reliability and without conflicting with access by the CPU 1, improving reliability in invalidation processing.

[0022]

As explained above, in the present invention, the cache is invalidated by acquiring the bus master right, so it is easy to implement even when the system becomes high speed, and the bus master right is transferred from the CPU to the cache controller. By giving priority to the cache, the cache can be invalidated with just one cycle of CPU access in the worst case, the time from error occurrence to cache invalidation can be shortened, and unreliable cache can be used when an error occurs. Since it can be disabled without having to do so, reliability is improved.

[Brief explanation of the drawing]

[Figure 1] Configuration diagram of one embodiment

[Figure 2] Time chart diagram

[Figure 3] Diagram showing an example of a cache system

[Figure 4]
Assignment explanation diagram

[Explanation of symbols]

1 Processor CPU 2 Cache memory 3 Parity checker generator PC/PG4
Gate 6 Main memory 7 Bus arbiter 8 Parity generator PG 9 TAG memory section 10 Parity checker 11 Main memory control section 12, 15 Cache control section 13 Invalidation processing section 14 Valid/invalid register

Claims (1)

[Claims] [Claim 1] Processor (1) connected by a bus
Cache memory (2) between and main storage (6)
A data processing device is equipped with a bus arbiter (7) that arbitrates bus mastership, and a bus master function that has a higher priority than the processor, and when a cache error occurs, acquires bus mastership and transfers the bus mastership to the cache memory (2). and an invalidation processing unit (13) that performs invalidation processing of the cache memory, and when a cache error occurs, acquires bus mastership and prohibits access by the processor, and then performs invalidation processing of the cache memory. Invalidation method in case of cache error.