JPH04274091A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enlarge a difference between the output voltage of a sense line to a differential amplifier circuit and the output voltage of a reference line, by connecting the drain of the load transistor(Tr) of a memory cell with the gate electrode o the load Tr of a dummy cell and mutually connecting the drains of a first and a second load Tr of the dummy cell. CONSTITUTION:When the logic state of the memory cell 201 is zero, namely, when a data is written on the memory cell 201, the potential value Vsin of the sense line SL becomes a voltage VB at the intersected points of a drain voltage-current characteristic line (line 2) of the cell 201 and the static characteristic line (line 3). The potential value VR of the reference line RL becomes a voltage VA at the intersected points of the drain voltage-current characteristic line (line 1) when the logic state of the memory cell 201 is one and the line 3. By the differential amplifier circuit 217, Vsin and VR are compared, the logic state of the cell 201 is judged, and the result is outputted Vsout. Meantime, when the logic state of the cell 201 is '1', the value of Vin is VA, and the load Tr 215 is on continuity as a potential difference is generated among the source drains. The VR becomes a voltage VD at the intersected points of the line 1 and the load curve of the reference side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory cell, and particularly to a sense amplifier.

0002

2. Description of the Related Art FIG. 2 shows a circuit diagram of a conventional sense amplifier. The conventional technology will be explained using FIG. 2.

First, to show the configuration of a conventional sense amplifier, a memory cell transistor 201 (hereinafter referred to as a memory cell) is actually a plurality of memory cells connected in parallel, but in this case, a 1-bit memory cell Only shown. A reference dummy cell transistor 203 (hereinafter referred to as dummy cell) has the same characteristics as the memory cell 201. This memory cell 201 is a floating gate type n-channel MOS transistor (hereinafter referred to as NMOS),
The gate electrode is connected to a word line (WL), the drain is connected to a bit line, and the source is connected to ground (GND). When data is being written to the memory cell 201, the threshold value becomes high, so the memory cell 201 becomes non-conductive or the amount of current becomes small. The dummy cell 203 is always in an unwritten state. In this case, the logic state in which no data is written is represented as "1", and the logic state in which data is written is represented as "0". Transistor 205 is a transfer transistor that is switched by a decode signal (Y), and transistor 211 is a corresponding transistor. transistor 20
9 is a transfer transistor that inputs a constant voltage (VBB) to the gate electrode, and when a high voltage is applied to the bit line,
This is to prevent data from being written into the memory cell 201 by mistake. The transistor 211 is a corresponding transistor.

Transistors 205, 207, 209, 2
No. 11 uses NMOS. The load transistor 213 of the memory cell 201 and the load transistor 215 of the dummy cell 203 are P-channel MOS.
A transistor (hereinafter referred to as PMOS) is used, and the mutual conductance gm of PMOS215 is expressed as PMO
By making gm of S213 larger than gm, the voltage (VR) of the reference line (RL) is equal to the voltage (Vsin) of the sense line (SL) generated for the logic state of the read cell.
) between the maximum and minimum voltages.

In general, the load transistors are diode-coupled for read speed and voltage consistency as a differential amplifier input, and the load transistors of the memory cell and the load transistor of the dummy cell are connected to each other in consideration of the power supply voltage margin. The conductance ratio is set to 1:2. The differential amplifier circuit 217 is a common one.

Next, the circuit operating characteristics of the conventional sense amplifier will be explained with reference to FIG.

FIG. 3 is a graph showing the static characteristics of the memory cell 201, the load transistor 213, and the load transistor 215.

In this case, the horizontal axis represents the voltage (Vsin) of the sense line (SL) or the potential (VR) of the reference line (RL).
), and the vertical axis indicates the current flowing through the load transistor 213 or the load transistor 215. Solid line ■ and ■
is the gate voltage (VCC), which indicates the drain voltage-source-drain current characteristics of the memory cell 201, where the solid line ■ indicates the logic state "1", that is, when no data is written, the solid line ■ indicates the logic state "0". ”, that is, when data is written, it is on the same line as the horizontal axis. Also,
The broken line ■ represents the characteristics of the load transistor 213, and the dashed line ■ represents the characteristics of the load transistor 215.
The mutual conductance ratio of load transistors 213 and 215 is 1:2. Since the current flowing through the load transistor 213 is equal to the current flowing through the memory cell 201, the value of the voltage (Vsin) of the sense line (SL) is the same as the solid line ■ and the broken line ■ when the logic state of the memory cell 201 is "1". When the logic state of the memory cell 201 is "0", the voltage VB corresponds to the abscissa of the intersection B between the solid line (2) and the broken line (2). Also, VT
P is the threshold of load transistors 213 and 215.

On the other hand, since the logic state of the dummy cell 203 is always "1", the voltage (VR) of the reference line (RL) is the intersection point C between the solid line ■ and the dot-dash line ■ of the load transistor 215.
The voltage Vc corresponds to the abscissa of .

The differential amplifier circuit 217 has a sense line (SL)
The voltage (Vsin) of the cell is compared with the voltage (VR) of the reference line to determine whether the logic state of the cell is "1" or "0", and the result is outputted as Vsout.

[0011]

As described above, the mutual conductance ratio of the load transistor 213 of the memory cell 201 and the load transistor 215 of the dummy cell 203 is usually set to 1:2. This mutual conductance ratio has a great deal to do with the power supply voltage margin of the device.

FIG. 4 shows the gate-source voltage (VGS) and drain-source current (IDS) of the memory cell 201.
) is plotted by linear approximation, and the graph (2) for the logic state "0" is obtained by translating the graph (2) for the logic state "1" by ΔV in the horizontal axis direction.

On the other hand, the memory cell 201 in the logic state "1"
VG with the mutual conductance gm reduced to 1/n
When the S-IDS characteristics are plotted, they look like the broken line ■ in FIG. In FIG. 4, the maximum value of the power supply voltage (Vcc
max) is the intersection of the solid line (2) with the logic state "0" and the broken line (2), and the smaller n is, the larger Vccmax is.

Conversely, the minimum value Vccmin of the power supply voltage is determined by the point at which the differential amplifier circuit 217 can detect the difference between VR and Vsin, so the larger n is, the smaller it is.

From these facts, a good power supply voltage (Vc
c) To obtain a margin, the transconductance (gm) ratio of the memory cell load transistor and the dummy cell load transistor is usually set to 1:2.

However, since the load transistor is diode-coupled, as shown in FIG.
and VB instead of the intermediate voltage (VA + VB)/2
I lean towards the A side.

Furthermore, since Vsin only takes a high or low voltage depending on the logic state of the memory cell using VR as a reference voltage, there is a problem that the voltage difference is small when used as an input to the differential amplifier circuit 217.

Moreover, these problems make it difficult to adjust the gm of the load transistor, which significantly reduces the degree of freedom in designing the sense amplifier.

[0019]

Means for Solving the Problems The present invention provides a sense amplifier for detecting a logic state of a memory cell, in which the drain of a load transistor of a memory cell is connected to the gate electrode of a first load transistor of a dummy cell, and The above problem is solved by connecting the drain of the first load transistor and the drain of the second load transistor of the dummy cell.

[0020]

[Operation] By using the above configuration, the present invention has the following features:
When the logic state of the memory cell 201 is “0”, that is, when data is being written, the third load transistor 2
Since there is no potential difference between the source and drain of the third load transistor 215, the third load transistor 215 becomes non-conductive, and the sense line SL
The voltage Vsin of the reference line VR and the voltage VR of the reference line VR are determined from the static characteristics (■) of the second load transistor 219 and the static characteristics (■) and (■) of each logic state of the memory cell in FIG.
=VB, VR =VA, and the differential amplifier circuit 21
7 becomes larger.

On the other hand, when the logic state of the memory cell is "1", that is, when no data is written, a potential difference occurs between the source and drain of the third load transistor 215, and the third load transistor 215 becomes conductive. Therefore, the voltage Vsin of the sense line SL and the voltage VR of the reference line VR
From the static characteristics (■) which is a combination of the second load transistor 219 and the third load transistor 215 in FIG. 5, and the static characteristics (■) and (■) of each logic state of the memory cell, Vsi
n = VA, VR = VD, and the differential amplifier circuit 2
The voltage amplitude input to 17 becomes larger.

[0022]

Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. The configuration of the sense amplifier in FIG. 1 is such that a new PM is added to the load transistor of the dummy cell 203 of the conventional sense amplifier in FIG.
It is equipped with an OS 219. Components that are the same as those of the conventional sense amplifier shown in FIG. 2 are designated by the same reference numerals, and description thereof will be omitted.

The PMOS 219 has a source connected to the power supply VC.
The drain of C is connected to the reference line RL. Further, the gate electrode is connected to a sense line SL.

In this case, it is assumed that the mutual conductances gm of PMOSs 213, 215, and 219 are the same.

FIG. 5 is a graph showing the operating characteristics of this circuit, and shows the static characteristics of the memory cell 201, the load transistor 213 of the memory cell 201, and the load transistors 215 and 219 of the dummy cell 203.

In this case, the horizontal axis represents the potential Vs of the sense line SL.
in or the potential VR of the reference line RL, and the vertical axis indicates the current flowing through each transistor.

The solid line (■) in FIG. 5 indicates when the logic state of the memory cell 201 is "1", that is, when no data is written, and the solid line (■) indicates that the logic state of the memory cell 201 is "0".
The drain voltage-current characteristics of the memory cell 201 when data is being written are shown. Furthermore, the dashed line ■ indicates the static characteristics of the load transistor 219, the dashed-dotted line ■ shows the static characteristics of the load transistor 215, and the dashed-double line ■ is a combination of the dashed line ■ and the dashed-dotted line ■.
This is the case when each load transistor is conductive.

When the logic state of the memory cell 201 is "0", that is, when data is written in the memory cell 201, the value of Vsin is a voltage corresponding to the abscissa of the intersection B of the solid line ■ and the broken line ■. It becomes VB. Further, the value of VR is the voltage VA corresponding to the abscissa of the intersection point A between the solid line (■) and the broken line (■).

Here, the differential amplifier circuit 217 has Vsin
and VR are compared to determine the logic state of the memory cell 201, and the result is outputted as Vsout. VTP is the threshold of load transistor 219.

On the other hand, the logic state of the memory cell 201 is “1”.
”, that is, when no data is written to the memory cell 201, the value of Vsin is VA corresponding to the abscissa of the intersection of the solid line 2 and the broken line 2, and at this time, the load transistor 215 is connected to the source Since a potential difference occurs between the drains and conduction occurs, the load curve on the reference side is represented by the two-dot chain line ■.Therefore, VR is the voltage VD corresponding to the abscissa of the intersection D between the solid line ■ and the two-dot chain line ■. .

Here, the differential amplifier circuit 217 has Vsin
and VR are compared, the logic state of the memory cell 201 is determined, and the result is outputted as Vsout.

[0032]

As described above in detail, according to the present invention, the output voltage VR of the reference line RL is changed from the output voltage VR of the reference line RL to the sense line SL.
Since the output voltage Vsin moves in the opposite direction to the output voltage Vsin of , operate at similar voltage levels, allowing for a wide power supply voltage margin and greater freedom in differential amplifier circuit design.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a sense amplifier of the present invention.

FIG. 2 is a circuit diagram showing the configuration of a conventional sense amplifier.

FIG. 3 is a diagram showing static characteristics of a memory cell 201 and load transistors 213 and 215.

FIG. 4: Gate-source voltage (V
GS) and a drain-source current (IDS) using a linear approximation.

FIG. 5 is a diagram showing static characteristics of a memory cell 201 and load transistors 215 and 219.

[Explanation of symbols]

201 Memory cell 203 Dummy cell 213 Memory cell load transistor 215,
219 Dummy cell load transistor 217
differential amplifier circuit

Claims (3)

[Claims] 1. A memory cell having a first and a second terminal and storing a first or second logic level, wherein when the first logic level is stored, the memory cell has a first terminal and a second terminal. The state between the second terminals is the first resistance state, and when the second logic level is stored, the state between the first terminal and the second terminal is the second resistance state different from the first resistance state. a first transistor having a memory cell in a resistance state of , a source to which a potential is applied from a first power supply, and a drain connected to a first terminal of the memory cell, the drain being in a resistance state of the first transistor; a load reference element having a first transistor connected to a gate electrode of the transistor, a first terminal to which a potential is applied from a second power source having a potential different from the first power source, and a second terminal; , a second transistor having a source supplied with a potential from the first power supply and a drain connected to the second terminal of the load reference element, wherein the drain of the first transistor is connected to the second transistor. A semiconductor device comprising: a second transistor connected to a gate electrode of the first transistor; and a differential amplifier circuit connected to a drain of the first transistor and a drain of the second transistor. 2. The first resistance state is a conduction state between the first terminal and the second terminal of the memory cell, and the second resistance state is a state where the first terminal and the second terminal of the memory cell are electrically connected. 2. The semiconductor device according to claim 1, wherein the terminals of the semiconductor device are substantially non-conductive. 3. The load reference element includes a dummy cell having the same characteristics as the memory cell, a third transistor having a source supplied with a potential from the first power supply, and a drain connected to the drain of the second transistor. 2. The semiconductor device according to claim 1, further comprising a third transistor, the drain of which is connected to the gate electrode of the third transistor.