JPH04273173A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE:To prevent generation of warpage of wafer and dislocation by misfitting even in the case of stacking a heteroepitaxial growth layer on a substrate having different grating constant. CONSTITUTION:A P-type AlGaAs layer 2, an N-type AlGaAs layer 4 are continuously formed on the surface of a GaAs substrate 1 and an electrode 5 is provided at the upper surface of this N-type AlGaAs layer 4. At the rear surface of substrate 1, a P-type AlGaAs layer 3 is provided to prevent generation of warpage of substrate and dislocation by misfitting. An electrode 6 is also provided to this P-type AlGaAs layer 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed on a semiconductor single crystal substrate by a heteroepitaxial method and a method for manufacturing the same.

0002

2. Description of the Related Art Silicon (Si) is extremely excellent as a semiconductor material for microelectronics. In recent years, various semiconductor devices have been proposed that make full use of heteroepitaxial technology to add electronic functions that silicon does not have. Typical examples include a light emitting device in which a mixed crystal such as AlGaAs is grown heteroepitaxially on a GaAs substrate, and a GaAs/Si device in which GaAs is heteroepitaxially grown on a Si substrate.

By the way, in heteroepitaxial growth, mismatching of lattice constants poses a problem. For example, Al0.40
In Ga0.60As/GaAs, a lattice mismatch of about 0.04% occurs. Therefore, the diameter is 41 mm and the thickness is 300 mm.
Al0.35Ga0.65As on μm GaAs substrate
When 10 μm of layers are stacked, a warpage of about 50 μm occurs. After that, when the warped wafer is subjected to the device manufacturing process, cracks may occur on the wafer, and Ga
Misfit dislocations (dislocations based on lattice mismatch) generated at the interface between the As substrate and the AlGaAs group extend into the interior of the AlGaAs group, and become a factor that deteriorates the characteristics of the device. On the other hand, in the case of GaAs/Si, the lattice mismatch is actually close to 4%, which is a major obstacle to the practical application of GaAs/Si based elements.

0004

[Problems to be Solved by the Invention] As mentioned above, when heteroepitaxially grown layers are stacked on substrates with different lattice constants, there is a problem that wafer warpage and misfit dislocation occur due to lattice mismatch, etc. ing.

The present invention was made to solve the above problems, and its purpose is to prevent wafer warpage and misfit even when heteroepitaxially grown layers are stacked on substrates with different lattice constants. The present invention aims to provide a semiconductor device and a method for manufacturing the same that can prevent the occurrence of dislocations, prevent wafer cracking in the device manufacturing process, and improve the reliability of the device.

[0006]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides an element forming layer formed by heteroepitaxial growth on the surface of a semiconductor single crystal substrate, in which a semiconductor element is formed, and an element forming layer formed on the surface of a semiconductor single crystal substrate. An epitaxial layer formed by heteroepitaxial growth is provided on the back surface of the substrate.

[0007] Furthermore, the element formation layer is formed by successively forming a first conductivity type semiconductor layer and a second conductivity type semiconductor layer from the substrate by heteroepitaxial growth, and constitutes a diode. Furthermore, a Schottky gate field effect transistor is formed in the element formation layer.

Further, the element forming layer is provided with an element forming part and a dicing part made of the same semiconductor as the substrate and continuous with the substrate, and a semiconductor element is formed in each of the element forming part and the element forming layer. ing.

Furthermore, the present invention forms an element formation layer in which a semiconductor element is formed by heteroepitaxial growth on the front surface of the semiconductor single crystal substrate, and forms an epitaxial layer on the back surface of the semiconductor single crystal substrate by heteroepitaxial growth. is forming. Further, the element forming layer and the epitaxial layer are formed in the same epitaxial growth process.

Further, an element forming part and a dicing part made of the same semiconductor as the substrate and continuous with the substrate are provided in the element forming layer, and a semiconductor element is formed in each of the element forming part and the element forming layer, The central part of the dicing section is diced, and the diced semiconductors on both sides are left.

[0011]

[Operation] That is, according to the present invention, an element forming layer in which a semiconductor element is formed by heteroepitaxial growth is provided on the front surface of a semiconductor single crystal substrate, and an epitaxial layer is formed by heteroepitaxial growth on the back surface of the semiconductor single crystal substrate. Therefore, it is possible to prevent warping of the substrate and occurrence of misfit dislocations.

Furthermore, since an epitaxial layer is also provided on the back surface of the substrate, even when a diode is constructed by forming a first conductivity type semiconductor layer and a second conductivity type semiconductor layer on the element forming layer by heteroepitaxial growth. , it is possible to prevent deterioration of diode characteristics.

Furthermore, since an epitaxial layer is provided on the back surface of the substrate, even when a Schottky gate field effect transistor is formed in the element formation layer, deterioration of the characteristics of the transistor can be prevented.

Furthermore, since an epitaxial layer is also provided on the back surface of the substrate, the element forming layer is made of the same semiconductor as the substrate.
Even when an element forming part and a dicing part are provided that are continuous with the substrate, and the dicing part is diced after forming a semiconductor element in each of the element forming part and the element forming layer, the substrate can be prevented from cracking.

Furthermore, the present invention forms an element formation layer in which a semiconductor element is formed by heteroepitaxial growth on the front surface of a semiconductor single crystal substrate, and also forms an epitaxial layer on the back surface of the semiconductor single crystal substrate by heteroepitaxial growth. After that, a semiconductor element is formed on the element forming layer. Therefore, it is possible to prevent the warping of the substrate and the occurrence of misfit dislocations, so that the characteristics of the semiconductor device can be made uniform and the yield of the device can be increased. Further, by forming the element forming layer and the epitaxial layer on the back surface of the substrate in the same process, it is possible to prevent an increase in the number of manufacturing steps.

Furthermore, an element forming part and a dicing part made of the same semiconductor as the substrate and continuous with the substrate are provided in the element forming layer, a semiconductor element is formed in each of the element forming part and the element forming layer, and the dicing part is made of the same semiconductor as the substrate. By dicing the central part of the part and leaving the diced semiconductors on both sides, it is possible to further prevent the substrate from cracking.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the invention. This example uses AlGaA with a wavelength of 600 nm.
This figure shows a case in which a visible light diode is fabricated on a GaAs substrate. In the figure, a GaAs single crystal substrate 1 is a P-type GaAs single crystal plate with a (100) plane orientation, a thickness of 300 μm, and a diameter of 41 mm. Both surfaces of this substrate 1 are simultaneously coated with P-type Al0 with a thickness of 10 μm by a liquid phase growth method such as a dipping method.
．． 35Ga0.65As layers 2 and 3 are formed, and on this P type AlGaAs layer 3, N type Al0.30Ga0.
A 70As layer 4 is formed. By liquid phase growth method,
P-type AlGaAs layers 2 and 3 and N-type AlGaAs
When forming layer 4, the impurity in the tank is first made into P type, and then it is continuously formed as N type, or the impurity in the tank is made into P type.
It is also possible to provide a tank containing As and a tank containing N-type AlGaAs, and to sequentially immerse the wafer in these tanks. N on the P-type AlGaAs layer 3
When forming the P-type AlGaAs layer 4, P-type AlGaAs layer 4 is formed.
An N-type AlGaAs layer is simultaneously formed under the As layer 2, but this N-type AlGaAs layer is removed by polishing after formation. The warpage of the epitaxial wafer thus formed was several μm, and no misfit dislocations or cross hatches were observed on the surface of the element forming layer.

After patterning this epitaxial wafer and providing an electrode 5 made of, for example, Au on the N-type AlGaAs layer 4, and providing an electrode 6 made of, for example, Au-Cr below the P-type AlGaAs layer 2, , and diced into chips with a chip size of 300×300 μm2. Conventionally, the wafer cracking rate was 50% in the process before dicing.
As described above, in the case of this example, no cracking of the wafer occurred even if the same process as above was repeated 10 times.

In this embodiment, the P-type AlGaAs layer 2
, 3 are successively formed with N-type AlGaAs layers on both sides of the substrate 1.
s layers 2 and 3 are formed, and then AlGaA on the element formation side is formed.
Even if only the s-layer 4 is formed, the result is the same.

FIG. 2 shows the optical output of the light emitting diode according to this example when current is applied at 10 mA in correlation with the crystal defect density (EPD) of the GaAs substrate, and the horizontal axis represents E.
PD (numbers/cm2), the vertical axis is optical output (mV). In the figure, a shows the case of the present invention, and b shows the characteristics of a conventional light emitting diode. As is clear from the figure, in the light emitting diode manufactured by the conventional method, the light output tends to decrease when the EPD of the substrate becomes several 1000 cm-2 or more. For this reason, it could not be used for anything other than low-EPD crystal substrates produced by the boat growth method. However, the light output of the light-emitting diode using this invention is higher than that produced by the conventional method, and in the high-EPD region. Also, the optical output does not decrease and remains almost constant. For this reason, G
An aAs substrate can be used. In the pulling method, EPD tends to be high at the periphery and center of the crystal. For this reason, in the diode using the conventional method,
Although there was a drawback that an error occurred in the optical output depending on the position of the wafer, this invention can solve this problem.

That is, FIG. 3 shows GaA obtained by the pulling method.
This figure shows the optical output distribution of the diode along the <100> radial direction of the s-substrate, where a shows the case according to the present invention and b shows the case according to the conventional method. According to this invention, even if a GaAs substrate produced by a pulling method is used, the light outputs of a plurality of light emitting diodes manufactured from one wafer can be made uniform at a high level.

FIG. 4 shows the change over time in the optical output when 25 mA is applied as an index of the reliability of the light emitting diode. The horizontal axis shows the energization time (H), and the vertical axis shows the residual rate of light output (
100 of relative light output when initial is 100
percentage). In the figure, a is an example of a diode according to the present invention, and b is an example of a diode according to a conventional method. As is clear from the figure, the optical output of the diode according to the present invention hardly changes over time, whereas the optical output of the diode according to the conventional method deteriorates over time. This difference is considered to be due to cracks that have entered the AlGaAs layer and differences in dislocation density. In the conventional method, it is considered that cracks and dislocation density tend to increase when the EPD content of the substrate is large.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, GaAs layers are formed on both sides of a Si substrate, and on one GaAs layer, for example, S
It forms RAM. In other words, the surface orientation (10
0), both sides of the N+ Si substrate 51 as a wafer with a diameter of 2 inches are coated with MOCV using, for example, infrared heating.
D (Metal Organic Chemical V
GaAs layers 52 and 53 are formed simultaneously by an apordeposition (organic metal vapor phase epitaxy) method. Inside these GaAs layers 52 and 53, in order from the substrate 51 side, an undoped layer with a thickness of 1.0 μm,
A 1.5 μm thick vanadium (V) doped layer and a 1.0 μm thick undoped layer are successively formed. These layers are formed, for example, by changing the timing of adding impurities.

In this way, GaA is deposited on both sides of the substrate 51.
As a result of measuring the warpage of the wafer with the S layers 52 and 53 formed, the warpage was several μm. The warpage of the substrate obtained by the conventional method in which no epitaxial layer is formed on the back surface of the substrate is 58 μm, and it can be seen that the warp is significantly improved by the structure of the present invention.

In the GaAs layer 53, an SRAM is installed inside a chip having a size of 4 mm x 4 mm by a well-known method.
Schottky gate field effect transistor, which comprises
For example, LDD (Lighty Doped Dra
In) MESFET 54 of structure was provided. This MESF
ET 54 includes source and drain regions 55 and 56, a channel region 57 formed between these source and drain regions 55 and 56, a gate electrode 58 provided on this channel region 57, and source and drain region 5.
It is constituted by electrodes 59 and 60 provided on 5 and 56. After this, the wafer is diced and each chip is separated. In the conventional manufacturing method, many chippings and cracks occurred in the pellets after dicing, but in this example, no such defects occurred.

FIG. 6 shows the distribution of the threshold voltage (Vth) of the MESFET according to the present invention, and FIG. 7 shows the distribution of the threshold voltage (Vth) according to the conventional manufacturing method. The total number of test elements is 324 in the case of the present invention and 274 in the case of the conventional example. As is clear from FIGS. 6 and 7, in the conventional example, the threshold voltage is 0 to 0.4 (V).
However, in this invention, it is distributed between 0.2 and 0.
．． 4 (V) or less, and the error in threshold voltage for each element is reduced. Therefore, the operating characteristics of this invention are improved. This is considered to be due to a decrease in warpage, strain, or dislocation density.

Next, regarding the third embodiment of the present invention,
This will be explained with reference to FIGS. 8 and 9. This example shows a composite semiconductor device in which a compound semiconductor device and a Si semiconductor device are provided on a Si single crystal substrate, which is applied to, for example, an OEIC (Opto-Electronic IC).

That is, on both sides of the Si single crystal substrate 71, GaAs layers 72,
73 is formed. Thereafter, a silicon oxide film 74 is formed on the GaAs layer 73, and an opening 75 is formed in a portion that will become a dicing region and an element formation region. This opening 75
RIE using the silicon oxide film 74 formed as a mask
(Reactive Ion Etching)
A plurality of openings 76 are formed in the GaAs layer 73 through which the substrate 71 is exposed. Next, the plurality of openings 76 are filled with silicon 77 by selective epitaxial method to form a dicing region 78 and an element formation region 79 made of silicon single crystal. Thereafter, the silicon oxide film 74 is removed and a predetermined wafer process is performed to form a Si semiconductor element 81 in the element formation region 79 and a compound semiconductor element 82 in the element formation region 80, as shown in FIG. . Next, the center of the dicing region 78 is cut and separated into pellets surrounded by the remaining silicon 77.

[0030] In this embodiment, as in both of the above embodiments, it is possible to reduce warpage and dislocation of the substrate, and it is also possible to prevent chipping and cracking during dicing, thereby increasing the yield of devices. be able to. Note that this invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention.

[0031]

[Effects of the Invention] As detailed above, according to the present invention, even when a heteroepitaxially grown layer is deposited on a substrate having a different lattice constant, it is possible to prevent wafer warpage and misfit dislocation from occurring. Accordingly, it is possible to provide a semiconductor device and a method for manufacturing the same, which can prevent wafer cracking in the device manufacturing process and improve the reliability of the device.

[Brief explanation of the drawing]

FIG. 1 is a side sectional view showing a first embodiment of the invention.

FIG. 2 is a diagram showing the dependence of the crystal defect density of a substrate on the optical output of the light emitting device shown in FIG. 1;

FIG. 3 is a diagram showing the distribution of light output from the light emitting element shown in FIG. 1 within the substrate.

FIG. 4 is a diagram showing the residual rate of light output of the light emitting element shown in FIG. 1;

FIG. 5 is a side sectional view showing a second embodiment of the invention.

FIG. 6 is a diagram showing a distribution of threshold voltages of the semiconductor element shown in FIG. 5;

FIG. 7 is a diagram showing a distribution of threshold voltages of a conventional semiconductor device.

FIG. 8 is a side sectional view showing a third embodiment of the invention.

FIG. 9 is a side sectional view showing a different state of FIG. 7;

[Explanation of symbols]

1, 51, 71... Substrate, 3, 4, 53, 73... Element formation layer, 2, 52, 72... Back side epitaxial layer,
79...Element formation region, 78...Dicing section.

Claims (7)

[Claims] 1. An element forming layer formed by heteroepitaxial growth on the front surface of a semiconductor single crystal substrate, in which a semiconductor element is formed, and an epitaxial layer formed by heteroepitaxial growth on the back surface of the semiconductor single crystal substrate. A semiconductor device characterized by: 2. The element forming layer comprises a diode in which a first conductivity type semiconductor layer and a second conductivity type semiconductor layer are successively formed from the substrate by heteroepitaxial growth. semiconductor devices. 3. The semiconductor device according to claim 1, wherein a Schottky gate field effect transistor is formed in the element formation layer. 4. The element forming layer is provided with an element forming part and a dicing part made of the same semiconductor as the substrate and continuous with the substrate, and a semiconductor element is formed in each of the element forming part and the element forming layer. The semiconductor device according to claim 1, characterized in that: 5. An element forming layer in which a semiconductor element is formed is formed by heteroepitaxial growth on the front surface of the semiconductor single crystal substrate, and an epitaxial layer is formed by heteroepitaxial growth on the back surface of the semiconductor single crystal substrate. A method for manufacturing a semiconductor device, characterized by: 6. The method of manufacturing a semiconductor device according to claim 5, wherein the element forming layer and the epitaxial layer are formed in the same epitaxial growth step. 7. An element forming part and a dicing part made of the same semiconductor as the substrate and continuous with the substrate are provided in the element forming layer, and a semiconductor element is formed in each of the element forming part and the element forming layer, 6. The method of manufacturing a semiconductor device according to claim 5, further comprising dicing a central portion of the dicing portion and leaving semiconductors on both sides of the diced portion.