JPH04268812A - Digital timing discriminator and method for discrimination of frequency - Google Patents

Abstract

PURPOSE: To detect the frequency of a data input signal with a superior precision by monitoring a counted value for a prescribed frequency threshold. CONSTITUTION: The operation of a frequency discriminator circuit 10 gives a logical '1' output signal in an output 46, if the frequency of the data input signal applied to an input 12 is higher than a prescribed frequency threshold. The prescribed frequency threshold is determined by the frequency of a reference signal applied to an input 28 and the counted value monitored by decoding circuits 32 and 34. The output signal in the output 46 goes to logical '0', when the frequency of the data input signal is made lower than the frequency threshold. That is, the output signal is kept in the first logical state to indicate that the frequency of the data input signal is higher than the prescribed frequency threshold, if the counted value is reset by the data input signal before reaching a prescribed value. The signal is switched to a second logical state to indicate that the frequency of the data input signal is lower than the prescribed frequency threshold, if the counted value reaches the prescribed counted value before a reception of the reset signal.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates generally to digital timing discriminators with improved frequency detection resolution for identifying whether the frequency of a data input signal is above or below a predetermined threshold. .

0002

BACKGROUND OF THE INVENTION Frequency discriminator circuits are used in numerous applications where it is necessary to discriminate the frequency of a data input signal about a predetermined threshold. For example, magnetic disk
In applications that control drive servomechanisms, it is necessary to distinguish whether the frequency of the data input signal is above or below a threshold or reference frequency. A typical prior art technique for frequency discrimination uses a D-type flip-flop in combination with a timing capacitor and a comparator to monitor the voltage on the timing capacitor with respect to a reference potential. The output of the comparator is coupled to the data input of a second D-type flip-flop, and the data input signal is applied to the clock input of the flip-flop to provide an output signal indicating whether the frequency of the input signal is greater or less than a predetermined threshold. give. Logic 1 is D
The data input signal is applied to the clock input of the D-type flip-flop. The output signal of the D-type flip-flop is passed back to the reset input to generate a narrow pulse at its Q output. A narrow pulse charges the timing capacitor,
A current source continuously discharges this capacitor. The triangular voltage waveform developed on the timing capacitor is compared to a reference potential to provide a high output signal if the timing capacitor voltage is greater than the reference potential, and a low output signal if the timing capacitor voltage is less than the reference potential. give.

If the frequency of the data input signal is greater than a predetermined threshold, the narrow pulses appearing at the Q output of the D-type flip-flop circuit repeat quickly enough to raise the voltage on the timing capacitor above the reference potential. and the output signal will also remain high. Alternatively, if the frequency of the data input signal is low, the interval between the output pulses of the D-type flip-flop may be longer, allowing the current source to discharge the timing capacitor below the reference potential. The output signal of the frequency discriminator circuit drops to a logic 0, indicating that the frequency of the data input signal is less than a predetermined threshold. This threshold is determined by several analog control parameters including the capacitor value, the amount of power flowing through the current source, the reference potential, etc.

0004

Unfortunately, timing capacitors and current sources are temperature dependent devices.
It is influenced by variations in the manufacturing process, and on the other hand, the reference potential often contains external noise. It is difficult to maintain a stable operating point for a given frequency threshold since the above-mentioned variations in the analog control parameters limit their accuracy and also limit the resolution of the frequency discriminator circuit. This is particularly difficult when attempting to track data input signals over a range of frequencies. Analog components such as timing capacitors, current sources, and external reference potentials should be eliminated.

[0005]Therefore, a need arises for an improved frequency discrimination circuit that has greater accuracy in distinguishing frequencies of data input signals for a predetermined threshold.

[0006]

SUMMARY OF THE INVENTION In summary, the present invention includes a first circuit coupled to receive a data input signal and provide a first reset signal in response to the data input signal; It consists of a frequency discriminator circuit that adjusts the count value in response to the signal. A second circuit is also coupled to receive the first reset signal of the first circuit that resets the count value. The third circuit monitors the count value and has a first state when the count value is reset before reaching a predetermined count threshold, and a second state when the count value reaches a predetermined count threshold. generates an output signal with

In yet another example, the invention is a method of discriminating the frequency of a data input signal for a predetermined frequency threshold. A reset signal is generated in response to the data input signal, and the reset signal resets the count while the count value is adjusted in response to the reference signal. The count value is monitored and the output signal has a first state when the count value is reset before the predetermined count threshold and has a second state when the count value reaches the predetermined count threshold. give.

The frequency discriminator circuit has high resolution and detects the frequency of the data input signal for a predetermined frequency threshold by monitoring the count value. At this time, the output signal of the frequency discriminator circuit is is maintained at a first logic state when reset by the data input signal before the predetermined count value is reached, indicating that the frequency of the data input signal is greater than the predetermined frequency threshold. The output signal of the frequency discriminator circuit switches to a second logic state when the count value reaches a predetermined count value prior to receiving the reset signal, thereby indicating that the frequency of the data input signal is less than the predetermined frequency threshold.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a frequency discriminator circuit 1 suitable for fabrication in integrated circuit form using conventional integrated circuit processing techniques.
Indicates 0. A data input signal is applied to input 12 and is applied to the clock input of D-type flip-flop 16 via frequency divider circuit 14 . The data input of D-type flip-flop 16 receives a logic one from power supply conductor 18, which typically operates at a positive potential, such as VDD. The Q output of D-type flip-flop 16 generates a reset 1 signal at the reset input of the D-type flip-flop and also at the reset input of counter 20. The output signal of the frequency divider circuit 14 is passed through an inverter 22 to a D-type flip-flop 2.
4 and is applied to the clock input of D-type flip-flop 2.
Data input 4 is coupled to receive a logic 1 from power supply conductor 18. The Q output of D-type flip-flop 24 provides a reset 2 signal at its reset input and at the reset input of counter 26. A reference signal having a predetermined frequency, for example a frequency of 20 MHz, is input to input 2.
8 and the frequency is increased to 2 by the frequency multiplier circuit 30.
It is doubled and applied to the clock inputs of counters 20,26. The 4-bit count values of counters 20 and 26 are decoded by decoding circuits 32 and 34, respectively, and OR gate 3
6 is applied to the first and second inputs of 6. The output of this OR gate 36 generates a reset 3 signal at the reset input of a D-type flip-flop 38. Also, input 12
The data input signal applied to is coupled through a delay circuit 40 to the clock inputs of D-type flip-flops 38, 42 such that the data input of D-type flip-flop 38 receives a logic one from power supply conductor 18. Delay circuit 40 may be comprised of a series of inverters that delay the data input signal with respect to the reset 3 signal. The Q output of D-type flip-flop 38 is coupled to the data input of D-type flip-flop 42, and the reset input of D-type flip-flop 42 receives a logic zero from power supply conductor 44, which normally operates at VEE, such as ground potential. It is connected as much as possible. Output 46 is provided by the Q output of D-type flip-flop 42.

The primary operation of frequency discriminator circuit 10 is to provide a logic one output signal at output 46 if the frequency of the data input signal is greater than a predetermined frequency threshold. This predetermined frequency threshold is determined by the frequency of the reference signal and the predetermined count value recognized by the decoding circuits 32,34. The output signal at output 46 is a logic zero when the frequency of the data input signal is less than the frequency threshold. Therefore, a 20 MHz reference signal applied to input 28 doubles the frequency multiplier circuit 30 to 40 MHz.
Hz and is applied to the clock inputs of 4-bit counters 20, 26, incrementing the value of the counters on the rising edge of the reference signal until reset to 0 by the Reset 1 and Reset 2 signals, respectively. The frequency of the reference signal must be selectable and the counter 20,
It must match the width of 26.

A data input signal is applied to divider circuit 14 via input 12 while the reference signal is frequently incrementing counters 20 and 26. This frequency divider circuit 14 halves its frequency, and the D-type flip-flops 16 and 2
4 provides symmetrical waveforms at the clock inputs, thereby reducing timing jitter and pairing effects common in communication systems. Although this feature is not essential to the basic operation of the frequency discriminator circuit 10, it is a useful feature when two or more adjacent periods of the data input signal have different duty cycles. It is.

FIG. 2 shows a series of waveform diagrams useful in explaining the invention. The data input signal as shown in FIG. 2(A) may be asymmetric with respect to the reference signal. One phase of the output signal of the frequency divider circuit 14 is applied to the clock input of the D-type flip-flop 16, and the inverter 2
The opposite phase given to the output of D-type flip-flop 2
4 clock input, and 1/1 of the data input signal.
Generate Reset 1 and Reset 2 pulses as shown in FIGS. 2(B) and 2(C), operating at a frequency of 2. For example, the rising edge of the data input signal at time t0 in FIG. Propagates the applied logic 1 to the Q output, thereby
logic 1 for the reset 1 signal shown at time t1 of
to occur. The Reset 1 signal immediately resets the D-type flip-flop 16, but only after generating a short pulse equal to a time delay of sufficient duration by the D-type flip-flop 16 to reset the counter 20. One or more inverters (not shown) are coupled in series between the Q outputs of D-type flip-flops 16, 24 and the reset inputs to provide the required pulse widths of Reset 1 and Reset 2 to , 26 may be set to zero. However, the pulse widths of Reset 1 and Reset 2 must be smaller than the period of the data input signal to avoid losing track of the clock signals to the D-type flip-flops 16, 24. The next rising edge of the data input signal at time t2 causes a falling edge at the output of divider circuit 14 and a rising edge at the clock input of D-type flip-flop 24, thereby causing an applied signal at its D input. The output logic 1 is transferred to the Q output, generating a reset 2 pulse at time t3 as shown in FIG. 2(C). The Reset 2 signal zeroes counter 26 and resets D-type flip-flop 24 to logic zero.

The values of the counters 20 and 26 are determined by the decoding circuit 32.
, 34, respectively, to detect the occurrence of a predetermined 4-bit count value, for example, "1100". The decoding circuits 32, 34 each consist of a four-input AND gate (not shown) with an inverter coupled between the two least significant bits of the counters 20, 26 and the corresponding inputs of the AND gate. Thus, a count value of "1100" appears as "1111" at the input of the AND gate, causing its output to go to logic one. "1100"
Count values other than 0 apply one or more logic 0s to the inputs of the AND gate to generate an output logic 0. Decoding circuit 32
, 34 may consist of programmable combinatorial logic for decoding selectable counts. counter 20
, 26 is to load a predetermined count value such as ``1100'' and decrement the count to a minimum value such as ``0000'' before activating the Reset 3 signal. be.

[0014] From time t0 to t4, the frequency of the data input signal is greater than a predetermined threshold, so the reset 1 and reset 2 signals have a count value of "1100".
The counters 20, 26 can be reset before . The decoding circuits 32 and 34 each have an OR gate 36
2 (D
) generates a logic 0 for the reset 3 signal. The data input signal delayed by delay circuit 40 and applied to the clock inputs of D-type flip-flops 38 and 42 transfers a logic one at output 46 from the Q output of D-type flip-flop 38 to the Q output of D-type flip-flop 42.
Transfer to output. See FIGS. 2(E) and 2(F). In this manner, output 46 remains at a logic one while the frequency of the data input signal is greater than the predetermined frequency threshold.

Next, consider the case where the frequency of the data input signal starting at time t4 in FIG. 2 is low. The Reset 1 and Reset 2 signals are spread out with a longer data input signal period, allowing more time for the reference signal to increment the counters 20, 26 before activating the Reset 1 and Reset 2 signals. In fact, the next reset 1 signal after t4 will not appear to reset the counter 20 until the count value reaches "1100". Decoding circuit 3
The output signal of D2 becomes logic 1 at time t5, and D
The Q output of type flip-flop 38 is reset to logic zero. After propagating through delay circuit 40, the next rising edge of the data input signal at time t6 transfers a logic 0 through D-type flip-flop 42 to output 46, as shown in FIG. 2(F). The Reset 3 signal returns to logic 0 and releases the reset input of the D-type flip-flop 38 when the Reset 1 pulse zeroes the counter 20 or when the counter 20 increments to the next value. If the frequency of the data input signal is low, the time between the pulses of the reset 2 signal will also be extended and the counter 26 will again have the value "110".
0". As a result, reset 3 becomes active at time t7, and D-type flip-flop 38 is reset. D type flip flop 38
The Q output of will remain a logic 0 until the rising edge of the data input signal at time t8 once again clocks a logic 0 onto output 46. Reset 1 and Reset 2
If the output of the signal is delayed, the output signal of the decoder circuits 32, 34 continues to reset the D-type flip-flop 38. Therefore, output 46 remains at a logic zero while the frequency of the data input signal is less than a predetermined frequency threshold.

By applying the data input signal directly to the reset input of the counter 26, the frequency divider circuit 14, the D-type flip-flops 16, 24, the counter 20, and the decoding circuit 3
It is also possible to simplify the frequency discriminator circuit 10 by eliminating 2 and the OR gate 36. Although such a configuration simplifies the elements of frequency discriminator circuit 10, it sacrifices resolution and accuracy because the duty cycles of adjacent periods of the data input signal are not symmetrical. Also, by dividing the data input signal by, for example, 4 and applying a certain phase to four D-type flip-flops, such as 16 and 24, respectively, to control the reset inputs of four counters, such as 20 and 26, It is also possible to improve the resolution. Additional decoding circuitry monitors each counter value to detect one or more counters exceeding a predetermined count value. The combination of four D-type flip-flops and a counter detects drops in the frequency of the data input signal faster, thereby improving the resolution of the frequency discriminator circuit 10. Usually counters like 20, 26 and 1
As the number of D-type flip-flops such as 6,24 increases, the resolution also improves. Frequency detection resolution is counter 2
It can also be improved by widening 0 and 26 to increase the count value and increasing the frequency of the reference signal.

What has been provided is a novel frequency discriminator with high resolution for detecting the frequency of a data input signal for a predetermined frequency threshold by monitoring the count value of a frequency discriminator circuit. If the output signal is reset by the data input signal before the count value reaches the predetermined count value, the output signal remains at a first logic state, indicating that the frequency of the data input signal is greater than the predetermined frequency threshold. When the count value reaches the predetermined count value before receiving the reset signal, the output signal of the frequency discriminator circuit switches to a second logic state, thereby indicating that the frequency of the data input signal is less than the predetermined frequency threshold.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram illustrating a preferred embodiment of the invention.

FIG. 2 is a timing diagram used to explain the invention.

[Explanation of symbols]

10 Frequency discriminator circuit 12, 28 Input 14 Frequency divider circuit 16, 24, 38, 42 D-type flip-flop 18
, 44 Power supply conductor 20, 26 Counter 22 Inverter 30 Frequency multiplier 32, 34 Decoding circuit 36 OR gate 40 Delay circuit 46 Output

Claims (4)

[Claims] 1. A method of discriminating the frequency of a data input signal for a predetermined frequency threshold, comprising: generating a reset signal in response to the data input signal; adjusting a count value in response to a reference signal; resetting the count by a reset signal; and monitoring the count and providing an output signal having a first state when the count is reset before a predetermined count threshold is reached; A method comprising: providing said output signal having a second state when a numerical value reaches a predetermined counting threshold. 2. means (20, 26) for adjusting a first count in response to a reference signal and coupled to receive a first reset signal for resetting the first count; and and when the first count value is reset before reaching the predetermined count threshold value, provides an output signal having a first state, and when the first count value reaches the predetermined count threshold value, provides an output signal having a second state. A circuit characterized in that it is constituted by second means (32, 34, 36) for providing said output signal having a state. 3. A third means (16, 24) as claimed in claim 2, characterized in that it comprises third means (16, 24) coupled to receive said data input signal and provide said first reset signal in response to said data input signal. circuit. 4. An integrated circuit of a frequency discriminator for detecting the frequency of a data input signal for a predetermined frequency threshold, comprising: a first flip-flop circuit (16) having a data input, a clock input, a reset input and an output. the data input is coupled to receive a first logic signal, the clock input is coupled to receive a data input signal, and the output is coupled to the reset input of the first flip-flop circuit to receive a first reset signal. A first flip-flop circuit (16) that provides a clock input;
First counter (20) with reset input and output
wherein the clock input is coupled to receive a reference signal and adjust a first count value, and the reset input is coupled to receive the first reset signal, and the reset input is coupled to receive the first reset signal and adjust the first count value.
a first counter (20) for resetting the counted value;
an input coupled to the output of a counter, and having the first state when the first count value is equal to a predetermined count threshold, and the first count value is not equal to the predetermined count threshold. a first decoding circuit (32) having an output for providing an output signal having a second state; a second flip-flop circuit (38) having a data input, a clock input, a reset input and an output; Said first
a second flip-flop circuit (38) coupled to receive a logic signal, said clock input coupled to receive a data input signal, and said reset input coupled to receive said output signal of said first decoder circuit; ;
and a third flip-flop circuit (42) having a data input, a clock input, and an output, the data input coupled to the output of the second flip-flop circuit, and the clock input coupled to receive a data input signal. and has the first state when the output is reset before the first count value reaches the predetermined count threshold, and when the first count value reaches the predetermined count threshold;
An integrated circuit of a frequency discriminator, characterized in that it is constituted by: a third flip-flop circuit (42) that provides an output signal having the second state.