JPH04265568A - Digital recording circuit and reproducing circuit for magnetic card - Google Patents

Abstract

PURPOSE:To store data at a magnetic recording density twice as much as a normal FM system and to increase the information recording capacity on a magnetic card to twice the normal FM system by adopting an MFM system as the recording encoding system on the magnetic card. CONSTITUTION:At the time of read-in, a magnetic read-in circuit 4 makes selection between the FM system and the MFM system and encodes input data from an input amplifier 7 with a encoding system changeover command COD from a command register 4 connected to a CPU, and with a magnetic recording density changeover command FCI, changes the cycle of a synchronization clock CLK17 encodes the data and writes a data bit '0' by which leading four bits or more are magnetically inverted at a bit cell boundary consecutively. At the time of read-out, a magnetic read-out circuit 2 measures a magnetic inversion cycle Tb of leading data with the clock CLK17, uses a synchronization clock which is reset each time the magnetic inversion is detected and whose output is inverted each time the Tb/4 is counted, divides this clock into two sections to be a detection clock, conducts decoding and outputs a signal 19.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a digital recording/reproducing circuit for magnetic cards, and is used in various magnetic card systems such as toll processing machines using magnetic cards, including magnetic ticket processing machines in toll road toll collection systems. This is useful when applied to a reader/writer.

0002

[Prior Art] In conventional magnetic card systems, FM (Frequency) is used as an encoding method for digital magnetic recording.
cy Modulation) method is adopted.

FIG. 7 shows an example of recording using the FM method. As can be seen from FIG. 7, the FM method uses a data bit string of 10
In this method, the FM code string 102 is created so that the magnetization is reversed at the boundaries 101A of all bit cells in 0 and in the center 101B of the bit cells in each data bit "1". Therefore, when reading, the magnetization reversal signal 10 at the bit cell boundary
Since 4A allows bit synchronization on a bit by bit basis, it has the advantage of high self-synchronization ability. In the figure, 103 is a reproduced signal, 104 is a detection pulse, 105 is a detection clock, 106 is a decoder input, 107 is decoded data, Tb is a bit period, and Tw is a detection window width.

However, in the FM system, the maximum number of magnetization reversals MaxFRPI determined from the characteristics of the magnetic card and magnetic head
(Flux Reversals Per Inch
) to the maximum magnetic recording density MaxBPI (Bit P
Density ratio DR (Density Ra
tio) is as low as DR=BPI/FRPI=0.5, so it is not suitable for high-density magnetic recording.

Furthermore, in conventional magnetic card systems, the width (detection window width) Tw of the detection clock 105 during reading is constant for each system, and therefore only magnetic cards with a constant magnetic recording density can be read.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention uses MFM (Modif) as an encoding method.
ied Frequency Modulation
) method, the density ratio can be set to 1, and the information recording capacity of a magnetic card can be doubled compared to the FM method using the same magnetic card and magnetic head. is the first objective.

A second object of the present invention is to provide a digital recording circuit capable of recording in either the FM method or the MFM method, taking into account the coexistence with existing magnetic card systems using the FM method.

[0008]Furthermore, it is an object of the present invention to provide a digital reproducing circuit that can decode data on a magnetic card, whether it is an FM system or an MFM system, or even when the encoding system is the same but the recording density is different. is the third purpose.

[0009]

[Means for Solving the Problems] A digital recording circuit for a magnetic card according to the present invention which achieves the first object encodes input data using the MFM method, and provides continuous data bits of 4 or more bits whose magnetization is reversed at the bit cell boundary. The apparatus is characterized in that it includes an encoding circuit that outputs an MFM code string starting with "0" to a recording amplifier.

[0010] Furthermore, the digital recording circuit that achieves the second objective has a minimum bit period of Tbm recorded on a magnetic card.
When in, the period Tbmin /2 is a power of 2 that can sufficiently resolve the period 1/2 of Tbmin.
The encoder circuit is equipped with a synchronous clock generation circuit that inputs a basic clock having a value of N and generates a synchronous clock by dividing this basic clock by a power of 2 according to a command, and the encoding circuit uses this synchronous clock to generate an input signal. MF data according to command
Either the M method or the FM method is selected and encoded, and in the case of either encoding method, a code string having 4 or more consecutive data bits "0" whose magnetization is reversed at the bit cell boundary at the beginning is recorded by an amplifier. It is characterized in that it outputs to.

Furthermore, the digital reproduction circuit for a magnetic card according to the present invention which achieves the third object includes a magnetization reversal detection circuit for detecting magnetization reversal of data read from a magnetic card;
A magnetization reversal period measuring circuit that counts and measures the magnetization reversal period Tb at the beginning of data from a magnetization reversal detection signal using a basic clock, and a magnetization reversal period measuring circuit that is reset every time magnetization reversal is detected and from this point on, uses the basic clock as a measured value of the magnetization reversal period. Tb
A synchronous clock generation circuit that generates a synchronous clock whose output is inverted every 1/4 count, and a detection clock that has a detection window width of ±Tb/4 with respect to the center of the bit cell by dividing this synchronous clock twice. The present invention is characterized by comprising a detection clock generation circuit that generates the detection clock, and a decoding circuit that decodes data read from the magnetic card using the detection clock.

0012

[Operation] As shown in a recording example in FIG. 8, MFM encoding is performed using the bit cell center 101B of each data bit "1" in the data bit string 100, and the data bit "0" when data bit "0" continues. The MFM code string 108 is created so that the magnetization is reversed at each boundary 101C between the two. In FIG. 8, 103 is a reproduction signal, 104 is a detection pulse, 105 is a detection clock, 106 is a decoder input, 10
7 indicates decoded data, Tb indicates the bit period, and Tw indicates the detection window width.

Therefore, compared to the FM method, the MFM method does not necessarily provide magnetization reversal signals at all bit cell boundaries, so the self-synchronization ability is lower, but the recording density ratio is as high as 1, so it can be used like a magnetic disk device. It is used in applications where the operation of the recording medium is stable and high-density recording is required.

However, it is not used in applications such as magnetic cards, where uneven conveyance of a recording medium must be taken into account, because of its low self-synchronization ability.

[0015] In the present invention, when encoding using the MFM method,
The first 4 bits or more of the code string are consecutive data bits “0”.
”, and the magnetization is always reversed at the bit cell boundary in this leading part. Therefore, when reading an MFM code string recorded on a magnetic card according to the present invention, since magnetization reversal occurs at each bit cell boundary at the beginning of the data read from the magnetic card, the bit period can be determined by measuring this magnetization reversal period. Therefore, even if the self-synchronization ability of the MFM system itself is low, or even if there is uneven transportation of the magnetic card, it is possible to generate a detection clock with a detection window in the center of the bit cell based on the measured value. As a result, self-synchronization ability increases.

[0016] The encoding circuit converts the MFM method and F according to the command.
When encoding is performed by selecting the M method, it is possible to mix the existing FM method magnetic card system and the MFM method according to the present invention, and when encoding with either method, the magnetic card system is Four or more consecutive data bits "0" are recorded at the beginning of the data so that the magnetization is reversed at the bit cell boundary. As a result, the MFM method, F
No matter which M method is used for recording, synchronization is achieved during reading and there is no problem.

[0017] Furthermore, by using a basic clock that is sufficiently faster than the minimum bit period during encoding, and by dividing this basic clock according to the command and using it as a synchronization clock for encoding, different recordings can be performed using the same encoding method. Recording can be done with density. In this case as well, by recording 4 or more consecutive data bits "0" at the beginning of the magnetic data so that the magnetization is reversed at the bit cell boundary, synchronization can be achieved when reading regardless of the cycle of the synchronization clock during encoding. .

By recording 4 or more consecutive data bits "0" whose magnetization is reversed at the bit cell boundary as a preamble code at the beginning of the magnetic data, as described above, the data at the beginning of the magnetic data can be read as a preamble code. The magnetic reversal period Tb is set sufficiently high compared to this (for example, Tb/3
If measured using a basic clock with a period of 2), this measurement value T
b matches the bit width of the magnetic data. Therefore, by holding this measured value Tb, generating a synchronous clock with a period of 1/4 of Tb in synchronization with the detection of magnetization reversal, and generating a detection clock from this synchronous clock, it is possible to Synchronization will be reestablished, and synchronization can be correctly achieved without accumulating uneven conveyance of the magnetic card.

[0019] As a result, the capacity of the magnetization reversal period measuring circuit is set so that the count does not overflow even with the maximum magnetization reversal period handled by the system, and the counting is performed using a sufficiently resolvable basic clock even with the minimum magnetization reversal period. As long as it is set to
It is possible to decrypt data on magnetic cards.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below along with embodiments shown in the drawings. The digital magnetic recording/reproducing circuit according to this embodiment has a magnetic recording density of 100 BPI and 200 BPI according to a command when the maximum number of magnetization reversals is 400 FRPI.
, 400BP can be recorded in three ways, and 100BP
I encodes using the FM method, 200BPI allows encoding using either the FM method or the MFM method, and 400BPI encodes using the MFM method. Also, when reading, the magnetic recording density is 100BPI, 200BPI.
It is designed so that it can be read regardless of whether it is I or 400BP or whether the encoding method is FM or MFM.

FIG. 1 is a circuit diagram showing the overall configuration of a digital recording/reproducing circuit 1 for a magnetic card according to an embodiment of the present invention. This circuit 1 is connected to the bus of a microcomputer (CPU) system, and is a general-purpose DMA (Direct
In combination with a Memory Access (MemoryAccess) controller, it is configured to read and write to a magnetic card according to commands from the CPU, and to transfer data to and from the memory of the CPU system using DMA, and is aiming for standardization such as ASIC. In addition, CPU system, DM
A controller and magnetic card are not shown.

In FIG. 1, 2 is a magnetic read circuit, 3 is a magnetic write circuit, 4 is a command register, 5 is a data input latch, 6 is a data output latch, 7 is an amplifier for magnetic recording, and 8 is for magnetic reproduction. Amplifiers 9 to 19 are input/output terminals for each interface signal.

Among the interface signals, CS# is a chip select signal, IOW# is a write signal, IOR# is a read signal, D0 to D7 are data bus signals, and commands from the CPU are written to the command register 4. Of the bits in the command register 4, Q0 is a magnetic data read command MSR, Q1 is a magnetic data write command MSW, Q2 is a command FCI to switch the number of magnetization reversals at writing to 1:2, and Q3 is a command FCI to switch the number of magnetization reversals to 1:2. Commands COD for switching the encoding method during writing between the FM method and the MFM method are respectively assigned.

In this example, the maximum number of magnetization reversals is set to 400F.
When RPI is set, the recordable magnetic recording density is set to 100 BPI, 200 BPI, and 400 BPI as shown in Table 1 below, depending on the combination of each switching command FCI and COD.

[Table 1]

Furthermore, in this embodiment, when the conveyance speed of the magnetic card is 600 mm/s, the minimum bit period Tbmin of the MFM code is 25.4/(400×600)=10.
Since it is 5.8 μs, the basic clock CL in FIG.
As K, 3.3 μs that can be divided into 32 105.8 μs
A periodic clock is supplied externally, and this basic clock C
All timings are generated based on LK.

In FIG. 1, DRQ1 and DRQ2 are request signals to the DMA controller, and output latches 20,
21. Also, DAK#1, DAK#
2 is a response signal from the DMA controller. These are used for data transfer between the circuit 1 and the memory. W0 to 7 are data to the write circuit 3, WDAT is encoded data to the recording amplifier 7, RDAT is data from the reproduction amplifier 8, R0 to 3 is data decoded by the read circuit 2. It is.

Next, a concrete example of the digital reproduction, ie, magnetic readout circuit 2 will be explained with reference to FIGS. 2 to 4. FIG. 2 shows a circuit diagram, and circuits 201 to 212 constitute a digital reproduction circuit 2. FIGS. 3 and 4 show their timing charts. However, between FIG. 2, FIG. 3, and FIG. 4, the same numbers indicate corresponding circuits and their timings.

In FIG. 2, a circuit 201 detects magnetization reversal of reproduced data RDAT using a basic clock CLK and outputs an edge detection pulse. circuit 202
detects the width of the first edge and the second edge and enables the bit width counter 203. The bit width counter 203 counts the interval Tb between the first and second edges using the basic clock CLK, and in this embodiment, the maximum bit period is 42 in the case of 100 FRPI and FM recording at a card transport speed of 600 mm/s.
Since the time is 3.2 μs, if this is counted using the basic clock CLK having a cycle of 3.3 μs, a count capacity of 128 or more is required, and an 8-bit binary counter is used.

A circuit 204 is a counter for counting 1/4 of the count value Tb of the bit width counter 203 after the second edge is detected in the circuit 202, that is, after bit synchronization, and uses a 6-bit binary counter. . This 1/4 bit width counter 204 is used for each edge detection, and in the coincidence detection circuit 205, the 6 bits excluding the lower two bits of the bit width counter 203 and the 1/4 bit width counter 20
4 output 6 bits are compared and if they match (i.e. 1/4
bit width count).

The circuit 206 is a circuit that generates a synchronous clock whose output is inverted every time an edge is detected and every time a coincidence is detected by the coincidence detection circuit 205. That is, the synchronous clock is reset to a low level every time the magnetization is reversed, and is reversed every Tb/4 count.

The circuit 207 is a synchronous clock generation circuit 20
This circuit divides the frequency of the synchronization clock generated in step 6 by two to generate a detection clock that serves as a detection window during decoding. That is, the detection clock is at a high level for ±1/4 Tb with respect to the center of each bit cell, and this is the detection window width.

The circuit 208 is a decoder that decodes the reproduced data RDAT by sampling the detection clock every time an edge is detected. That is, if the detection clock is at a high level at the time of edge detection, the data bit is set to "1".

The circuit 209 is a detection clock generation circuit 20
This is a 4-bit shift register that shifts the output of the decoder 208 as input data every time the detection clock from 7 falls, and outputs decoded data R0 to R3.

The circuit 210 includes a 4-bit shift register 2
When the output of 09 becomes all "1", that is, consecutive 4
Bit data "1" is detected as a start code for digit synchronization, data transfer latch 211 is set, and 4-bit counter 212 is enabled.

The 4-bit counter 212 repeatedly counts 0, 1, 2, 3, 0, 1, etc. every time the detection clock rises, and when this output is 0, that is, every 4 bits are synchronized with the digits. , the DMA request signal R with the detection clock width is
DRQ is generated, outputs R0 to 3 of the 4-bit shift register 209 are latched into the data output latch 6 in FIG.
Transfer to memory using DMA. Data is transferred to the memory in units of bytes (8 bits), and the lower 4 bits are valid digits.

Note that among the outputs of the 1/4 bit width counter 204 in the timing charts of FIGS. 3 and 4, C
If the edge is detected first, the 1/4 bit width counter 204 will be reset, so that the 1/4 bit width counter 204 will not be generated.

Next, a specific example of the digital recording, ie, magnetic writing circuit 3 will be explained with reference to FIGS. 5 and 6. FIG. 5 shows a circuit diagram, and circuits 301 to 314 constitute the digital recording circuit 3. FIG. 6 shows a timing chart. However, the same numbers between FIG. 5 and FIG. 6 indicate the circuits of the corresponding parts and their timings.

In FIG. 5, a circuit 301 is a frequency dividing circuit that divides the basic clock CLK with a period of 3.3 μs by 16 times, 32 times, and 64 times, and has a card transport speed of 600 times.
Command of magnetization reversal in mm/s 200FRPI (FC
I=“0”), 400FRPI (FCI=“1”),
Recording encoding method command FM (COD="0"), MFM
(COD="1"), the magnetic recording density determined by these is 400BPI, 200BPI, 100BP
52.8 μs, 1 corresponding to 1/2 of each bit period of I
A clock with a cycle of 05.6 μs and 211.2 μs is generated.

The circuit 302 is a gate that selects a clock of a corresponding period from the frequency dividing circuit 301 according to a combination of each command FCI and COD, and outputs it as a synchronized clock WCLK.

The circuit 303 divides the frequency of the synchronized clock WCLK from the gate circuit 302 into a shift clock S.
This is a D type latch that generates CLK.

The circuit 304 synchronizes the magnetic write command MSW set from the CPU with the shift clock SCLK from the latch 303 to enable the 4-bit counter 305, and also synchronizes the magnetic write command MSW set from the CPU with the shift clock SCLK from the latch 303 to enable the 4-bit counter 305. This is a 5-bit shift register that generates a write data enable signal WENB in synchronization with the falling edge of a synchronous clock.

The 4-bit counter 305 has 0, 1, 2,
3, 0, 1... is repeatedly counted, and when this output is 0, that is, every 4 bits, a DMA request signal WDRQ having the width of the shift clock SCLK is generated through gates 306 and 307, and the data input latch shown in FIG. 5 are taken into the 4-bit shift register 308 and IBG latch 311 in FIG.

The 4-bit shift register 308 shifts out 4-bit data W0-3 from the LSB of the outputs W0-7 of the data input latch 5 in synchronization with the shift clock SCLK.

The circuit 309 is a 4-bit shift register 3
This is a D-type latch for delaying the shift outputs W0 to W3 of No. 08 by one stage, and its purpose is to detect bit cell boundaries to invert magnetization at bit cell boundaries where data bits "0" continue during recording in the MFM method.

The circuit 310 is a gate for switching the encoding method according to the command COD by controlling the clock enable signal CE of the encoder 313.

If the clock is enabled, the encoder 313 inverts its output at the falling edge of the synchronous clock, performs encoding using the FM method or the MFM method according to the output of the gate circuit 310, and outputs encoded data WDAT. Data from memory is transferred in bytes, and the lower 4 bits W
0 to 3 are valid digits. Note that the most significant bit W7
is latched by the IBG latch 311 and when it is “1”, the gate 312 outputs the signal to the encoder 3 for 4 bit cycles.
This is used to inhibit the clock enable of No. 13 and prevent output inversion, that is, to perform DC magnetization recording between data blocks.

In the timing chart of FIG. 6, data W0 to W7 received in response to the DMA request (WDRQ) issued by the gate 307 are taken into the shift register 308 with a delay of 4 bit periods, that is, the timing of the next DMA request. I try to keep it that way.

Furthermore, in FIG. 6, data in the FM system (FM output) outputted by the encoder 306 and data in the MFM system (MFM output) are shown when the magnetic recording density is the same.

[0049]

Effects of the Invention According to the present invention, by adopting the MFM method as the recording and encoding method of the magnetic card, the conventional FM
Since data can be recorded at twice the magnetic recording density compared to conventional methods, the information recording capacity of the magnetic card can be doubled.

In this case, regarding bit synchronization, which is a problem in the MFM method, synchronization can be reestablished at the time of detecting each magnetization reversal at the boundary of a bit cell where a data bit "0" continues and at the center of a bit cell where a data bit "1" is present. This improved synchronization.

[0051] Also, according to the command, the encoding method can be changed to MFM or F
M can be selected, and the synchronization clock during encoding can also be changed, so even when increasing the magnetic recording capacity of a magnetic card system that is already in operation, the circuit of the present invention can be used to increase the magnetic recording capacity during the equipment replacement period. This allows for mixed use with other machines. For example, if an existing machine reads a magnetic card recorded using the FM method at 100 BPI, the circuit of the present invention can read it at 400 BPI.
It is possible to re-record to I, MFM format, or vice versa.

Furthermore, according to the present invention, if the head of the data on the magnetic card is 4 or more consecutive data bits "0" that are reversed at the bit cell boundary, regardless of whether it is an FM system or an MFM system, Even if the magnetic recording density is different (for example, 100 BPI to 400 BPI), magnetic cards can be read. Therefore, the circuit of the present invention can be standardized, and the range of application can be expanded by ASIC, etc.
You can expect a lot of cost reduction.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall circuit of the present invention.

FIG. 2 is a diagram showing a magnetic readout circuit (reproduction).

FIG. 3 is a flowchart of the magnetic readout circuit.

FIG. 4 is a flowchart of the magnetic readout circuit.

FIG. 5 is a diagram showing a magnetic write circuit (recording).

FIG. 6 is a timing chart of the magnetic write circuit.

FIG. 7 is a timing chart showing an example of recording using the FM method.

FIG. 8 is a timing chart showing an example of recording using the MFM method.

[Explanation of symbols]

1 Digital recording/reproduction circuit 2 Magnetic readout circuit 3 Magnetic write circuit 4 Command register 5 Data input latch 6 Data output latch 7 Recording amplifier 8 Reproduction amplifier 201 Edge detection circuit 202 Edge width detection circuit 203 Bit width detection circuit 204 1/4 Bit width counter 205 Coincidence detection circuit 206 Synchronous clock generation circuit 207 Detection clock generation circuit 208 Decoder 209 4-bit shift register 210 Start code detection circuit 211 Data transfer latch 212 4-bit counter 301 Frequency divider circuit 302 Synchronous clock selection gate 303 Shift clock Generation latch 304 5-bit shift register 305 4-bit counters 306, 307 4-bit shift register 309
Bit cell boundary detection latch 310 Encoding method switching gate 311 IBG latch 312 DC magnetization recording gate 313 Encoder

Claims (3)

[Claims] [Claim 1] Encoding input data using an MFM method,
A digital recording circuit for a magnetic card, comprising an encoding circuit that outputs an MFM code string having four or more consecutive data bits "0" at the head whose magnetization is reversed at a bit cell boundary to a recording amplifier. [Claim 2] When the minimum bit period recorded on a magnetic card is Tbmin, the period Tbm is a power of 2 that can sufficiently resolve a period of 1/2 of Tbmin.
The encoder circuit is provided with a synchronous clock generation circuit that inputs a basic clock having in /2N and generates a synchronous clock by dividing the frequency of this basic clock by a power of 2 according to a command, and the encoding circuit converts this synchronous clock into a synchronous clock. The input data is encoded by selecting either the MFM method or the FM method according to the command, and in either encoding method, continuous data bits of 4 or more bits whose magnetization is reversed at the bit cell boundary.
2. The digital recording circuit for a magnetic card according to claim 1, wherein the digital recording circuit for a magnetic card outputs a code string starting with "0" to a recording amplifier. 3. A magnetization reversal detection circuit that detects magnetization reversal of data read from a magnetic card, and a magnetization reversal period measuring circuit that counts and measures the magnetization reversal period Tb at the beginning of data using a basic clock from a magnetization reversal detection signal. and,
A synchronous clock generation circuit that generates a synchronous clock that is reset every time magnetization reversal is detected and whose output is inverted every time the basic clock is counted from this point to 1/4 of the measured value Tb of the magnetization reversal period, and a synchronous clock that is doubled. a detection clock generation circuit that generates a detection clock having a detection window width of ±Tb/4 with respect to the center of the bit cell; and a decoding circuit that decodes data read from a magnetic card using the detection clock. A digital playback circuit for a magnetic card, comprising: