JPH04262437A - Cache data replacer in cache memory - Google Patents

Abstract

PURPOSE:To reduce queuing time of a processor and to improve the throughput of the processor system by reducing the number of times of data transfer between a cache memory and the main memory. CONSTITUTION:In a cache data replacer for cache memory where write action is carried out for a cache memory divided into a plurality of blocks, where writing of cache data in a block for which the writing was carried out is carried out for the main memory when replacing cache data, replace memories 24 and 25 for storing history data for block are provided. The memory 24 stores therein data indicating an update history, and in memory 25 data indicating a replace history is stored. When cache data in the cache memory is changed, a bit corresponding to a block where the history data was changed is set at '1', and when replacing cache data, cache data in a block whose corresponding bit of the history data is '0' is replaced prior to others.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory replacement device for operating a processor at high speed, and more particularly to a cache data replacement device in a write-back type N (N≧2) way set associative cache memory.

0002

[Background Art] In order to make a processor operate at high speed,
It is common practice to arrange a cache memory, which has a small capacity but can operate at high speed, between a processor and a main storage device. The storage area of the main storage device is divided into a plurality of blocks, and some of the storage data of the plurality of blocks is loaded into the cache memory. The processor first accesses the cache memory, and if data at the accessed address exists on the cache memory, that is, when there is a cache hit, the processor directly accesses the data on the cache memory and reads or writes it. . Furthermore, when there is no data at the corresponding address on the cache memory, that is, when a cache miss occurs, a new block is read from the main memory and replaced with any old block already on the cache memory. This replacement is generally called a replacement. At this time, the method for determining which block to replace is called a replacement algorithm. This replacement algorithm uses the LRU (Least
FIFO (First In First O) method, which targets the block most recently read into the cache memory
t) method etc. are known.

[0003]Also, data on the cache memory may be updated by write access from the processor, but when replacing, all data in a certain block on the cache memory is written to the main memory at once. The method is called a write-back method. Note that write-back
) method is sometimes called a copy-back method. When the processor accesses the cache memory that can operate at high speed, the overall processing speed becomes faster.

[0004] In conventional cache memory, the above-mentioned LRU method and FI
The FO method is used, but these methods only focus on the frequency of data use and the order in which it was input, and check whether or not the data in the block to be replaced has changed, that is,
Replacement was performed by write-back regardless of whether writing was performed or not.

[0005]

[Problems to be Solved by the Invention] However, when data in the cache memory is unconditionally written back to the main memory during replacement, it takes time to write to the main memory, so the wait time of the processor increases. There was a problem that the system throughput decreased due to the increase in the amount of data.

In view of the above problem, the present invention reduces the number of times data is transferred between the cache memory and the main memory by reducing the number of writes back from a cache memory block in which data has been changed to the main memory. reduce,
The purpose of this is to reduce processor latency and improve system throughput.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides that a write operation is performed on a cache memory divided into a plurality of blocks, and the cache data of the written block is transferred to a main storage device. A cache data replacement device for a cache memory in which writing is performed at the time of replacement is provided with a history data memory for storing history data consisting of a plurality of bits corresponding to each block, and in an initial state, the bits of the history data are stored in a first memory. state, and when the cache data in the cache memory is changed, a bit corresponding to the changed block of the history data is set to a second state, and when the cache data is replaced, the history data The cache data of the block whose bit is set to the first state is preferentially replaced.

[0008]

According to the present invention, in the initial state, the bits of the history data stored in the history data memory are set to, for example, "0". Then, when the cache data in the cache memory is changed, the corresponding bit becomes
For example, it is set to "1". When replacing cache data, for example, cache data in blocks that are set to "0", that is, blocks that have not been changed, are preferentially replaced. The data in the block whose contents have been changed by the processor will eventually need to be replaced, but replacement requires writing back from the cache memory to the main memory, and this write back takes time. It takes. Therefore, in the present invention, by preferentially replacing blocks whose cache data has not been changed, that is, blocks that do not require write back, the rate at which blocks that require write back are evicted from the cache memory is reduced. . This reduces the number of write-backs and improves system throughput.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, features of the present invention will be specifically explained based on embodiments with reference to the drawings.

FIG. 1 shows a schematic diagram of a cache memory to which the present invention is applied. In this embodiment, a 4-way set associative cache memory will be described as an example. The set associative method is a method for determining where on the cache memory the data on the main storage device should be associated, and the storage area of the cache memory and main storage device is divided into four blocks. The correspondence is made in units of blocks. Regarding the set associative method itself, for example,
Muraki, Kuroda, Shindo, "Cache Memory Methods and Trade-offs," Complete Guide to 32-Bit Microprocessors, Nikkei McGraw-Hill Publishing, pp. 242-265. In the set associative system, the cache memory is composed of a matrix with E rows and S columns, each of which has blocks as elements. E is called the number of elements, S is called the number of sets,
A method in which the number of elements is N is called an N-way set associative method. Note that E, S, and N are integers of 1 or more.

In FIG. 1, numeral 1 is a processor address section schematically showing real address information from a processor (not shown), and this processor address section 1 includes a tag address 2, a set address 3, and a word address 4. ing. The set address 3 from the processor address section 1 is supplied to the replacement circuit 5, the tag memory 6, the valid memory 7, and the memory main body 8a of the data memory 8. Further, the word address 4 is supplied to the selector 8b of the data memory 8.

The tag address 2 from the processor address unit 1 is compared with the tag data 13 from the tag memory 6 in a comparator 9, and when the two match, a cache hit signal 10 is output. This cache hit signal 10 is supplied to the sequencer 11, and the sequencer 1
1 outputs a data selection signal 12. This data selection signal 12 is supplied to the selector 8c of the data memory 8, and target cache data 14 is output from the data memory 8 based on the set address 3 and word address 4.

In the cache memory described above, when a cache miss occurs, the replacement circuit 5 reads a new block from the main memory and replaces it with any old block already on the cache memory. Hereinafter, the replacement circuit 5 will be explained in detail with reference to FIG. 2.

The replace circuit 5 includes an update history data replace memory 24 that stores blocks accessed by the set address 3 from the processor address section 1 shown in FIG. 1 and whose data has been updated, and a replace memory 24 that stores the replaced blocks. Historical data replacement memory 2
5. Update history data 26 from the replace memory 24 and replace history data 27 from the replace memory 25
It is comprised of a replacement determining circuit 28, etc., which determines a block to be replaced. Replace data 29 is output from the replace determination circuit 28, and this replace data 29 is supplied as data to the replace memories 24 and 25, as well as to the tag memory 6 and valid memory 7.

[0015] Also, a replace signal (indicated by RP in the figure) 30, a cache hit signal (indicated by C-H in the figure)
31 and a processor write signal (indicated by P-wr in the figure) 21 through an AND circuit 22 to replace the memory 24.
Replace update signal for (indicated by R-wr in the figure)
33 is generated. Also, AND from the replace signal 30 and the cache miss signal (indicated by C-M in the figure) 32.
The circuit 23 generates a replace update signal (indicated by R-wr in the figure) 34 for the replace memory 25.

The processor write signal 21 is output from the processor when the processor writes, and the replace signal 30 is output from the sequencer when cache data needs to be replaced (when there is a cache miss and the cache memory is full of valid data). It is output from 11. Further, the cache hit signal 31 is output from the sequencer 11 when there is a cache hit (when the cache hit signal 10 becomes valid), and the cache miss signal 32 is output from the sequencer 11 when there is a cache miss (when the cache hit signal 10 becomes valid).
output from the sequencer 11).

The above replace update signals 33 and 34 are as follows:
This signal determines the conditions for writing data into the replacement memories 24 and 25. Note that the bit width of the update history data 26, replace history data 27, and replace data 29 is the same as the number of sets, that is, the number of ways, and 2
If it is a way, it is 2 bits, and if it is 4 ways, it is 4 bits. In the embodiment, a 4-way case is explained.

The replace memory 24 for storing the data update block is updated when the cache memory has a write hit, and the replace memory 25 for storing the replace block is updated when a data block is replaced due to a cache miss. Ru.

The replacement operation in the above-mentioned 4-way set associative cache memory will be explained below for each case.

(1) In case of lead hit.

This means that the type of access from the processor is read, and that the data at the accessed address is on the cache memory. In this case, the data blocks in the cache memory are not updated or replaced, and the replacement memories 24 and 25 are not updated, so the replacement determination circuit 28 does not operate. Note that the replacement determination circuit 28 becomes operable in the case of a read miss, write hit, or write miss, which will be described below.

(2) In case of read error.

This means that the type of access from the processor is read, and that the data at the accessed address is not on the cache memory. In this case, since it is necessary to transfer the missed data from the main memory to the cache memory, the replacement determining circuit 28 selects one of the four sets specified by the set address 3 as the transfer destination block in the cache memory. decide. Assume now that the history data of the set accessed by the set address 3 of the processor address section 1 is in the state shown by the update history data 26 and the replacement history data 27 in FIG. 3(a). In addition, ■～■ in the diagram
indicates the number of each block. In FIG. 3(a), “0
The update history data 26 of "010" indicates that the data of block ■ has been changed in the past.
The replacement history data 27 of "0001" indicates that block (2) has been replaced. The replacement determining circuit 28 determines the location of the block to be replaced based on these two pieces of data. In this example, since the flags of block ■ and block ■ are set, block ■ or block ■ can be selected as the replacement block, but in the example of FIG.
Block ■ is selected as indicated by the replacement data 29 of ``100''. Note that it is optional to select either block ■ or block ■, and for example, it may be determined randomly or in ascending order of block numbers. .The replacement data 29 is input to the sequencer 11,
executes replacement of the cache data of the corresponding block based on the replacement data 29.

When the replacement of block (2) is completed, the replace signal 30 and the cache miss signal 32 are asserted, and the contents of the replace memory 25 are changed to those shown in FIG. 3(b).
) will be updated as follows. That is, the bit corresponding to block (2) of the replacement history data 27 becomes "1".

(3) In the case of a light hit.

This means that the type of access from the processor is write, and that the data at the accessed address is on the cache memory. Here, it is assumed that block (2) of the set specified by set address 3 has been write-hit (see FIG. 4). Due to the set address 3, the replace signal 30, cache hit signal 31, and processor write signal 21 are asserted, and the contents of the replace memory 24 are updated as shown in the update history data 26 of FIG. 4(b).

(4) In case of write error.

As in the case of a read miss, the contents of the replace memory 25 are changed as shown in FIG. 5(a) so that the bit corresponding to block ■ of the replace history data 27 becomes "1".
The information is updated as shown in FIG. 5(b). Further, history data 26 and 27 are output from the replacement memories 24 and 25 (see FIG. 4(a)). The replace determining circuit 28 outputs replace data 29 based on these two data in the same manner as in the case of a read error.

[0029] Each signal 21, 30, 3 in each of the above cases
The level relationship between numbers 1 and 32 is as follows.

[0030]
Read Read Write Write
Hit Miss Hit Miss processor write signal 21 0 0
1 1 replace signal 30 0
1 0 1 cache hit signal 31 1
0 1 0
Cache miss signal 32
0 1 0
1 (5) When the history data of any block is "1".

As replacements and data updates are performed, which block's history data (update history data 26,
The replacement history data 27) may also become "1" (see FIG. 6(a)). At this time, the replacement determination circuit 2
8 is at the end of data replacement or after data update,
Output “0000” to the replacement data 29. At the same time as the output, the clear signal 35 is asserted, and "0" is written in the replacement memories 24 and 25, returning to the initial state (see FIG. 6(b)).

In the explanation of the above embodiment, a block in which neither of the replace memories 24 and 25 is "1" is replaced, but this condition can also be changed as follows.

Now, the replacement memories 24 and 25 are shown in FIG.
Assume that the situation is as shown in (a). First, at least one of the replace memories 24 and 25 whose output is "0" is replaced. In the example of FIG. 7(a), blocks ■～■
is subject to replacement. The bit of the replaced block in the replacement memory 25 is changed to "1". Figure 7
As shown in (b), when all the outputs of the replace memory 25 become "1", next, the replace memory 24 outputs "1".
0" and the replace memory 25 is "1". In the example of FIG. Then, as shown in FIG. 7(c), all outputs of the replace memory 24 are "1".
When this happens, the replacement memories 24 and 25 are initialized to "0" as shown in FIG. 7(d).

Furthermore, in a write hit, only the replace memory 25 is updated, similar to the previously described embodiment. In this way, the replacement order is determined by weighting the update of the replace memory by writing by the processor and the update of the replace memory by replacing. In addition,
In the example shown in FIG. 7, weighting is performed at write:replace=2:1. By weighting in this way, it is possible to change the order of replacement,
Performance can be improved depending on the type of application program.

In the embodiment shown in FIG. 2, the update history data 26 and the replacement history data 27 are stored in separate replacement memories 24 and 25, but as shown in FIG. Replace memory 3
7 can also be integrated. Incidentally, members and the like corresponding to those in the embodiment shown in FIG. 2 are given the same reference numerals, and explanations thereof will be omitted.

In the embodiment shown in FIG. 8, the replace update signals 33 and 34 are supplied to a replace memory 37 via an OR circuit 36. In addition, the replacement memory 37
The tag address 2 is supplied as an address signal from the processor address section 1 shown in FIG. 28.

[0037] In the above embodiment, the bit of the history data in the initial state is set to "0", and the bit of the updated or replaced block is set to "1". “0” may be inverted.

[0038]

As described above, in the present invention, when the cache data in the cache memory is changed, the bit corresponding to the changed block of history data is set to "1", for example, When replacing cache data, for example, by preferentially replacing cache data in blocks that are set to "0", the ratio of data in blocks modified by the processor to be evicted from the cache memory will be lowered. . This reduces the number of writebacks, reduces processor latency, and increases system throughput.

[Brief explanation of the drawing]

FIG. 1 shows a schematic diagram of a cache memory to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a replacement circuit used in the cache memory of FIG. 1;

FIG. 3 is a diagram showing the transition of data in a replacement memory when a read miss occurs.

FIG. 4 is a diagram showing the transition of data in a replace memory when a write hit occurs.

FIG. 5 is a diagram showing the transition of data in a replacement memory when a write error occurs.

FIG. 6 is a data transition diagram of the replacement memory when all data is “1”.

FIG. 7 is a data transition diagram of a replacement memory when weighted replacement is performed.

FIG. 8 is a block diagram showing another configuration example of a replacement circuit.

[Explanation of symbols]

1 Processor address section 2 Tag address 3 Set address 4 Word address 5 Replace circuit 6 Tag memory 7 Valid memory 8 Data memory 9 Comparator 10 Cache hit signal 11 Sequencer 12 Data selection signal 13 Tag data 14 Cache data 21 Processor write signals 22, 23 AND circuit 24 Replace memory for update history data 25 Replace memory for replace history data 26 Update history data 27 Replace history data 28 Replace decision circuit 29 Replace data 30 Replace signal 31 Cache hit signal 32 Cache miss signals 33, 34 Replace update signal 35 Clear Signal 36 OR circuit 37 Replace memory 38 Replace history data

Claims (1)

[Claims] 1. A cache data replacement device for a cache memory in which a write operation is performed on a cache memory divided into a plurality of blocks, and cache data of the written block is written to a main storage device at the time of replacement. A history data memory is provided for storing history data consisting of a plurality of bits corresponding to each block, and in an initial state, the bits of the history data are set to a first state, and the cache data in the cache memory is changed. when the bit corresponding to the changed block of the historical data is set to a second state, and when replacing the cache data, the cache of the block whose bit of the historical data is set to the first state; A cache data replacement device in a cache memory, which replaces data preferentially.