JPH04261226A - Data compressor - Google Patents

Abstract

PURPOSE:To reduce the time required for data compression considerably. CONSTITUTION:A map section 1 is provided with a register latching a value representing the order of codes for each kind of the inputted codes, that is, the sequential number. A comparison section 2 detects whether or not a code string is the same as the code string already inputted based on the sequential number of the code latched in the register. Then a generating section 3 detects whether or not the same code strings are consecutive based on the sequential number and outputs a prescribed compression code when the consecution of the same code strings is detected. An output section 4 applies synchronization processing to the code string after data compression as required and outputs the result as an output data.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a data compression device.
In particular, the present invention relates to a device that effectively compresses data when the same code string is consecutive.

0002

2. Description of the Related Art A conventional data compression device of this type is shown in FIG. This device receives a string of codes representing one character per byte as input, and when the same code string is input consecutively, it outputs a predetermined compression code that represents the repetition of the string. be. The reference area register 501 and the comparison area register 502 are both shift registers that shift codes in 1-byte units, and the code string to be data compressed is input to the register 501 as input data, shifted 1 byte at a time, and then stored in the register. 501 to register 50
Move to 2. Comparison circuit 503 includes registers 501 and 5
This is to sequentially compare the codes held in 02 one by one (one byte at a time) and detect whether the same character string is consecutive. The control circuit 504 controls each of the above sections and outputs a compressed code based on the detection result of the comparison circuit 503.

To explain the operation, the control circuit 504 controls the comparison circuit 503 to first search the register 502 for the same code as the first code of the register 501, and if the same code is found, the registers after that code are searched for. 50
The code string held in the register 501 is compared one code at a time with the code string from the beginning of the register 501. And register 50
If all the codes up to the code immediately preceding the first code found in step 2 match, it is determined that the same code string is continuous, and a compressed code is output.

[0004] If the same code as the first code in register 501 is not held in register 502, the character string is shifted by one code to the register 502 side, and the new first code in register 501 is stored in register 502. Perform the comparison process described above. Figure 6 shows an example of such a case.
The first character “a” in register 501 is the first character “a” in register 502.
Since the character string is not held in the register 502, the character string is shifted by one character to the register 502 side.

[0005] Furthermore, even if the same code as the first code in register 501 is held in register 502, if a mismatch occurs in the subsequent comparison process, the character string is shifted by one code to register 502. , the above-described comparison process is performed on the code that has newly become the head of the register 501. Figure 7
shows an example of such a case, where the first character "a" of register 501 is held in register 502, but when comparing the fourth character, that is, e and d,
Since there will be a mismatch, the character string will be stored in register 50 in this case as well.
Shift one character to the 2nd side.

[0006] By repeating such operations, consecutive identical character strings are detected, and data compression is performed by representing the subsequent character strings with compression codes.

[0007]

However, in such a conventional data compression device, two registers 501 and 502
Since the code strings are input into the register 502 and the codes are compared, time is required to fill the register with the codes.Furthermore, since the register 502 is used to search for codes, it also takes time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data compression device that solves these problems and significantly reduces the time required for data compression.

[0009]

[Means for Solving the Problems] The present invention provides a data compression device that outputs a predetermined compression code when the same code string is continuously input, and a counter that increases by one each time a code is input. , a plurality of corresponding registers each corresponding to the type of code and holding the count value of the counter when a code of the corresponding type is input, and a plurality of corresponding registers corresponding to the type of the input code held. A match detection signal is output when the current value and the value obtained by adding 1 to the value held in the corresponding register corresponding to the previously input code type, and when they do not match. a comparison means for outputting a mismatch detection signal; a start register for holding a counted value of the counter when the comparison means outputs the mismatch detection signal; the code is input;
When the comparison means outputs the coincidence detection signal, a value obtained by adding 2 to the value held in the corresponding register corresponding to the previously input code and a value held in the start register. and compressed code generating means that outputs the compressed code when the values match.

0010

[Example] Next, an example of the present invention will be described. Figure 1
An example of a data compression device according to the present invention is shown in FIG. This device accepts a string of codes representing one character per byte as input, and if the same code string is input consecutively, it inserts a predetermined compression code that represents the repetition of the string. be. Then, a map unit 1 equipped with a register that holds a value representing the order of codes input as input data, that is, an order value, detects a code string that is the same as a code string that has already been input based on the order value of the codes. A comparison unit 2 detects that the code string is continuous and inserts a predetermined compression code into the code string, and a generation unit 3 inserts a predetermined compressed code into the code string, and performs synchronization processing etc. on the code string after data compression as necessary. and an output section 4 that outputs the data as output data.

The map section 1 has a configuration as shown in FIG. When input port 101 receives one code as input data, it notifies counter 104 of this fact, and also sends the input code to decoder 102 and selector 10.
Output to 3. The counter 104 is incremented by 1 every time there is a notification from the input port 101, and its initial value is 0, and after counting up to 511, it starts counting from 1 for the next input notification. The corresponding register group 105 consists of a plurality of registers each corresponding to the type of code, and each register has 9 bits and has an initial value of 0. When the decoder 102 receives a code from the input port 101, it selects and drives the register of the corresponding register group 105 that corresponds to the code. Then, select the value held by selector 1
03, and after the selection operation of the selector 103, which will be described later, the counted value of the counter 104 is taken in and held. The valid register 106 is a 9-bit register that holds the order value from the S register 201 of the comparator 2, which will be described later. The selector 103 outputs the code from the input port 101 and the count value of the counter 104 to the generation unit 3 when the value output by the corresponding register group 105 is greater than or equal to the value of the valid register and less than the count value of the counter, It also outputs the value from the corresponding register to the comparator 2. On the other hand, when the value output by the corresponding register group 105 is outside the above range, the code from the input port 101 is directly output to the output unit 4.

The comparison section 2 has a configuration as shown in FIG. The S register 201 is a 9-bit register,
When the order value is sent from the selector 103, it is held and sent to the comparator 204 and the valid register 10 of the map unit 1.
Output to 6. Adder 202 adds 1 to the order value output by S register 201 and outputs the result. The T register 203 is a 9-bit register, holds the value output by the adder 202, and outputs it to the comparator 204 and a comparator 302 of the generation unit 3, which will be described later. Comparator 204 compares the values held by registers 201 and 203, and outputs 0 when they match, and outputs 1 when they do not match to control circuit 303 of generation unit 3, which will be described later.

The generating section 3 has a configuration as shown in FIG. When the comparator 204 outputs 1, the start register 301 holds the count value of the counter 104 at that time, that is, the order value of the sign, under the control of the control circuit 303 described later. Note that the initial value of the start register 301 is 1. Comparator 302 compares the order value held by start register 301 and the value held by T register 203 plus 1, and outputs 0 if they match, and 1 if they do not match. The 8-bit register 304 is a register for holding the code from the selector 103. The buffer 305 receives the code from the selector 103 through the register 304, and stores the same consecutive code string,
Or keep that candidate.

The control circuit 303 stores the sign from the selector 103 in the register 304 while the comparator 204 outputs 0.
The data is taken into the buffer 305 and held there. Further, when the comparator 204 outputs 1, the selector 10
The code from 3 is stored in the register 304 before the buffer 305.
I'll keep it to that. The value held by the start register 301 and
When the value obtained by adding 1 to the value from the T register 203 is equal, that is, when the comparator 302 outputs 0, it means that the same consecutive character string has been searched, and the control circuit 30
3 outputs a predetermined compression code to the output section 4. Thereafter, the control circuit 303 sends the value of the start register 301 to the valid register 106, stores a value obtained by adding 1 to the value of the counter in the start register, and initializes the buffer 305. The control circuit 303 determines that when the T register 203 is not in its initial state and its value is other than 0, and the comparator 204 outputs 1, the code string held by the buffer 305 is not a repeated code string. So buffer 305
The codes within are sequentially output to the output unit 4, and then the last code retained in the register 304 is output to the buffer 305.
be stored in And the start register has a counter 10.
The count value of 4 is held, and the effective register is S register 2.
The value of 01 is held. Even if the comparator 204 outputs 1, if the value from the T register 203 is 0, the count value of the counter 104 is stored in the start register 301, and then the process moves to input the next code.

Next, the operation will be explained using a specific character string as an example. First, in the initial state, the count value of the counter 104, the values held by the corresponding register group 105 and the T register 203 are all 0, and the values held by the valid register 106 and the start register 301 are 1. The initial values for registers 201, 304 and buffer 305 are arbitrary.

"abcdefabcabc" as a character string
..." is input. When the sign of the first character "a" is input, the input port 101 notifies the counter 104 of this fact, and as a result, the counter 104 increases its count value by 1. , the order value of the first character “a” is 1
Output. On the other hand, the input port 101 supplies the above code to the decoder 102, and the decoder 102 sends the corresponding register group 10 corresponding to the code, that is, corresponding to the character "a"
5 corresponding registers are driven. All registers in the corresponding register group 105 are initialized and hold 0, so
The driven register outputs 0 to the selector 103. Since the value is outside the range of greater than or equal to the value held by the valid register 106 and less than the counted value of the counter 104, the selector 103 directly outputs the character "a" to the output unit 4. Thereafter, the driven corresponding register holds the count value of the counter 104, that is, the order value 1 of the first character "a". On the other hand, when the output unit 4 receives the character "a", it performs a synchronization process and outputs it. The map section 1 and the output section 4 operate in the same manner for each character up to the sixth character "f", and the corresponding register for each character holds its order value, and each character is output from the output section 4. Ru.

Next, when the seventh character "a" is input, the counter 104 outputs 7 as the count value, and the register corresponding to the character "a" in the corresponding register group 105 is driven again. . In this case, the value of the driven register is the order value 1 of the first character "a", and the value of the valid register 106 is in the range of 1 or more and less than the count value of the counter 7, so The selector 103 outputs the character "a" and the count value 7 of the counter 104 to the generating section 3, and outputs the value of the register corresponding to the character "a" to the comparing section 2.

In the comparator 2, the value 1 of the register corresponding to the character "a" from the selector 103 is held in the S register 201, and the comparator 204 stores the value 1 of the S register 201 and
At this time, it is compared with the value 0 (initial value) held in the T register 203, and since they do not match, 1 is output to the generation unit 3. After that, the T register 203 is added to the adder 202.
The value 2 obtained by adding 1 to the value 1 of the S register 201 output by the S register 201 is held. This value is the ordinal value of the second character "b".

In the generating section 3, the control circuit 303 controls the comparator 2.
Since the output value 1 from 04 is received, the count value 7 of the counter 104 output by the selector 103 at this time is held in the start register 301. In other words, since the comparator 204 outputs 1, there is a possibility that the character "a" from the map unit 1 is the first character of a continuous character string, and the start register 301 holds its order value 7. . The control circuit 303 also causes the character “a” from the selector 103 of the map section 1 to be stored in the register 304.

Next, when the eighth character "b" is input, the counter 104 outputs 8 as the count value, and the register corresponding to the character "b" in the corresponding register group 105 is driven again. . In this case, the value of the driven register is the order value 2 of the second character "b", and the value of the valid register 106 is in the range of 1 or more and less than the count value of the counter 8, so The selector 103 outputs the character "b" and the count value 8 of the counter 104 to the generating section 3, and outputs the value 2 of the register corresponding to the character "b" to the comparing section 2.

In the comparator 2, the value 2 of the register corresponding to the character "b" from the selector 103 is held in the S register 201, and the comparator 204 stores the value 2 of the S register 201 and
At this time, it is compared with the value 2 held in the T register 203, and in this case, since they match, 0 is output to the generation unit 3. After that, the T register 203 is added to the adder 202.
The S register 201 outputs the value 2 plus 1, which is 3. This value is the ordinal value of the third character "c".

In the generation section 3, the control circuit 303 controls the comparator 2.
Since we receive the output value 0 from 04, this 8th character may be a character that forms a continuous string, so we leave the start register 301 as is (holds the order value 7) and change the map part to The character "b" from the selector 103 of No. 1 is stored in the buffer 305 along with the character "a" held in the register 304 through the register 304. As a result, the characters stored in the buffer 305 are “
ab”. Also, the comparator 302 inputs the start register 30
1 value 7 and T register 203 value 2 (value before update) is 1
However, since they do not match, the control circuit 303 outputs 1, and as a result, the control circuit 303 outputs the buffer 30.
Since the character string "ab" stored in No. 5 cannot yet be determined to be a continuous character string, the compressed code is not transmitted.

Next, when the 9th character "c" is input to the map section 1, each section operates in the same way as in the case of the 8th character "b", and the value of the T register 203 is set to the 4th character. The order value of the th character "d" is 4, the character string in the buffer 305 is "abc", and no compression code is sent.

Next, when the tenth character "a" is input, the counter outputs 10 as a count value, and the register corresponding to the character "a" in the corresponding register group 105 is driven again. In this case, the value of the driven register is the order value 7 of the seventh character "a", and the value of the valid register 106 is in the range of 1 or more and less than the count value of the counter 10, so The selector 103 outputs the character "a" and the count value 10 of the counter 104 to the generating section 3, and outputs the value 7 of the register corresponding to the character "a" to the comparing section 2.

In the comparator 2, the value 7 of the register corresponding to the character "a" from the selector 103 is held in the S register 201, and the comparator 204 stores the value 7 of the S register 201 and
At this time, the value 4 held in the T register 203 is compared with the value 4 held by the T register 203, and in this case, since they do not match, the generation unit 3
Output to. After that, the T register 203 is added to the adder 20
The value 8 is the sum of 1 and the value 7 of the S register 201 output by 2.
hold. This value is the ordinal value of the eighth character "b".

In the generation section 3, the control circuit 303 controls the comparator 2.
Since the output value 1 from 04 is received, the count value 10 of the counter 104 output by the selector 103 at this time is held in the start register 301. That is, comparator 204
outputs 1, so the character "a" from map part 1 may be the first character of a new continuous string,
The start register 301 holds its order value 10. The control circuit 303 also controls the selector 1 of the map section 1.
The character "a" from 03 is stored in the register 304, and the character string "abc" held in the buffer 305 is outputted to the output unit 4. At this time, the control unit 303 also causes the valid register 106 to hold the order value 7 of the seventh character "a" held in the S register 201. When the output section 4 receives the character string "abc" from the generation section 3, it outputs it. That is, in this case, the value of the start register 301 and
Before the value of T register 203 plus 1 matches,
Since the comparator 204 outputs 1, it turns out that the character string “abc”, which was stored in the buffer 305 with the possibility of being a continuous character string, is not, and the character string “abc
” is output as is.

The 11th character "b" and the 12th character "c" are processed in the same way as the 8th and 9th characters, except that the 12th character In the case of the letter "c", the value from the T register 203 is 9, so the value 10 obtained by adding 1 to it matches the value of the start register 301, and the comparator 302 outputs 0. Therefore, the control circuit 303 determines that the character string "abc" stored in the buffer 305 at that time is a character string continuously repeated from the seventh character preceding it, and applies the compression code to the character string "abc". Send. However, since there is a possibility that the character string "abc" continues after the last character string, the control unit 303 actually sends the compression code as follows.
This occurs after it has been confirmed that this string is not consecutive.

Thereafter, the control circuit 303 causes the valid register 106 to hold the value 10 of the start register 301, so that in subsequent processing, the same preceding character is found from the 10th character onward.

By the above operation, the input data "abcd
efabcabc...", this data compression device outputs "abcdefabc (compression code)..." as compressed data.

[0030]

As explained above, in the data compression device of the present invention, for each type of code, a register is provided to store the order value of the code of that type, and the order of the codes of the code classes stored in these registers is stored. Registers are provided to store values, and consecutive repeated code strings are detected based on the order values of the codes stored in these registers. Therefore, unlike the conventional method, the codes themselves are not compared, so there is no need to input the codes into the shift register, and there is no need to search for codes. As a result, it becomes possible to significantly reduce the time required for data compression.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a data compression device of the present invention.

FIG. 2 is a block diagram showing in detail a map section configuring the data compression device of FIG. 1;

FIG. 3 is a block diagram illustrating in detail a comparison section that constitutes the data compression device of FIG. 1;

FIG. 4 is a block diagram showing in detail a generation unit that constitutes the data compression device of FIG. 1;

FIG. 5 is a block diagram showing an example of a conventional data compression device.

FIG. 6 is a diagram for explaining the operation of a conventional data compression device.

FIG. 7 is a diagram for explaining the operation of a conventional data compression device.

[Explanation of symbols]

1 Map section 2 Comparison section 3 Generation part 4 Output section 101 Input port 102 Decoder 103 Selector 104 Counter 105 Corresponding register group 106 Valid register 201 S register 202 Adder 203 T register 204,302 Comparator 301 Start register 303 Control circuit 304 8-bit register 305 Buffer

Claims (1)

[Claims] Claim 1: A data compression device that outputs a predetermined compression code when the same code string is continuously input, comprising: a counter that increases by 1 each time a code is input, and a counter corresponding to each type of code; When a corresponding type of code is input, a plurality of corresponding registers that hold the count values of the counter, and one value held by the corresponding register corresponding to the input type of code. Comparing means outputs a coincidence detection signal when a value obtained by adding 1 to the value held in the corresponding register corresponding to the previously input code type matches, and outputs a mismatch detection signal when they do not match. When the comparison means outputs the coincidence detection signal, the start register for holding the counted value of the counter, and the code are input, and when the comparison means outputs the coincidence detection signal, the start register holds the count value of the counter, and when the comparison means outputs the coincidence detection signal, Compressed code generating means that outputs the compressed code when a value obtained by adding 2 to the value held in the corresponding register corresponding to the input code matches the value held in the start register. A data compression device comprising: