JPH04259251A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To absorb a surge voltage between a power source pin and a ground pin and to reduce the area of a chip by interposing protective elements between a special pin of the power source pin, the ground pin and the other pin. CONSTITUTION:A transistor T41 as a protective element is connected between a first ground pin 6 and a first power source pin 5. Similarly, transistors Tr2-Tr5 are respectively connected as protective elements between the pin 6 and a second power source pin 7, between the pin 6 and a second ground pin 8, between the pin 6 and an input pin 3, and between the pin 6 and an output pin 4. That is, the pin 6 is connected to the other end of the protective element connected at one end to all pins 4, 5, 7, 8. Thus, surge voltages of the pins 4-8 are absorbed by the respective elements, thereby reducing an area of a chip.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device suitable for application to a device having a plurality of power supply pins and a plurality of ground pins.

0002

2. Description of the Related Art Currently, the scale of circuit integration of semiconductor integrated circuit devices typified by semiconductor memories is increasing. Along with this, chip size has increased and data access times have been required to be faster. As a result, noise between the power supply line and the ground line increases, and the adverse effect on circuit operation may not be negligible. In particular, noise in the data output circuit of a semiconductor memory has a large effect on other circuits. One countermeasure for this problem is to use power supply pins and ground pins separately for data output circuits and peripheral circuits. The use of a plurality of power supply lines and ground lines as a noise countermeasure is increasingly being used as a design method, and is expected to increase more and more in the future.

On the other hand, a MOS type semiconductor integrated circuit device is
Due to the characteristics of its process structure, it is susceptible to electrostatic damage. As a countermeasure against this, a protection element made of a bipolar transistor as shown in FIG. 4 is connected to all pins. This bipolar transistor is constructed by using a substrate or a well as a base (p-sub), leading out an A terminal and a B terminal from the n+ part, and leading out a C terminal from the base. This bipolar transistor has voltage-current characteristics as shown in the characteristic diagram of FIG. In other words, it has such a characteristic that when the increasing voltage between the A terminal and the B terminal (breakdown voltage) is reached, a current suddenly flows from that point on. Therefore, when a surge voltage occurs between both terminals, current flows through this transistor. This prevents an excessive potential difference from being applied to other elements within the integrated circuit for a long time.

FIG. 2 shows a protection circuit for a general semiconductor integrated circuit device. In particular, the power pin and ground pin are each
This is an example of two cases. As shown in FIG. 2, a transistor Tr6 is connected between the power supply pin 1 and the ground pin 2 for protection. A transistor Tr7 is connected between the power supply pin and the input pin 3, and a transistor Tr8 is connected between the ground pin 2 and the input pin 3 for protection. A transistor T is connected between power supply pin 1 and output pin 4.
A transistor Tr9 is connected between r10, ground pin 2 and output pin 4 for protection.

According to the above configuration, surges between the power pin 1 and the ground pin 2, the input pin 3, and the output pin 4, and the surge between the ground pin 2 and the input pin 3, and the output pin 4 can be prevented. can be absorbed effectively.

On the other hand, FIG. 3 shows a configuration diagram of a protection circuit of a conventional semiconductor integrated circuit device. In particular, the case where there are a plurality of power supply pins and a plurality of ground pins (two each) is illustrated. As shown in FIG. 3, a transistor Tr11 is connected between the first power pin 5 and the first ground pin 6, and a transistor Tr1 is connected between the second power pin 7 and the second ground pin 8.
5 are each connected for protection. Further, transistors Tr13 and Tr14 are connected between the first power pin 5 and the second power pin 7 and between the first ground pin 6 and the second ground pin 8 for protection. There is. Transistors Tr16 and Tr12 are connected for protection between the first power pin 5 and the second ground pin 8, and between the first ground pin 6 and the second power pin 7, respectively. In addition, the first power pin 5, the first ground pin 6, the second
Transistors Tr17, Tr18, T
r19 and Tr20 are connected for protection. first power pin 5, first ground pin 6, second power pin 7, second
Transistors Tr24, Tr23, Tr22, and Tr21 are connected between the ground pin 8 and the output pin 4, respectively, for protection.

According to the above configuration, surges generated between the first power pin 5, the first ground pin 6, the second power pin 7, and the second ground pin 8, and To effectively absorb surges generated between the first power pin 5, the first ground pin 6, the second power pin 7, and the second ground pin 8 and the input pin 3 or the output pin 4. Can be done.

[0008]

A conventional semiconductor integrated circuit device has been constructed as described above. Therefore, in a configuration having a plurality of power supply pins and a plurality of ground pins, the number of combinations in which protection elements are connected increases. moreover,
In order to connect protection elements to all power supply pins and ground pins, it becomes necessary to route the input and output pin wiring. This results in an increase in chip size, which becomes a factor that increases costs. Therefore, effective solutions in this regard have become a major challenge.

The present invention has been made in view of the above, and
The purpose is to install protective elements for electrostatic discharge between all power pins, ground pins, and input/output pins in devices with multiple power pins and multiple ground pins without increasing chip size or chip cost. An object of the present invention is to obtain a highly reliable semiconductor integrated circuit device having surge resistance equivalent to that when placed between them.

0010

Means for Solving the Problems The device of the present invention includes a plurality of power supply pins for supplying a power supply voltage to a semiconductor circuit, and a plurality of power supply pins for supplying a ground voltage to the semiconductor circuit in cooperation with the power supply pins. a ground pin, an input pin for inputting a signal to the semiconductor circuit, an output pin for deriving a signal from the semiconductor circuit, one particular pin among the power supply pin and the ground pin, the input pin, and the output pin. The device is configured to include protection elements connected between the pin, a power supply pin other than the specific pin, and a ground pin, respectively.

[0011]

[Operation] A protective element is interposed between one specific pin of the power supply pin and the ground pin and the other pins. Therefore, the surge voltage between those pins is absorbed by each protection element. Moreover, a plurality of protection elements connected in series are interposed between the pins other than the specific pin and the other pins. Therefore, the surge voltage between those pins is absorbed by a plurality of protection elements connected in series.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a protection circuit for a semiconductor integrated circuit device according to an embodiment of the present invention. In particular, a configuration in which there are two power supply pins and two ground pins is illustrated. As shown in FIG. 1, a transistor Tr1 is provided as a protection element between the first ground pin 6 and the first power supply pin 5, and a protection element is provided between the first ground pin 6 and the second power supply pin 7. A transistor Tr2 is connected as a protection element between the first ground pin 6 and the second ground pin 8.
However, a transistor Tr4 is connected between the first ground pin 6 and the input pin 3 as a protection element, and a transistor Tr5 is connected between the first ground pin 6 and the output pin 4 as a protection element. That is, the other end of the protection element whose one end is connected to all the other pins 4, 5, 7, and 8 is connected to the first ground pin 6.

The operation of the above configuration will now be explained according to Table 1.

Now, the first ground pin 6, the first power pin 5, the second power pin 7, the second ground pin 8, and the input pin 3
, and any one of the output pins 4 is generated. In this case, transistors Tr1, T
Any one of r2, Tr3, Tr4, and Tr5 independently undergoes a voltage breakdown and absorbs the surge voltage. On the other hand, suppose that a surge voltage occurs between the first power pin 5 and the second power pin 7, for example. For this surge voltage,
A protection circuit of transistors Tr1 and Tr2 operates in series. In other words, the surge current is caused by the transistors Tr1, Tr
2, a surge protection operation is performed. In other words, the surge voltage generated between the first ground pin 6 and the other pins is
Absorbed by one protection element. However, surge voltages generated between other pin combinations are absorbed by a combination of two or more protection elements connected in series. Table 1 shows combinations of transistors that are involved in absorbing surges when they occur between pins. As is clear from Table 1, any surge voltage generated between any pins is absorbed through at least two protection transistors connected in series.

[0016]

[Table 1] In the above embodiment, a configuration was illustrated in which the protective transistors were connected toward each pin around the first ground pin 6, but the present invention is not limited to this. do not have. For example, the same effect can be obtained by connecting the protection elements around the first power pin 5, second power pin 7, or second ground pin 8 and toward each other pin. can. Further, in the above embodiment, the case where there are two power supply pins and two ground pins each is illustrated. However, it goes without saying that the present invention is also applicable to cases where there are three or more of each, or cases where the numbers of power supply pins and ground pins are different.

[0017]

[Effects of the Invention] As described above, according to the present invention, in a semiconductor circuit having a structure having a plurality of power supply pins and a plurality of ground pins, surge voltage between each pin can be absorbed with a small number of protection elements. As a result, the chip area can be reduced and costs can be reduced, and an inexpensive and highly reliable semiconductor integrated circuit device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a protection circuit of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a protection circuit of a general semiconductor integrated circuit device having one power supply pin and one ground pin.

FIG. 3 is a configuration diagram of a protection circuit of a conventional semiconductor integrated circuit device having multiple power supply pins and multiple ground pins.

FIG. 4 is an explanatory diagram of a cross-sectional structure of a bipolar transistor that is a protection element.

[Figure 5] Voltage of the bipolar transistor shown in Figure 4 -
It is a current characteristic diagram.

[Explanation of symbols]

1 Power pin 2 Ground pin 3 Input pin 4 Output pin 5 First power pin 6 First ground pin 7 Second power pin 8 Second ground pin

Claims (1)

[Claims] 1. A plurality of power supply pins for supplying a power supply voltage to a semiconductor circuit, a plurality of ground pins for supplying a ground voltage to the semiconductor circuit in cooperation with the power supply pin, and a signal input to the semiconductor circuit. an input pin for deriving a signal from the semiconductor circuit, one specific pin among the power supply pin and the ground pin, a power supply pin other than the input pin, the output pin, and the specific pin; 1. A semiconductor integrated circuit device comprising: protection elements connected between respective ground pins.