JPH0425751B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is used in general image scanning/storage devices or image scanning/display devices that once scan and decompose an image and then compose the image again, such as a facsimile transmission device. The present invention relates to an image signal processing method and an image signal processing device.

Configuration of conventional technology and its problems In recent years, the use of facsimile in daily work has been expanding more and more, and along with this, the demand for reproduction of halftones in addition to the conventional black and white binary is also increasing. Reproduction of halftones is often restricted by both recording devices and transmission methods. For example, devices that store data on silver halide photographic paper used in photography and thermal recording devices have good halftone recording characteristics, but electrostatic recording devices and inkjet recording devices are essentially suited for binary recording. I can say that. On the other hand, the transmission method is changing from the conventional analog transmission to digital transmission, and there is a tendency to make full use of data compression technology to perform faster and more efficient transmission. Therefore, if there is a good method for pseudo-halftone display using a black and white binary recording device, it will be compatible with the future direction of digital data transmission, and it will be possible to construct a more optimal facsimile transmission system.

Now, typical methods of pseudo-halftone display include the halftone method seen in printed images of newspapers and magazines, and the dither method in which the image is binarized according to a matrix table of threshold values. However, these conventional methods have the disadvantage of deteriorating the resolution for binary images such as characters and line drawings, and therefore, for images that contain a mixture of intermediate density and binary images, one or the other must be sacrificed. You won't be able to use it.

The dither method, which is a pseudo-halftone display with relatively little deterioration in the resolution of binary images, will be described below as one of the conventional examples with reference to FIG. In the figure a, 1 is a pattern indicating quantized original image data, 2 is a pattern indicating threshold value data, and 3 is a pattern indicating binarized data. The original image data D _xy is compared in size with the threshold data S _xy at the corresponding position, and if it is larger, it is black (=1), otherwise it is thresholded as white (=0\), and the binarized data is processed.
Converted to P _xy . For example, threshold data 2 is shown in figure b.
Threshold data having a size of 4×4 as shown in the figure is repeatedly expanded. When the threshold value window is 4×4, 16 types of threshold values can be set, and therefore, halftone display that pseudo-expresses 17 levels for the original image data is possible. D _nax shown in FIG. 5B represents the maximum value of the original image data.

As mentioned above, in the dither method shown in the example in Figure 1, each pixel of the original image data is thresholded independently and converted to binary data, but the number of blacks corresponding to the level of the original image data appears in each threshold window. This results in an average representation of midtones. The relationship between the size of the threshold window and display image quality is that the smaller the window, the better the image resolution, but fewer halftone levels that can be displayed; the larger the window, the worse the image resolution, but the more halftone levels that can be displayed. There is a relationship of becoming. In any case, this method has the disadvantage that the display quality of a black-and-white binary original image is poorer than that of ordinary binary processing.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an image signal processing method and an apparatus thereof that can perform pseudo-halftone display without deterioration in image quality due to resolution deterioration of the binary image.

Structure of the Invention The present invention provides: (1) storing in a first image signal storage device an image signal level obtained by superimposing a random noise component on the image signal level of each pixel obtained by scanning and decomposing the original image; (2) storing the image signal level of each pixel without superimposing random noise components in a second image signal storage device; (3) scanning the second image signal storage device with the number of pixels M; Sum of all image signal levels within the window
Find the sum S of S _n and the error correction amount E, and when OSC×M, S=C×N+A When O>S, N=O, A=O When S>C×M, N=M, A=O [ However, C is a predetermined image signal level, N is an integer satisfying O≦N≦M, and A is O≦A<C ₀ ]. The number M of pixels for scanning the position of the first image signal storage device
(5) superimposing additional data whose size is controlled according to the sum S on each pixel within the first scanning window; For each pixel in the second scanning window corresponding to the first scanning window, in descending order, the first to Nth pixels have a pixel signal level of C, (N+1)
The th pixel is assigned A as the image signal level, the remaining pixels are assigned O as the image signal level, and in ascending order, the 1st to (M-N-1)th pixels are assigned O as the image signal level. , (M-N)
The pixel is replaced with A as the pixel signal level, and the remaining pixels are given C as the pixel signal level. The image signal level P _1ST of a pixel that is no longer included in the scanning window is determined by comparing the image signal level P _1ST with a predetermined binarization level V where OV<C.
If P _1ST is large, set C to the image signal level.
If P _1ST is not large, set O to image signal level P _2ND
(7) Give the sum of the differences between the image signal levels P _1ST and P _2ND as the error correction amount E after the next scanning window movement, (8) Above (2), (3), (4), (5), (6), (7) in the first
The first,
Image processing is performed repeatedly while moving the second scanning window by a predetermined number of pixels.

DESCRIPTION OF EMBODIMENTS An embodiment of the image signal processing method of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram explaining the scanning window and data conversion. In the figure a, 5 is original image data, and data conversion is performed one by one within the scanning window 6 while the scanning window 6 is main-scanning to the right side of the figure a and sub-scanning to the lower side. Although the size of the scanning window 6 is arbitrary, it is, for example, about 2×2 pixels, 3×3 pixels, or 4×4 pixels. The scanning window 6 is basically scanned pixel by pixel in both the main scanning direction and the sub-scanning direction, but this is not necessarily the case.

Note that this embodiment will be explained by scanning one pixel at a time.

Now, if the scanning window 6 is 2×2 pixels, one pixel of the original image data, for example, the pixel D _n,o within the scanning window 6.
will undergo data conversion four times as the scanning window 6 moves. Data conversion is performed as shown in FIGS. 2b to 2e. Note that FIG. 2B shows the original image data at the position of the scanning window 6, and FIG.

(However, the number ' indicates the number of times that pixel has undergone data conversion in the past.) Figure d shows the state after data conversion has been performed at the current scanning window 6 position. . Here, it is assumed that the converted data is not rewritten to the original image data but is stored separately. The data conversion within the scanning window 6 is performed as shown in the flowchart of FIG. 3. (a) The total sum S of data as shown in FIG. 2c is determined.

S=D _n-1 , _o-1 + D _n-1 ″, _o + D _n ′, _o-1 + D _n,o ...(1) (b) Find N and A in the following equation.

S=C・N+A...(2) However, C is a constant, for example, C=D _nax .
D _nax is the maximum value. Further, N is a positive integer.

(c) Check the order of data size as shown in Figure 2b. If the values are the same, they are determined in a predetermined order.

(d) Convert the data shown in FIG. 2c to C for N parts corresponding to the data shown in FIG. 2b in order of size, convert the next to A, and convert the rest to 0\.
For example, in (b), N=1 is found, and in (c), λ _n,o-1・D _n,o-1 ＞λ _n,o・D _n,o ＞λ _n-1,o・ ・D _{n- 1,o} > λ _n-1 , _o-1 ·D _n-1 , _o-1 ...(3) When the relationship is found, data conversion as shown in FIG. 2e is performed. However, λ is a noise component.

If the above data conversion is performed on all data of the original image, it will be 0 if the data value of the original image data is small.
Where the number of C is large and the data value is large, the number of C is large, and the conversion is done in proportion to the data value of the original image data. Therefore, if normal threshold processing is performed on the data-converted values to create binarized data, pseudo-intermediate display data can be obtained.

According to the data processing described above, since the conversion data is arranged (redistributed) in order of the original image data, not only does decomposition and deterioration of the black and white binary original image not occur, but also the thin lines in the original image are Because of this, even areas that would be dotted lines in normal threshold processing tend to be reproduced as continuous lines. This is because, in the data processing described above, large value data in the original image attracts surrounding small value data and has the effect of becoming even larger.

Furthermore, according to the above data processing, since random noise components are superimposed on the input image signal level,
Random noise levels can be ranked for images in which the same image signal level exists within a wide range, for example, images generated using a computer or the like. Therefore, it is possible to suppress the occurrence of periodic patterns in the regenerated image.

Now, in Fig. 2 d, D _n-1 ′′′′, _o-1 is the value after the last data conversion. This value is O or C
In the case of A, it is fine, but in the case of A, it is binarized and an error occurs. That is, after binarization, white has a value of O and black has a value of C, so performing threshold processing on A and binarizing it means redundantly changing it to white or black. This worsens the gradation characteristics of the pseudo halftone, but let the value of D _n-1 ′′′′, _o-1 be P _1ST , and the difference between the value P _2ND (0\ or C) determined by the threshold value is the error. Correction amount E
The gradation characteristics can be improved by adding the sum S when calculating the sum S in the next scanning window.

Further, according to the data processing described above, there is a tendency for the image to have strong outline emphasis due to the above-mentioned attraction effect. In addition, where the original image has a flat density distribution, noise in the original image and noise components in photoelectric conversion create peaks and valleys (black, white) after data conversion, resulting in a binarized image with a random pattern like grain. .

Therefore, in order to make the flat density distribution of the original image become a regular distribution after data conversion and weaken the edge enhancement effect, the following method can be considered.

That is, in the data processing described above, new data is arranged in descending order of original image data within the scanning window. Therefore, by introducing regularity into the data for ranking, it becomes possible to impart regularity to the data distribution after conversion depending on the strength of the regularity, and at the same time, the peaks and troughs of the regularity work to suppress the above-mentioned attraction effect. can be made to last. FIG. 4a shows the method for providing regularity. In the figure, 11 represents original image data, 12 represents added data, and 13 represents data added to the original image data. By using the data 13 shown in FIG. 4a as the ranking data instead of the data 13 in FIG.
The above-mentioned attraction effect can be suppressed compared to the data conversion procedure in the above. Note that the data 12 in FIG. 4 is a regular array pattern, and can be created in any way, but an example thereof is shown in FIG. 4b. Figure 4b shows the case where additional data for 4 x 4 pixels is expanded, and the data value is set as a value obtained by quantizing the original image data 11 in Figure 4a with 8 bits (0 to 255). There is. The size of the additional data is set to 1/8 or less of the maximum value of 255 of the original image data, but it is preferable that the size of this value is slightly larger than the noise component of the original image data. That is, in general, original image data obtained by scanning an image is a light reflectance signal, and the white portions of the original image have large noises, and the black portions have small noises. Therefore, it is better to control the size of the additional data according to the size of the original image data. An example is shown in FIG. Scanning window 6 is 2x2, original image data 11
In the case of 8-bit quantization, the horizontal axis represents the total sum S of data within the scanning window 6, and the vertical axis represents the correction coefficient of additional data.

In this embodiment, the additional data is simply corrected to 1/2, 1/4, 1/8, or 1/16 according to the value of the data sum S, but it is sufficient for practical use. However, ideally, the amplitude correction coefficient of the additional data should be a constant ratio to the value obtained by converting the data sum S, which is light reflectance data, into density.

In the following, the image signal processing method will be explained in more detail with reference to the flowchart shown in FIG. 6 in consideration of the above-mentioned contents.

[In the flowchart shown in FIG. 6, G ₁ , G ₂ : image data storage device, W ₁ : scanning window for image data of G ₁ , λ _n,o・D _n,o , λ _{n,o- 1}・D _n,o-1 , λ _n-1,o・D _n-1,o ,
λ _n-1 , _o-1・D _n-1 , _o-1 : each data in W ₁ , λ: random noise, W ₂ : scanning window for image data of G _2, D _n,o , D _n ′ , _o-1 , D _n-1 ″, _o , D _n-1 ′′′′, _o-1 :W
The value before data conversion at the current scanning window position for each data in ₂ . The number ′ is the number of times data was converted at the past scanning window position, D _n,o , D _n ″, _o-1 , D _n-1 ′′′′, _o , D _n-1 ′′′′,
_o-1 : Value after data conversion at the current scanning window position for each data in _W2 . The number ' is the number of times data has been converted in the past including the current scanning window position, E: error correction amount, S _n : total data within scanning window W ₂ , S: value of S _n + E, M: scanning window W ₁ , number of pixels in scanning window _W2 , M=4, C: predetermined image signal level, N: integer ONM, A: OA<C, d _n,o , d _n,o-1 , d _{n-1 , o} , d _n-1 , _o-1 : additional data, k : amplitude correction coefficient that changes according to S, γ _n,o , γ _n,o-1 , γ _n-1,o , γ _n-1 , _o-1 : Ranking data, γ _n,o = k×d _n,o +λ _n,o・D _n,o γ _n,o-1 = k×d _n,o-1 +λ _{n,o- 1}・D _n,o-1 γ _n-1,o =k×d _n-1,o +λ _n-1,o・D _n-1,o γ _n-1 , _o-1 =k×d _{n- 1} , _o-1 +λ _n-1 , _o-1・D _n-1 , _o-1 V: Indicates the binarization level, respectively.

(b) Input the image data with random noise superimposed and the image data without superimposed random noise into the storage devices G ₁ and G ₂ respectively (the following processing is performed while inputting the image data one pixel or one scanning line at a time). It is also possible to do this, but in this case we will process it after all image data has been input.)

(b) A scanning window W ₁ is placed at the start position of the main scanning and sub-scanning of the image data input to the storage device G ₁ , and a scanning window W is placed at the start position of the main scanning and sub-scanning of the image data input to the storage device G ₂ . ₂ is initially set.

(c) Error correction amount E= as initial value at the beginning of main scanning
Set O.

(d) Total sum Sm of data within scanning window _W2 and error correction amount E
Find the sum S.

(e)・(f) Compare and judge the size of S, and if O>S
In (g), set N=O, A=O, and if S>C×M, set N=M, A=O in (ch), otherwise, in (li), set N and A such that S=C×N+A. demand.

(J) Find a coefficient k for correcting the amplitude of additional data according to the value of S.

(Ru) Ranking data γ _n,o , γ _n,o-1 , γ _n-1,o '
γ _n-1 , _o-1 , γ _n,o = k×d _n,o + λ _n,o・D _n,o γ _n,o-1 = k×d _n,o-1 + λ _{n,o- 1}・D _n,o-1 γ _n-1,o =k×d _n-1,o +λ _n,o-1・D _n-1,o γ _n-1 , _o-1 =k×d _{n- 1} , _o-1 +λ _n-1 , _o-1・D _n-1 , _o-
1 , and the corresponding data positions within the scanning window _W2 are rewritten as follows in descending order of size.

[Let C be up to the Nth number.

Let A be the N+1st one.

Let the rest be O. 〕 (ヲ) Data D _n-1 ′′′′, _o-1 in scanning window W ₂ is P _1ST
shall be.

(W) Compare P _1ST and binarization level V. P _1ST
If is large, then (F) sets P _2ND to C, and if P _1ST is large, then (Y) sets P _2ND to O. In addition,
Since the values of data D _n-1 ′′′′, _o-1 are finally converted to binary data at the binarization level V,
Here, it is the same whether you replace it with the value of P _2ND or leave it as is.

(T) Calculate P _2ND −P _1ST by setting E as the error correction amount to be corrected at the next scanning window position.

(v) Both scanning window W ₁ and scanning window W ₂ are moved by one pixel in the main scanning direction.

(2) Determine whether processing in the main scanning direction is complete. If it has not finished, return to (d).

(t) If it has finished, press (w) to return both scanning window W ₁ and scanning window W ₂ to the main scanning start position.
Move one pixel in the sub-scanning direction.

(n) Determine whether processing has ended in the sub-scanning direction, and if it has not ended, return to (c).

By using the processing methods (a) to (e) shown in FIG. 6, it is possible to obtain a pseudo-halftone display that does not cause deterioration in image quality due to deterioration in resolution of a binary image.

Next, an image signal processing device according to an embodiment of the present invention will be described with reference to FIG.

FIG. 7 shows block connections of an image signal processing apparatus in an embodiment of the present invention.

In FIG. 7, reference numeral 15 denotes a timing signal generation circuit that supplies timing signals to each block function to be described later, and timing signal supply lines to each block function are omitted. 17 is an A/D converter that converts an analog image signal input through the terminal 16 into a digital image signal; 10 is a random noise superimposition circuit 19, 21 is a gate circuit 18, 2, respectively;
0, an image data storage device that stores or reads out a digital image signal according to an address specified through 0; 22, an address control circuit that sends address information to the gate circuits 18, 20 to control the gate circuits 18, 20; 23, an address control circuit; a binarization circuit that binarizes the data for which all data conversion processing for redistribution has been completed and records it in an image recording device or the like via a terminal 24;
5 is a data addition circuit that calculates the sum S of the data within the scanning window and the error correction data E sent from the error correction calculation circuit 26; 28 is a ranking circuit that ranks the output of the additional data adder circuit 27 in descending order of data; 29 is a data adder circuit 25;
This is a redistribution circuit that creates converted data from the total sum S sent from and redistributes it.

The operation of the above configuration will be explained below.

First, an analog image signal obtained by scanning an original image is converted into a digital image signal by an A/D converter 17 via an input terminal 16, and the image signal stored in an image data storage device 19 is generated by a random noise superimposition circuit. 10 into a random noise superimposed digital image signal, which is stored via a gate circuit 18. Further, the digital image signal stored in the image data storage device 21 is converted into a digital image signal by the A/D converter 17 and then stored via the gate circuit 20. At that time, the gate circuit 18
and gate circuit 20 are controlled by an address control circuit 22, and instruct data write/read addresses of memory device 19 and memory device 21, respectively. In the process described later, the data stored in the storage device 19 is used as ranking data, and the data in the storage device 21 is rewritten one by one through data conversion by reallocation.

Further, the data for which all the data conversion processing for redistribution has been completed is read out from the storage device 21 via the gate circuit 21, and output image signal is recorded via the binarization circuit 23 by an image recording device (not shown) or the like. The signal is output to the output terminal 24 as a signal. Now, the data addition circuit 25 uses the data within the scanning window obtained from the storage device 21 via the gate circuit 20 and the error correction amount calculation circuit 26.
The total sum S of the error correction data E obtained from the above is calculated. The additional data addition circuit 27 controls the size of each additional data prepared internally by the sum S obtained from the data addition circuit 25, and adds each value and each data within the scanning window obtained from the storage device 19 through the gate circuit 18. are added and the information is sent to the ranking circuit 28.
Send to. The ranking circuit 28 determines all data addresses at the corresponding scanning window positions in the storage device 21 in descending order of the data obtained from the additional data addition circuit 27, and notifies the address control circuit 22 and the error correction calculation circuit 26. Also, at this notification timing, the error correction amount calculation circuit 26 and the redistribution circuit 29 are also notified. Therefore, the redistribution circuit 29
creates converted data from the sum S obtained from the data adder circuit 25 and sequentially writes the converted data to the address of the storage device 21 specified by the address control circuit 22 via the gate circuit 20. The error correction calculation circuit 26 outputs P _1ST , which is the last data-converted value (D _n-1 ′′′′, _o-1 in FIG. 2 d) within the scanning window, to the ranking circuit 2.
Based on the address and timing information from 8, the conversion data of the redistribution circuit 29 is selected, and _the
is compared with the binarization level V obtained from the binarization circuit 23 to obtain the value P _2ND of O or C, and the value P _1ST -P _2ND is given as the error correction amount E in the next scanning window.

By repeating the above steps, image signals can be processed.

The detailed configurations of the additional data addition circuit 27, ranking circuit 28, redistribution circuit 29, and error correction calculation circuit 26 shown in FIG. 7 will be described below with reference to FIGS. 8 to 13.

FIG. 8 is a block diagram showing the detailed configuration of the additional data addition circuit 27 of FIG. 7. For example, assume that additional data in a 4×4 matrix 30 shown in FIG. 9a is repeatedly added to the original image data. A storage device 32 stores the matrix data in an array 31 as shown in FIG. 9b. The storage device 32 stores the contents of a 2-bit counter 34 that counts sub-scanning synchronization pulses input from an input terminal 33 as an upper address, and the contents of a 2-bit counter 36 that counts a timing pulse _T1 input from an input terminal 35 as a lower address. Content data is output. Also, input terminal 3
The sub-scan synchronizing pulse inputted from input terminal 3 resets the counter 36, and the timing pulse _T1 inputted from input terminal 35 captures the output data of the storage device 32 into five registers 37. Assuming that the additional data is prepared as 8-bit data from b ₀ to b ₇ (however, b ₀ is higher-order), each of the five registers contains 1/1, 1/2, and 1/4. , 1/8, and 1/16 data. The comparison circuit 38 compares the contents of the sum S input from the input terminal 39 with internal constants C ₁ to C ₄ and sets one of the five output lines to 1 and the others to 0. The constants are C ₁ = 960, C ₂ = 896, shown in Figure 5.
Values such as C ₃ = 768 and C ₄ = 512. The gate circuit 40 outputs the contents of one of the five registers 37 shown below based on the output signal of the comparison circuit 38.

[When S>C ₁ , register contents of 1/16 data C ₁ When S>C ₂ , register contents of 1/8 data C ₂ When S>C ₃ , register contents of 1/4 data C ₃ S>C ₄ Register contents of 1/2 data when C ₄ Register contents of 1/1 data when S. ] The adder circuit 41 inputs the output of the gate circuit 40 and the data of the storage device inputted from the input terminal 42 to the input terminal 43.
The sum is added according to the timing pulse T ₂ input from , and is output to the output terminal 44 . In other words, the relationship between the sum S of the input terminal 39, the data D of the input terminal 42 (see FIG. 2b), the timing pulse T ₁ of the input terminal 35, and the timing pulse T ₂ of the input terminal 43 is expressed as follows. It is shown in Figure 10.

Next, details of the ranking circuit 28 will be explained. FIG. 11 shows a block configuration of the ranking circuit 28 shown in FIG. The four pieces of data within the 2×2 scanning window, including the additional data, are input from the data input terminal 44 and stored in predetermined positions of four data registers 47 corresponding to the positions within the scanning window via the gate circuit 46. be done. The predetermined position at this time is designated by setting the address of the output of the counter 48 that counts the timing pulse T ₂ inputted from the input terminal 43 in the register 47 via the gate circuit 49 . Input terminal 43
The timing pulse T ₂ inputted from the gate circuit 50 becomes a data write clock for the register 47 and is also sent to the timing control circuit 51 to output a gate switching signal to the signal line 52. The gate switching signal on the signal line 52 drives the gate circuit 46, the gate circuit 49, and the gate circuit 50, and enters the register 47 from the input terminal 44.
It creates an input mode state that takes in individual data. On the other hand, the maximum value detection circuit 53
The maximum value is detected for the four data of 7, and the data address of the maximum value is output. At this time, the timing control circuit 51 drives the gate circuit 46, gate circuit 49, and gate circuit 50 with the gate switching signal on the signal line 52, thereby creating a mode for rewriting the contents of the register 47. In this state, the data address of the maximum value is the gate circuit 4.
The negative constant value of the register 54 is set in the register 47 via the gate circuit 46. Then, the internal clock signal output from the timing control circuit 51 via the signal line 55 becomes the data write clock for the register 47 via the gate circuit 50.
The maximum value data of the register 47 is rewritten to negative data. In this state, when four internal clocks are output to the signal line 55, the contents of the register 47 all change to negative values. In the order in which this internal clock is output, the data addresses corresponding to the data first fetched into the register 47 are outputted to the output of the maximum value detection circuit 53 in descending order. This address becomes the write data of the four address storage registers 56 and is stored in sequence. At this time, the internal clock of the signal line 55 becomes the write clock of the address storage register 56 and is simultaneously input to the counter 57. The output of the counter 57 is sent to an address storage register 56 via a gate circuit 58.
Specify the location where address data is to be stored. At this time, the output signal 59 output from the timing control circuit 51 drives the gate circuit 58 to enter the data write state, that is, the output of the counter 57 is applied to the address storage register 56. After four pieces of address data are written in the address storage register 56, the output signal of the signal line 59 drives the gate circuit 58 to put the address storage register 56 in a data read state. After that, when a read clock is output to the signal line 60 of the timing control circuit 51, the counter 61 counts this clock and provides the output to the address storage register 56 via the gate circuit 58 to specify the read position of the address data. . In this way, the ranking circuit 2
Address data from 8 is output to output terminal 62. Further, the readout clock on the signal line 60 is outputted to an output terminal 63 and becomes a timing signal for other circuit blocks. Note that the counters 48, 57, and 61 are all 2-bit counters, and are reset by a sub-scan synchronization pulse (not shown). Furthermore, the details of signal timing adjustment, such as delay time compensation in hardware production, are self-evident and will not be explained here.

What should be noted here is that there are four types of address data output to the output terminal 62: 00, 01, 10, and 11, and the addresses in the image data storage devices 19 and 20 in FIG. It will be made in Therefore, 00, 01, 10, 11 are addresses within the scanning window, and if we consider them in correspondence with the scanning window 9 in Figure 2d, then 00D _n-1 ′′′′, _o-1・
It is sufficient to define 01 as D _n-1 ′′′′, _o・10 as D _n ″, _{and o-1}・11 as D _n ′, _o .

Therefore, the data input from the input terminal 44 must also appear in the order corresponding to the addresses within this scanning window. Error correction calculation circuit 26 in FIG. 13, which will be described later.
The address constant in also means an address within the scanning window.

Next, the redistribution circuit 29 will be explained.

FIG. 12 shows detailed block connections of the redistribution circuit 29 of FIG. 7. The sum S of data within the scanning window is set in a register 66 from an input terminal 64 via a gate circuit 65. A timing signal input from the input terminal 67 drives the gate circuit 65 and the register 66, and when setting the sum S in the register 66, the signal from the input terminal 64 is passed through and written to the register 66. Otherwise, gate circuit 6
5 allows the output signal of the subtraction circuit 68 to pass through. The subtraction circuit 68 extracts the contents of the register 69 from the contents of the register 66.
The constant C set in is subtracted and output.
The timing signal input from the input terminal 63 drives the register 66, and the output signal of the subtraction circuit 68 input via the gate circuit 65 is taken into the register 66. Therefore, the output of the register 66 is to sequentially subtract the constant C from the initial sum S every time a timing signal is input from the input terminal 63. Comparison circuit 7
0 is the content of register 66 and the content of register 69 C
When the contents of the register 66 are larger or the same, the gate circuit 71 is driven and the contents C of the register 69 are made the output of the gate circuit 71, and when the contents of the register 66 are small, the gate circuit 71 is driven and the register 69 is output. The contents of 66 are taken as the output of the gate circuit 71.
The positive/negative determination circuit 72 drives the gate circuit 73, and when the contents of the register 66 are positive, the output of the gate circuit 71 is used as the output of the gate circuit 73, and when the contents of the register 66 is negative, the constant 0, which is the contents of the register 74, is used.
By making the output of the gate circuit 73, the redistributed data is outputted to the output terminal 75.

Next, the error correction calculation circuit 26 will be explained.

FIG. 13 shows detailed block connections of the error correction calculation circuit 26 of FIG. 7. Comparison circuit 7
6 is the address constant of register 77 and input terminal 62
The address data input from the input terminal 63 are compared, and if they match, the gate circuit 78 is driven to allow the timing signal input from the input terminal 63 to pass. The address constant of register 77 is the value of the last data converted within the scanning window.
D _n-1 ′′′′, address within the scanning window of _o-1 in the above example
The value will be 00. The comparison circuit 79 compares the binarized level V input from the input terminal 80 and the redistributed data input from the input terminal 79, and if the redistributed data is larger, it drives the gate circuit 81 and changes the constant C of the register 82. is the output of the gate circuit 81, and if the redistributed data is large, the gate circuit 81
to drive the constant 0 of the register 83 to the gate circuit 8
The output is 1. The subtraction circuit 84 subtracts the output of the gate circuit 81 from the redistribution data at the input terminal 75. The register 85 takes in the subtraction result of the subtraction circuit 84 using the output signal of the gate circuit 78 and supplies it to an output terminal 86 as an error correction amount E.

Effects of the Invention As described above, the present invention can obtain pseudo halftones without deteriorating image quality, and the image processing according to the present invention only needs to be performed in the image reading example. Therefore, for example, existing facsimile systems can be implemented by simply adding some circuits to the transmitting side. Conventionally, when an image was a mixture of a binary image such as a character line drawing and a halftone image, it was impossible to avoid deterioration in the image quality of one of them, but the present invention has made it possible to display and record images of high quality for both. Furthermore, in the conventional dither method, the number of pseudo halftone levels that can be expressed is limited by the matrix size, and if the scanning window size is increased to increase the number of levels, the resolution will deteriorate. Therefore, when processing color images, the number of reproduced colors is so small that it is not practical. However, since the levels that can be expressed in the present invention are essentially continuous, it can be said to be an optimal method for color image processing. In addition, in color image processing, it is easily possible to reduce the overlap of each color by staggering the level distribution of the additional data for each of the yellow Y, cyan C, magenta M, and black B signals. That is clear.

Further, according to the present invention, a good reproduced image can be obtained even for image signals of equal level over a wide range, especially image signals of equal level generated by a computer.

Furthermore, the regularity of the additional data also improves the band compression efficiency of various currently announced predictive coding methods, and the present invention has a very large effect.

[Brief explanation of drawings]

Figures 1a and b are schematic diagrams illustrating the dither method, which is one of the conventional pseudo halftone displays, and Figures 2a to 2e are scanning windows and data conversion of an image signal processing method in an embodiment of the present invention. FIG. 3 is a flowchart showing a part of the processing procedure of the method; FIGS. Figure 5 is a graph showing the relationship between the additional data correction coefficient and the total sum S.
The figure is a flowchart showing the processing procedure of an image signal processing method in an embodiment of the present invention, FIG. 7 is a block wiring diagram of an image signal processing device in an embodiment of the present invention, and FIG. 8 is an additional data in the device. 9a and 9b are schematic diagrams for explaining the storage state of the storage device in the additional data adding circuit, and FIG. 10 is a timing chart showing the operation of the additional data adding circuit. 11
12 is a block diagram of the ranking circuit in the same device, FIG. 12 is a block diagram of the redistribution circuit in the same device, and FIG. 13 is a block diagram of the error correction calculation circuit in the same device. 19, 21... image data storage device, 25...
Data addition circuit, 26...Error correction calculation circuit, 2
7... Additional data addition circuit, 28... Ranking circuit, 29... Redistribution circuit.

Claims (1)

[Claims] 1. An image signal level obtained by scanning and decomposing an original image and superimposing a random noise component on the image signal level of each pixel is stored in a first image signal storage device, and the random noise component is stored in a first image signal storage device. The pixel signal level of each pixel whose components are not superimposed is stored in a second pixel storage device, and the second pixel number M of pixels to be scanned in the second pixel storage device is stored.
The sum of the image signal levels of all pixels within the scanning window S _n
Find the sum S of the error correction amount E, and when OSC×M, S=C×N+A When O>S, N=O, A=O When S>C×M, N=M, A=O [However, C is a predetermined image signal level, N is an integer ONM, and A is OA<C. ] Calculate N and A, and calculate the sum S for each pixel within a first scanning window of M pixels in which a position of the first image signal storage device corresponding to the second image signal storage device is scanned. After superimposing additional data whose size is controlled according to 1 for descending order of pixels
The pixel from the th to the Nth has an image signal level of C.
, the (N+1)th pixel is assigned A as the image signal level, the remaining pixels are assigned O as the image signal level, and in ascending order, from the 1st to (M-N
-1)th pixel has O as the image signal level,
The (M−N)th pixel has A as the image signal level,
The remaining pixels are replaced by assigning C as the image signal level, and for each pixel within the current second scanning window, the image signal level P _1ST of the pixel that will no longer be included within the scanning window due to subsequent scanning window movement. In contrast, the image signal level P _1ST is determined by comparing the image signal level P _1ST with a predetermined binarization level V where OV<C.
If the image signal level P _1ST is large, C is given as the image signal level P 2ND, and if the image signal level P 1ST is not large, O is given as the image signal level P _2ND .
The sum of the differences between the image signal levels P _1ST and P _2ND is given as An image signal processing method characterized by repeating the process while moving by a predetermined number of pixels. 2. An image signal level obtained by scanning and decomposing the original image and superimposing a random noise component on the image signal level of each pixel is stored in the first image signal storage device, and each pixel on which a random noise component is not superimposed is stored. A second image signal level of the number M of pixels to be scanned in the second image signal storage device is stored in a second image signal storage device.
The sum of the image signal levels of all pixels within the scanning window S _n
and the sum S of the error correction amount E. When OSC×M, S=C×N+A When O>S, N=O, A=O When S>C×M, N=M, A=O [However, , C is a predetermined image signal level, N is an integer ONM, and A is OA<C. ] Calculating means for calculating N and A, and each pixel within a first scanning window of M pixels for scanning a position of the first image signal storage device corresponding to the second image signal storage device; a ranking means for superimposing additional data whose size is controlled according to the sum S and then numbering each pixel in descending order or ascending order of image signal level;
For each pixel in the second scanning window corresponding to the first scanning window, in descending order, the 1st to Nth pixels have a pixel signal level of C, and the (N+1)th pixel has a pixel signal level of C. The remaining pixels are assigned O as the image signal level, and in ascending order, the 1st to (M-N-1)th pixels are assigned O as the image signal level, and the (M-N)th pixel is assigned O as the image signal level. pixel is assigned A as the image signal level, and the remaining pixels are assigned C as the image signal level, and each pixel within the current scanning window _W2 is included within the scanning window again by subsequent scanning window movement. Image signal level of pixels that disappear
For P _1ST , when the image signal level P _1ST is compared with a predetermined binarization level V where OV<C, if the image signal level P _1ST is large, C is determined, and the image signal level P _1ST is large. If there is no image signal level P _2ND , means for replacing O as the image signal level P 2ND, and means for providing the sum of the difference between the image signal levels P _1ST and P _2ND as the error correction amount E after the next scanning window movement;
An image signal processing device comprising: means for moving the first scanning window and the second scanning window by a predetermined pixel with respect to the entire area of the first and second image signal storage means.