JPH04255114A - Bit error detection circuit for analog/digital converter - Google Patents

Abstract

PURPOSE:To realize the bit error detection circuit for the analog/digital converter(ADC) in which a bit error rate BER of the ADC is measured in real time at a high speed with high accuracy. CONSTITUTION:A test waveform S such as a sine wave is generated by a test waveform generating section 2 and injected to a DUT (ADC 1). A reference waveform generating circuit 5 obtains in advance a logical waveform in the preliminary test, and limit value generating circuits 61, 62 generate a limit value resulting from adding a set width of prescribed upper and lower limits to the said logic value. Then magnitude comparators 71, 72 in the main test compare an output of the ADC 1 with outputs of both the limit generating circuits 61, 62 and when the output of the ADC 1 exceeds the limit, it is discriminated that a it error takes place, the bit error signal is outputted to error counter sections (event counters 91, 92) and a bit error rate is obtained based on the count of the said counters 91, 92.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error detection circuit for an analog-to-digital converter that operates in real time and at high speed.

0002

[Prior Art] Analog-to-digital converter (hereinafter referred to as "
DC characteristics test (DC characteristics test)
There are DC linearity tests, etc.) and AC characteristic tests (AC linearity tests, SN ratio tests, etc.). These tests are
It is often realized based on DSP (digital signal processing) technology.

[0003] Particularly in AC linearity tests and S/N ratio tests, the output of the ADC, which is the device under test (DUT), is once taken into a buffer memory, and then the desired test parameters are calculated by CPU processing (fast Fourier transform, etc.). ing. This method has the advantage that the degree of freedom of analysis is improved because the data taken into the buffer memory is post-processed.

On the other hand, in recent years, ADCs have been used in various fields, such as
It has been applied to electronic equipment such as communication equipment, AV equipment, and measuring instruments, but since the data after AD conversion is a digital code, if there is even a single bit error in the data, spectrum analysis and histogram There is a risk that subsequent processing by law etc. will be meaningless. For this reason, importance has been placed on the bit error rate BER.

Conventionally, this bit error rate BER was determined by calculating the AC linearity error many times, treating the linearity error above a certain value as a bit error, and dividing it by the total number of data (number of measurements). It is calculated by

However, this technique is disadvantageous in that it is not a real-time test and the bit error rate BER itself is on the order of PPM, requiring a huge amount of memory and digital data processing time.

[0007]

[Objective] The present invention was proposed in order to solve the above problems, and it is an object of the present invention to provide an ADC bit error detection circuit that can measure the bit error rate of an ADC in real time, at high speed, and with high accuracy. With the goal.

[0008]

Summary of the Invention In order to achieve the above object, the present invention
The DC bit error detection circuit includes a test waveform generation section that generates a test waveform to be input to an analog-to-digital converter as a DUT, and a test waveform of the sampling data output from the ADC and the test waveform at the sampling time. Compare the theoretical value data of A
When the deviation between the DC sampling value and the theoretical value of the test waveform exceeds a predetermined value, it is assumed that a bit error has occurred. The device is characterized by comprising an error counter unit that inputs a bit error signal and counts the bit error signal.

Further, the digital data value comparison section is constituted by a reference waveform generation circuit, a pair of limit value generation circuits, and a pair of magnitude comparators, the reference waveform generation circuit generates theoretical value data of the test waveform, and the The limit value generation circuit generates limit value data by adding predetermined upper and lower limit setting widths to the theoretical value data, and the magnitude comparator generates the sampling value output from the analog-to-digital converter and the limit values from both limit value generation circuits. and when the sampled value exceeds the limit value, it is assumed that a bit error has occurred and a bit error signal is output, and further, the count value counted by the error counter section and It is also characterized by comprising bit error rate detection means for calculating the ratio of the number of comparisons between the sampling data and the theoretical value data.

The basic operation of the bit error detection circuit of the present invention will be explained below. Note that each component of this bit error detection circuit operates in synchronization with a predetermined reference clock signal. First, a test waveform is generated by the test waveform generator. As this test waveform, various suitable waveforms such as a sine wave and a sawtooth wave can be adopted, but considering that subsequent signal processing is easy and a waveform that is close to the actual operation of the ADC is preferable, a sine wave is preferably used. For example, when using a sine waveform, the frequency of the sine wave is basically determined by the specifications of the ADC, but specifically the depth of the memory where the waveform data of the test waveform generator is stored, the memory It also depends on the number of cycles of the sine waveform written on the clock frequency.

Before carrying out the main test, the following preliminary test is usually carried out. In this preliminary test, a test waveform is input to the ADC, and theoretical waveform data (reference waveform data) is obtained from the output of this ADC. The reference waveform data generated from the above preliminary test is performed under substantially the same conditions as when the main test is performed. In other words, using the test waveform used in this test,
Since the reference waveform data is generated by operating C, the test system (especially the delay of the test waveform generator) and DU
It is possible to eliminate or correct delays and the like that depend on the internal structure of the ADC.

In this test, the digital data value comparison section compares the theoretical reference waveform data with the output data from the ADC, and compares the sampling value of the analog-to-digital converter with the theoretical value of the test waveform. When the deviation from the value exceeds a predetermined value, it is assumed that a bit error has occurred, and the digital data value comparison section outputs a bit error signal. Note that, for example, when the test waveform is a sine wave, the limit value output from the limit value generation circuit also changes dynamically, so that bit errors can be detected with high accuracy. Then, the value of the bit error rate BER can be obtained by counting the bit error signal by the error counter section and dividing this counted value by the number of comparison operations.

Furthermore, the digital data value comparison section may be constructed of a reference waveform generation circuit, a pair of limit value generation circuits, and a pair of magnitude comparators. In this case, the reference waveform generation circuit generates the theoretical value of the test waveform, and the limit value generation circuit (including memory)
By storing in advance a limit value obtained by adding predetermined upper and lower limit settings to the theoretical value, the magnitude comparator can more quickly compare the test waveform data with the reference waveform data. Furthermore, the count value of the error counter (■) and the number of comparisons between the sampling data output from the analog-to-digital converter and the theoretical value data of the test waveform at the sampling time of the test waveform (■) are determined, and the difference between ■ and ■ is calculated. The bit error rate of the DUT can be detected in real time by calculating the ratio of .

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, a desired waveform (sine wave S in the figure) is input to the ADC 1, which is a DUT, from a test waveform generator (test waveform generator 2 in the figure) that can generate any waveform. The test waveform generator 2 is composed of a RAM and a digital-to-analog converter (DAC), and the sine waveform data S stored in the RAM is DA-converted by the DAC and output. The ADC1 may or may not have a built-in clock generator, but normally the clock generator 3 is connected to the ADC as shown in Figure 1.
It is externally attached to C1. In the figure, this clock generator 3 synchronizes the entire bit error detection circuit system. In FIG. 1, an ADC 1 inputting a predetermined clock CLK from a clock generator 3 normally performs A/D conversion on the input signal in synchronization with the CLK, and outputs a digital code.

A digital data value comparator 4 is connected to the output side of the ADC 1. This digital data value comparison section includes a reference waveform generation circuit 5 that generates a theoretical value of a test waveform, a pair of limit value generation circuits 61 and 62, and a pair of magnitude comparators 71 and 72. Note that the address counter 8 is connected to the digital data value comparison section 4 (in FIG. 1, the limit value generation circuit 6
2), the address counter 8 counts the number of comparison operations, and is used for calculating the bit error rate BER.
2 compares the value of the digital code from the ADC 1 and the value of the digital code from the limit value generation circuits 61 and 62 in real time. In the figure, limit value generation circuits 61 and 62 generate upper limit (H side) and lower limit (L side) limit values, respectively. In addition, the H side and L side magnitude comparators 71 and 72 are connected to the event counter 9.
1,92. These event counters 91 and 92 constitute an error counter unit that counts bit errors.

The operation of the bit error detection circuit shown in FIG. 1 will be explained below. A preliminary test will be conducted before the main test. That is, first, a sine wave S is input from the test waveform generator 2 to the ADC 1, and an n-bit digital code X is generated by the ADC 1. This digital code X is directly captured by the reference waveform generation circuit 5, and the captured data code X is subjected to sine curve fitting to obtain ideal sine wave data (sine wave theoretical value data). Next, desired H-side and L-side limits are added to the obtained ideal sine wave data to generate limit value data, and this limit value data is written into limit value generation circuits 61 and 62. Note that in this preliminary test, the test waveform generation circuit 2,
Since the ADC 1 operates in the same manner as in the main test, it is possible to eliminate or correct errors caused by delays in the test waveform generation circuit 2 and the ADC 1 as described above.

In this test, the magnitude comparators 71 and 72 receive the data code X from the ADC1.
The limit value code L is input from the limit value generation circuits 61 and 62. In FIG. 1, the codes X and L input to the magnitude comparator 71 are represented as HX and HL, and the codes X and L input to the magnitude comparator 72 are represented as LX and LL. These data codes HX and HL, and LX and LL are generated synchronously and are compared by magnitude comparators 71 and 72. The magnitude comparator 71 outputs a bit error signal to the event counters 91 and 92 when HL<HX, and the magnitude comparator 72 outputs a bit error signal to the event counters 91 and 92 when LL>LX.

After performing the comparison operation a desired number of times (set by the address counter 8), the event counter 9
1.92 and the previously set count value of address counter 8 (i.e., the number of comparisons), calculate the bit error rate by BER = (event counter count value) / (address counter count value). Can be done. BE above
The calculation of R is performed by a bit error rate detection means (not shown). Usually, the sum of the counts of event counters 91 and 92 is used as (count value of event counter) in the above equation, but for example, the count value of either event counter 91 or 92 can also be used.

Note that the magnitude comparator 71,
72, masking unnecessary bits (for example, lower bits) of the limit signals HL and LL from the limit value generation circuits 61 and 62 enables faster and simpler measurement.

[0020]

[Effects of the Invention] Since the present invention is configured as described above, the following effects can be achieved. (1) Since no memory buffer is used, bit errors of the ADC can be determined in real time, at high speed, and with high accuracy. (2) By conducting a preliminary test under conditions similar to the main test, errors caused by system delays and ADC output delays can be eliminated. (3) Since a dynamically changing waveform such as a sine wave can be used as the test waveform, bit error detection can be performed under conditions close to actual operation. (4) By generating limit values in advance by adding predetermined upper and lower limit settings to the theoretical value of the test waveform using both limit value generators, it is possible to compare the size of the test waveform data and the reference waveform data by the dynamic comparator. Comparisons are made more quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a bit error detection circuit of the present invention.

[Explanation of symbols]

1 ADC (DUT) 2 Test waveform generator (test waveform generator) 3 Clock generator 4 Digital data value comparison unit 5 Reference waveform generation circuit 61, 62 Limit value generation circuit 71, 72 Magnitude comparator 8 Address counter

Claims (3)

[Claims] 1. A test waveform generation unit that generates a test waveform to be input to an analog-to-digital converter as a test target, sampling data output from the analog-to-digital converter, and a sampling time of the test waveform. Compare the theoretical value data of the test waveform at A bit of an analog-to-digital converter, comprising: a digital data value comparison section that outputs; and an error counter section that inputs and counts a bit error signal from the digital data value comparison section. Error detection circuit. 2. The digital data value comparison section includes a reference waveform generation circuit, a pair of limit value generation circuits, and a pair of magnitude comparators, the reference waveform generation circuit generates theoretical value data of the test waveform, and the The limit value generation circuit generates limit value data by adding predetermined upper and lower limit setting widths to the theoretical value data, and the magnitude comparator generates the sampling value output from the analog-to-digital converter and the limit values from both limit value generation circuits. 2. The bit of the analog-to-digital converter according to claim 1, wherein when the sampled value exceeds the limit value, it is determined that a bit error has occurred and a bit error signal is output. Error detection circuit. Claim 3: A count value counted by an error counter unit;
3. The bit error detection circuit for an analog-to-digital converter according to claim 1, further comprising bit error rate detection means for calculating a ratio between the number of comparisons between the sampling value and the theoretical value.