JPH04250783A - Picture processing unit - Google Patents

Abstract

PURPOSE:To make the processing unit small and to reduce the power consumption by connecting a video decoding section to each of plural compression video memories and applying video processing to plural video decoding outputs. CONSTITUTION:A video decoder 20 receives a video compression data via a transmission line and is designated of to which of compression video memories 4,5,6 the data is to be written and writes the video compression data to the compression video memory 4. Then a read instruction is given to the decoder 20, the compression video memory 4 is read, and a decode circuit 44 decodes the data into the original video data and it is displayed. Moreover, while the compression video memory 4 is read and decoded and the data is displayed, the video data is written to the compression video memory 5, a read instruction reads the compression video memory 5 and the data is decoded and displayed. This is applied similarly even to the compression video memory 6. Furthermore, a video processing circuit 11 applies arithmetic processing to the video data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus that decodes a video signal from compressed video information input from a transmission medium or a storage medium.

0002

2. Description of the Related Art FIG. 5 shows a block diagram of a conventional video decoding device and its peripheral devices. 51 is a video decoding device 61
52 is an interface unit that converts the signal inputted at the input unit 51 into compressed video data and device control commands;
53 is a decoding circuit that restores compressed video data compressed by a combination of the sub-sampling method and the DPCM method to the original video data, and 54 is a frame memory F that stores one frame of video data restored by the decoding circuit 53.
MA, 55 is a frame memory FMB that stores one frame of video data restored by the decoding circuit 53, 56 is a frame memory FMC that stores one frame of video data restored by the decoding circuit 53, and 59 is a frame memory. This is a memory control unit that controls writing and reading to 54 to 56. 57 is a video processing circuit that generates various images such as scrolling and wipe using a plurality of frame memories, and 58 is a D/A converter that converts video data read from the video processing circuit 57 into analog. 6
2 is an analog output section of the video decoding device, and 60 is a display device that displays the video.

Further, in FIG. 5, 71 is a digital output section of the video decoding device, and the memory control circuit 59 receives a recording command inputted from an external switch 74 from a command input section 73, and outputs a recording command from an external recording device 72, for example. A digital video signal is output to a printer or the like. In this conventional example, the video decoding device receives compressed video data created and processed in the host processing unit 63 of the video compression device and compressed in the compression unit via a transmission path, and after decoding, the video data is stored in three frame memories 54 to 56 is specified, and the video compressed data is written to the first frame memory. Thereafter, the first frame memory is read out and displayed. While reading and displaying the first frame memory, compressed video data is written to the second frame memory, and then the second frame memory is read and displayed. In this way, the same applies to the third frame memory, and when the frame memory is read, the video processing circuit 57 not only switches the display but also scrolls and displays between the plurality of frame memories 54 to 56. , wipe display, etc. can be easily controlled.

0004

[Problems to be Solved by the Invention] However, in the above conventional example, one frame memory is required for each video, and for example, 4,000 dots horizontally and 2,000 dots vertically.
In the case of a dot image, if each pixel is expressed in 8-bit gradation and color is expressed in RGB, the amount of information in one image is 4,000 × 2,000 × 8 × 3 = 192,
000,000 bits, and if you add it to 3 pieces, it becomes 576,000,000 bits.
Problems arose in the large size of the equipment, high power consumption, and high cost.

The present invention solves the problems of large-sized devices, high power consumption, and high costs, and achieves miniaturization, low power consumption, and
The purpose is to provide a low-cost video decoding device.

[0006]

[Means for Solving the Problems] The problems of the present invention are as follows:
at least two compressed video memories that store input compressed video information; at least two video decoders connected in series or parallel to each of the compressed video memories;
This is achieved by an image processing device characterized by comprising: processing means for video processing the plurality of outputs of the plurality of video decoding units.

With the above configuration, compressed video information is written into a vacant compressed video memory, and the compressed video information is decoded into video information in the order of output in the decoding section, which is output to the video processing section. can be omitted,
This makes it possible to reduce the size of the device, reduce power consumption, and provide a low-cost image processing device.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a video decoding apparatus according to the present invention. 1 is a compressed data input unit that inputs compressed video data from a transmission medium or a storage medium; 20 is a video decoding device according to the embodiment; 21 is a display device such as a color monitor that displays video; and 22 is a printer or the like that records video. It is a recording device.

In the video decoding device 20, 2 is the input section 1
4 is the interface section 2 which converts the input signal into compressed video data, device control commands, etc.
The compressed video memory SMA, 44, which stores one frame of video compressed data separated by the method, converts the video compressed data stored in the compressed video memory SMA4 into the original video data by, for example, a combination of the sub-sampling method and the DPCM method. The decoding circuit A to be restored, 5 is a compressed video memory SMB that stores one frame of compressed video data separated by the interface section 2, and the decoding circuit 45 is a compressed video memory SMB that stores one frame of compressed video data separated by the interface unit 2.
A decoding circuit B restores the compressed video data stored in the MB 5 to the original video data, 6 a compressed video memory SMC that stores one frame of compressed video data separated by the interface unit 2, and 46 a sub-sample, for example. By combining the method and DPCM method, compressed video memory SM
This is a decoding circuit C that restores the compressed video data stored in C6 to the original video data.

These compressed video memories SMA to SMC (4
6) is a dual port random access memory configured so that video data can be written to a random address from the interface unit 2 side, and read out from the decoding circuits 44 to 46 completely asynchronously. . In addition, these decoding circuits 44 to 46 have circuits that can effectively read out the compressed video memory at every 1/30 second and complete decoding, but the timing of writing and decoding of compressed video signals is is the control unit 13
will be in charge. The control unit 13 includes compressed video memories 4, 5, 6.
9 is a digital video bus VBA that can transmit video data at a frame rate; 10 is another digital video bus VBB that can transmit video data at a frame rate; and 11 is a digital video bus VBB that can transmit video data at a frame rate. a video processing circuit that inputs the digital video buses VBA and VBB of 9 and 10 and processes the video data; 12 is a D/A converter that converts the video data read from the video processing circuit 11 into analog;
Reference numeral 14 denotes a video data output section that outputs video data read out from the video processing circuit 11. 23 is a switch that sends a command to the control unit 13 to cause the currently displayed video to be continuously displayed or to cause the recording device 22 to record the currently displayed video.

On the other hand, FIG. 5 shows a video compression device corresponding to the video decoding device 20 shown in FIG. From there, a necessary portion is selected in the host processing unit 63, or an image is created by operating a keyboard or mouse (not shown), and these images are combined to create one image. 64 is a compression unit that generates compressed video data by compressing the video created by the host processing unit 63 by a combination of the sub-sampling method and the DPCM method; 65 is a transmission unit that multiplexes and transmits the compressed video data and information; 66 is an output section of the video compression device.

In FIG. 5, reference numeral 70 denotes a transmission line, and for instant transmission, it can be transmitted via optical fiber, satellite, terrestrial radio waves such as microwave, etc.
It is a transmission medium such as optical space, and for storage transmission, it is a storage medium such as a tape-shaped medium such as a digital VTR or DAT, a disk-shaped medium such as a floppy disk or an optical disk, or a solid medium such as a semiconductor memory. be. The transmission rate on the transmission path varies depending on the size of the video, the compression rate, and the time to display one video, and varies from several tens of kilobits/second to several tens of megabits/second.

The control procedure executed by the above-mentioned apparatus will be explained with reference to the flowcharts of FIGS. 2 and 3. First, when the apparatus of the embodiment starts, all read commands are reset (S1), and after becoming ready for reception, it is determined whether there is a write command in the received information separated by the interface section 2 (S2). ), and if there is a write command, check which compressed video memories 4, 5, and 6 can be written to (
S3), enable writing to the designated compressed video memory, and write compressed video information (S4). For time management of the order in which simultaneously written information is read out, separate read commands are registered by the interface section 2 (S5).

FIG. 3 shows a control flow for reading written compressed information in accordance with the registered reading order.
When the device is started up, it is first initialized (S11), and when video output is possible (S22), it is decoded by decoding circuits 44 to 46 according to the registered reading order, and then sent to either digital video bus 9 or 10. It is output, subjected to appropriate processing in the video processing circuit 11, and output (S2
3).

As mentioned above, the video decoding device in this embodiment has the ability to create and
Receives the compressed video data that has been processed and compressed in the compression unit via the transmission line, and when it is specified which of the three compressed video memories to write to, writes the compressed video data to the first compressed video memory. . Thereafter, the first compressed video memory is read out in response to a read command, and immediately decoded into original video data by a decoding circuit and displayed.

That is, compressed video data is read out at a frame rate and decoding is repeated. Also, while the first compressed video memory is read, decoded, and displayed, compressed video data is written to the second compressed video memory, and then the second compressed video memory is read by a read command. , decrypt, and display. The same process is performed for the third compressed video memory. In addition, the two decoding circuit outputs, that is, the video data, are simultaneously output to digital video buses 9 and 10, respectively, and the video processing circuit temporally switches and selects one of the two digital video buses to display the data. In addition to switching cuts, it also performs wipe display, etc., and by changing the readout address over time, it can scroll display between multiple compressed video memories. A composite image of two images is created by weighting the image data and performing operations such as addition, subtraction, multiplication, and division.

Next, a second embodiment of the present invention will be explained using FIG. 4. FIG. 4 is a configuration block diagram of a second embodiment of the present invention, in which 101 is an input unit for inputting compressed video data from a transmission medium or storage medium, 120 is a video decoding device, and 121 is a color monitor for displaying video, etc. with a display device of 122
is a recording device such as a printer that records images. 120
In the video decoding device according to the second embodiment of the present invention,
Reference numeral 102 denotes an interface unit that converts the signal inputted by the input unit 101 into compressed video data, device control commands, etc.;
4 is a compressed video memory SM that stores one frame of compressed video data separated by the interface unit 102;
A, 105 is a compressed video memory SMB that stores one frame of video compressed data separated by the interface unit 102; 106 is a compressed video memory that stores one frame of video compressed data separated by the interface unit 102; It is SMC. These compressed video memories 10
Reference numerals 4 to 106 designate dual port random access memories configured so that video data can be written to random addresses from the interface section 102 side and read from the decoding circuit side completely asynchronously.

Furthermore, these compressed video memories 104 to 10
6 is effectively the compressed frame rate, that is, the compression rate times the frame rate every 1/30 seconds (the compression rate is a number N greater than or equal to 1).
It has a circuit that can read data at a rate of 1/N. 109 is a digital video bus VBA capable of transmitting video data at a compressed frame rate; 11
0 is another digital video bus VBB capable of transmitting video data at a compressed frame rate. 144 is
For example, by combining the sub-sampling method and the DPCM method, digital video buses VBA, V
The decoding circuit A, 145 that restores the original video data via one of the digital video buses BB stores the data in one of the compressed video memories SMA, B, and C by, for example, a combination of the sub-sampling method and the DPCM method. This decoding circuit B restores the compressed video data to the original video data via one of the digital video buses VBA and VBB.

These decoding circuits are constructed of circuits that read and decode the compressed video memory at a compressed frame rate, and effectively output video data at a frame rate, that is, every 1/30 second. 111 is a video processing circuit that inputs the decoding circuits A and B of 144 and 145 and processes video data; 112 is a D/A converter that converts the video data read from the video processing circuit 111 into analog; 1
14 is an output unit that outputs the video data read out from the video processing circuit 111. 123 is a switch that sends a command to the device control circuit 113 to cause the currently displayed video to be continuously displayed or to cause the recording device 122 to record the currently displayed video. 113 is compressed video memory 1
Writing and reading for 04, 105, and 106,
This is a control unit for controlling each function of the video processing circuit No. 111.

[0020] Normally, compressed video memories 104, 105, 1
The control section 113 allows the control section 113 to write the write commands sorted by the interface section 102 to the compressed video memory 06. Further, the read commands separated from the interface section 102 are sent to the control section 1 of 113.
13 performs time management, controls which compressed video memories 144 and 145 are outputted to which digital video bus, and further issues various execution commands to the video processing circuit 111.

The video decoding device in the second embodiment receives compressed video data created and processed in the host processing section of the video compression device and compressed in the compression section via a transmission path, and stores three compressed video memories. The compressed video data is designated to which one of the compressed video memories is to be written. Thereafter, in response to a read command, the first compressed video memory is output to either digital video bus 109 or 110, decoded into original video data by either decoding circuit 144 or 145, and displayed. That is, reading compressed video data at the compressed frame rate, decoding it, and outputting the video data at the frame rate are repeated. Also, while the first compressed video memory is being read out, decoded, and displayed, the second compressed video memory is output to either digital video bus 109, 110, and the decoding circuits 144, 145 convert the original video data. decode and display. In this way, reading compressed video data at the compressed frame rate, decoding it, and outputting the video data at the frame rate are repeated. The same process is performed for the third compressed video memory.

Furthermore, two compressed video memory outputs, that is, compressed video data, are simultaneously output to the digital video buses 109 and 110, respectively, and the decoding circuits 144 and 145
By decoding and selecting which of the two decoding circuits the video processing circuit temporally selects, it is possible to not only switch the display but also perform wipe display, etc., and also change the readout address temporally. Therefore, scrolling display among a plurality of compressed video memories is performed. Further, the video data outputted to the two decoding circuits are calculated, for example, by addition or by multiplying each video by a predetermined coefficient and then compositing, thereby creating a composite video of the two videos.

It should be noted that the control flowchart of the second embodiment is omitted since FIGS. 2 and 3 can be used for the most part. Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the number of compressed video memories, the number of decoding circuit units, the number of digital video buses, etc. 1, 9,10, Figure 4, 109,1
10 was explained using the bus configuration of the digital video bus.
It may be a simple switch circuit that performs switching. Although the so-called sub-sampling method and DPCM method have been described as compression/decoding methods, various other compression/decoding methods such as ADCT method and vector quantization method can also be applied.

Furthermore, although the external recording device connected to the output section of the present apparatus has been described as having a so-called digital interface, it may also be an external recording device having a so-called analog interface connected to the D/A section of the present apparatus. Although the external output device has been described as having two systems, a display device and a recording device, it is also possible to use a device having only one of them. In addition, in this example, the smell is 1/3
Although the explanation has been made for so-called non-videos where the video is not updated in 0 seconds, the technology according to the present invention is not limited to so-called non-videos due to the increase in the capacity and speed of transmission media.
The present invention can also be applied to a video decoding device that handles moving images whose video is updated every second.

[0025]

As can be easily understood from the above description, according to the present invention, compressed video information is written in a writable compressed video memory, and the compressed video information is decoded by the decoder in the order of output. Since it is output directly to the video processing section,
It is possible to provide an image processing device that can omit a frame memory, is smaller in size, has lower power consumption, is less expensive, and can perform high-speed processing.

[Brief explanation of the drawing]

[0026]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

[0027]

FIG. 2 is a flowchart showing a control procedure for writing compressed video information in an embodiment of the present invention.

[0028]

FIG. 3 is a flowchart showing a control procedure for decoding written compressed video information in an embodiment of the present invention.

[0029]

FIG. 4 is a block diagram showing a second embodiment of the invention.

[0030]

FIG. 5 is a block diagram illustrating the configuration of a conventional example of the present invention.

[0031]

[Explanation of symbols]

1,101 Compressed data input section 2,102 Interface section 4,104 Compressed video memory SMA 5,105 Compressed video memory SMB 6,106 Compressed video memory SMC 9,109 Digital video bus VBA10,11
0 Digital video bus VBB11, 111 Video processing circuit 12, 112 D/A converter 13, 113 Control section 14, 114 Video data output section 20, 120 Video decoding device 21, 121 Display device 22, 122 Recording device 23, 123 Switch 44, 144 Decoding circuit A 45, 145 Decoding circuit B 46, Decoding circuit C

Claims (1)

[Claims] 1. At least two compressed video memories that store input compressed video information, at least two video decoders connected in series or parallel to each of the compressed video memories, and the plurality of video decoders. 1. An image processing apparatus comprising: processing means for video processing a plurality of outputs of the image processing apparatus.