JPH04250576A - Image processor - Google Patents

Abstract

PURPOSE:To decrease the number of storage means stored with image data and address counters, to eliminate the need for address control by an external personal computer, etc., and to easily incorporate a binarization function. CONSTITUTION:A memory stored temporarily with image data outputted by an AD converter, a memory stored with a correction value for normalizing the white level and black level of an image signal, and a memory stored with a binarization slice level for converting the image signal into binary data are put together as blocks into two storage means 52 and 53 and data in those memories are read and written on a time-division basis with a write address signal and a read address signal generated by a write address signal generating means and a read address generating means.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus that digitizes a signal of an original image read by a handy scanner, an image reader, etc., and transfers the digitized signal to an external image utilization apparatus such as a personal computer.

0002

2. Description of the Related Art When a signal of a document image read by a handy scanner or an image reader is transferred to an external image utilizing device such as a personal computer, there is a gap between the handy scanner or image reader and the image utilizing device.
An image processing device is arranged as a kind of interface that digitizes the signal of the original image.

In such an image processing device, two buffer memories are provided, and digitized image data is written into these buffer memories alternately, and when one is in a writing state, the other is in a reading state. According to
There are devices that enable high-speed transfer of image data.

FIG. 11 is a block diagram showing the configuration of a conventional example, in which an AD converter 100 converts an image signal VS obtained by scanning a document image with a handy scanner (not shown) into image data SD consisting of a plurality of bits. , an A buffer memory 101 and a B buffer memory 102 that alternately store the image data SD output from this AD converter 100 line by line in the main scanning direction, and the white level of the image signal VS output from the handy scanner. and a correction value (shading correction value) H for normalizing the black level.
An address signal WAD for writing the image data SD output from the C buffer memory and the D buffer memory 104 that have stored DW and HDB, and the AD converter 100 into the A buffer memory 101 and the B buffer memory 102.
and a read address signal R for reading out the image data SD written in the A buffer memory 101 and the B buffer memory 102.
Address register 106 that outputs AD and correction value H in C buffer memory and D buffer memory 104
DW, HDB read/write address signal R/W・ADC,
Address counter 107, 1 that outputs R/W・ADD
08 and the white level correction value HDW read from the C buffer memory 103 as an analog white level correction signal HS.
DA converter 109 for converting into W and D buffer memory 1
DA converter 11 that converts the black level correction value HDB read from 04 into an analog white level correction signal HSB.
0.

Furthermore, a selector 111 selectively supplies the image data SD output from the AD converter 100 to the A buffer memory 101 and the B buffer memory 102 alternately for each line in the main scanning direction; The selector 112 that sends the image data read from the buffer memory 102 to the data bus 114 of the personal computer PC via the next stage selector 113 and the write address signal WAD output from the address counter 105 are switched to the write state.
Buffer memory 101 (or B buffer memory 102
), and the read address signal RAD output from the address register 106 is sent to the selector 115 and the address counters 105, 107, 108. Increment signals INC1, INC2, INC3 to address register 106, address signal set pulse SPP to address register 106, select control signal SL1 to selectors 111, 112, 115,
The controller 116 outputs SL2 and SL3.

Here, the read address signal RAD is output from the address register 106 instead of the address counter because of the A and B buffer memories 101 and 102.
This is to transfer only the image data SD of necessary pixels out of the image data SD written to the personal computer PC.

In the conventional image processing apparatus configured as described above, when the handy scanner is in a standby state for reading an original image, the A buffer memory 101 is in a write state,
The other B buffer memory 102 has been switched to a read state by the controller 116. A selector 11 on the input side of these buffer memories 101 and 102
1 selectively supplies the image data SD from the AD converter 100 to the A buffer memory 101 in the write state, and the selector 112 on the output side supplies the B buffer memory 102 in the read state.
Selector 113 selects the image data to be read from
It is controlled by select control signals SL1 and SL2 so that it is selectively supplied to the personal computer PC through the input terminals.

[0008] Furthermore, C and D buffer memories 103 and 10
4 stores in advance correction values HDW and HDB for correcting the white level and black level of the read pixels in the main scanning direction. These correction values HDW and HDB are the level of the image signal VS of each pixel in the main scanning direction when the white reference image is read in advance with the handy scanner, and the level of the image signal VS of each pixel when the light source is not turned on. The normalized calculation is performed for each pixel, and the calculation results are transferred to the C and D buffer memories 103 and 104 via the data bus 114 to be stored.

[0009] In such a state, the handheld scanner starts reading an original image, and the image signal VS of each pixel in the main scanning direction is AD in chronological order starting from the first pixel.
When input to the converter 100, the AD converter 100 converts this image signal VS into image data SD consisting of a plurality of bits.
Convert to At this time, address counters 107 and 108
is incremented by increment signals INC2 and INC3 with a period corresponding to the reading speed of one pixel in the main scanning direction, and can specify the read address of the correction values HDW and HDB corresponding to the first pixel to the last pixel in the main scanning direction. It looks like this.

[0010] As a result, the C and D buffer memories 103
, 104, the white level correction value HDW and the black level correction value HD corresponding to the first pixel to the last pixel in the main scanning direction.
B are read out sequentially. The correction values HDW and HDB are converted into analog correction signals HSW and HSB by DA converters 109 and 110, respectively, and inputted to the AD converter 100 as white level and black level conversion reference voltages.

[0011] Thereby, the AD converter 100 converts the image signal VS of each pixel into image data SD consisting of a plurality of bits based on the white level and black level conversion reference voltages of the corresponding pixel.

This image data SD is selected by the selector 111 as A.
Since the buffer memory 101 side is selected, the signal is supplied to the A buffer memory 101.

On the other hand, like the address counters 107 and 108, the address counter 105 is incremented by an increment signal INC1 having a period corresponding to the reading speed of one pixel in the main scanning direction, and is incremented from the first pixel to the last pixel in the main scanning direction. It is now possible to specify the write address of the image data SD up to the point where the image data SD is to be written. Further, a read address signal RAD specifying image data of a desired pixel is transferred from the personal computer PC to the address register 106 via a data bus 114 and a selector 113, and is set by a set pulse SP output from the controller 116. It has become. For example, when transferring one line of image data SD stored in the B buffer memory 102 to the personal computer PC in order from the first pixel to the last pixel,
A read address signal RAD corresponding to the first pixel to the last pixel is transferred from the personal computer PC, and a set pulse S is output from the controller 116.
It is set by P.

Here, since the A buffer memory 101 is in the write state and the B buffer memory 102 is in the read state, the write address signal WAD output from the address counter 105 is input to the A buffer memory 101 through the selector 115. address register 10
The read address signal RAD output from 6 is input to the B buffer memory 102 through the selector 115.

In this way, the image data SD is input to the A buffer memory 101 through the selector 111, and the write address WAD is input through the selector 115.
By inputting , the image data SD from the first pixel to the last pixel in the main scanning direction is sequentially written.

On the other hand, in the B buffer memory 102, by inputting the read address signal RAD through the selector 115, the image data SD written in the previous line from the first pixel to the last pixel is sequentially read out. , selectors 112, 113, and data bus 114 to the personal computer PC. In addition, the first
Since the image data SD is not stored in the line,
This first line of image data SD is not used.

In this way, reading and writing of one line of image data SD in the main scanning direction is completed. Then, when a line start pulse (not shown) indicating that reading for the next line has started is output from the handy scanner, the controller 116 changes the A buffer memory 101, which had been in the writing state, to the reading state. The B buffer memory 102, which was in the write state, is switched to the write state through the controller 116. Furthermore, the selector 111 is set to AD by the select control signals SL1 and SL2.
The output image data SD of the converter 100 is selectively supplied to the B buffer memory 102, and the selector 112 supplies the image data SD read from the A buffer memory 101 to the selector 1.
13 to selectively supply the personal computer PC. Furthermore, in response to the select control signal SL3, the selector 115 selectively supplies the write address signal WAD output from the address counter 105 to the B buffer memory 102, and selectively supplies the read address signal RAD output from the address register 106 to the A buffer memory 101. Switch to

In this state, when the handy scanner starts outputting a timing pulse of one pixel period, the controller 116 outputs the increment signals INC1 to IN.
C3 is generated and address counters 105, 107, 10
Write address signal WAD, R/W output from 8
- Update ADC, R/W, and ADD one address at a time. Thereby, contrary to the previous line, the image data SD output from the AD converter 100 is written into the B buffer memory 102 in order from the first pixel.

On the other hand, in parallel with the image data writing operation, the personal computer PC writes the address register 1 through the data bus 114 and the selector 113.
In order to transfer the image data written in the A-buffer memory 101 in the previous line at 06, a read address signal RAD instructing to read from the first pixel is set. As a result, the image data SD written in the A-buffer memory 101 in the previous line is sequentially read out and transferred to the personal computer PC via the selectors 112, 113 and the data bus 114.

In this way, two buffer memories 10
1 and 102 are alternately switched for each line in the main scanning direction to read and write image data from the handy scanner, thereby transferring document image data read by the handy scanner to the personal computer PC at high speed.

[0021]

However, in the above conventional configuration, four buffer memories 101 to 104 are used to read and write image data SD.
Three address counters 105, 107, 108 and one address register 106 are used to generate these address signals. Therefore, there are problems in that the number of buffer memories and address counters is large, the circuit configuration becomes complicated, and the cost increases.

[0022] Furthermore, in the personal computer PC,
Since the read address signal RAD is set in the address register 106 to transfer the image data SD at a desired pixel position, it is necessary to manage the address of the image data SD to be transferred, reducing the burden on software spent on address management. The problem is that it's big.

[0023] Furthermore, when it is required to transfer binarized image data to a personal computer PC, there is a problem that a binarization function cannot be easily added.

A first object of the present invention is to reduce the number of storage means for storing image data and address counters;
An object of the present invention is to provide an image processing device that can eliminate the need for address management in an external personal computer or the like.

A second object of the present invention is to provide an image processing device in which a binarization function can be easily incorporated.

[0026]

[Means for Solving the Problems] In order to achieve the first object, the present invention provides an AD converter that converts an image signal obtained by scanning an original image into image data consisting of a plurality of bits; A first memory block that temporarily stores image data output from the AD converter, and second and third memory blocks that store correction values for normalizing the white level and black level of the image signal. write address signal generation for outputting an address signal for writing image data output from the AD converter into a first memory block of the first and second storage means; means, read address signal generating means for generating a read address signal for reading image data written in the first memory block of the first and second storage means, and read/write operations for image data of a predetermined number of pixels. a memory switching means for switching one of the first memory blocks of the first and second storage means to a reading state and the other to a writing state; A correction value for normalizing the white level and black level is read from the address specified by the current write address signal among the second and third memory blocks of the first or second storage means, and
control means for inputting a conversion reference value into the D converter; and a control means for inputting the image data read from the first memory block of the first or second storage means switched to the read state by the memory switching means to the outside. I tried to transfer it.

Further, in order to achieve the second object, the present invention includes an AD converter that converts an image signal obtained by scanning an original image into image data consisting of a plurality of bits; a first memory block that temporarily stores image data to be output; second and third memory blocks that store correction values for normalizing the white level and black level of the image signal; first and second storage means comprising a fourth memory block storing a binarization slice level for binarization; and image data output from the AD converter are stored in the first and second memory blocks. write address signal generation means for outputting an address signal for writing into a first memory block of the storage means;
read address signal generating means for generating a read address signal for reading image data written in the first memory block of the second storage means; 1st, 2nd
a memory switching means for switching one of the first memory blocks of the storage means to a read state and the other to a writing state; a binarization means for binarizing image data output from the AD converter; The second storage means of the first or second storage means is in a writing state by the storage means.
, a correction value for normalizing the white level and black level and a binarization slice level are read from the address specified by the current write address signal among the third and fourth memory blocks, and the correction value is read from the address specified by the current write address signal. a first control means that causes the converter to input the conversion reference value, and inputs the binarization slice level to the binarization means as the binarization reference value;
in the binarization mode, a second control means for writing the binarized image data output from the binarization means into the first memory block instead of the image data output from the AD converter; The image data read out from the first memory block of the first or second storage means which is switched to the read state by the memory switching means is transferred to the outside.

The write address signal and the read address signal each consist of an upper address signal and a lower address signal, and the upper address signal specifies the first to fourth memory blocks, and the lower address signal specifies a predetermined number of pixels. It is preferable to have a configuration in which addresses corresponding to image data are sequentially specified.

Further, it is preferable that the upper address signal goes around once in one pixel period.

Furthermore, it is preferable that the binarized image data is written in units of a plurality of pixels to each address of the first memory block.

Furthermore, the write address signal is updated at a cycle corresponding to the image reading speed of a reading device that reads the original image, and the read address signal is updated at a cycle corresponding to the image reading speed of an external image utilization device. A configuration like this is preferable.

[0032]

[Operation] According to the configuration of the first invention, there is a memory for temporarily storing image data output from the AD converter, and a memory for storing correction values for normalizing the white level and black level of the image signal. are organized into blocks and aggregated into two storage means, and data in these memories is read and written by a write address signal and a read address signal generated from a write address signal generating means and a read address generating means.

Therefore, the number of memories and address counters for reading and writing image data is reduced, and an external personal computer or the like only manages the number of image data transfers and does not need address management.

Further, according to the configuration of the second invention, the memory storing the binarization slice level for binarizing the image data is further divided into blocks and consolidated into two storage means, and the binarization Since the data binarized according to the slice level is stored in the first memory block, the binarization function can be easily incorporated.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. <Configuration> FIG. 1 is an overall block diagram showing the input/output relationship of the image processing device according to the present invention. A handy scanner 2 is connected to the input side of the image processing device 1, and an image utilization device is connected to the output side. A personal computer PC is connected.

The handy scanner 2 includes a light emitting element 4 that serves as a light source for illuminating the image forming surface of the document, and a photo interrupter 5 that detects the amount of rotation of the roller when sliding on the image forming surface of the document.
, a line pulse L indicating that one line has advanced in the sub-scanning direction based on the output pulse signal of this photointerrupter 5.
A line pulse circuit 6 that outputs P, a reading start button 7 that is operated when starting inputting the original image, and a CCD sensor (image sensor) 9 consisting of a plurality of pixels lined up in the main operation direction of the original image are activated one pixel at a time. a CCD driver 8 that drives the CCD sensor 9, an amplifier 10 that amplifies the output signal of each pixel of the CCD sensor 9 and supplies it to the image processing device as an image signal VS, a line pulse LP output from the line pulse circuit 6, and a reading start button 7. Based on the reading start signal ST output from the line pulse LP
, a reading start switch signal SSW, a reading start signal SP in the main scanning direction, and a timing signal WR representing each pixel reading timing.
It consists of

On the other hand, the image processing device 1 and the personal computer PC have a data bus 12 and an address bus 1.
3 and other control signal lines, and the control signals include a reset signal RES, a signal IORD that instructs reading or writing of data appearing on the data bus,
IOWR, signal for transferring image data to the internal memory of personal computer PC in direct memory access format DMARQ (DMA request signal), DM
There are AACK (DMA enable signal) and IREQ (interrupt request signal).

2 to 4 are diagrams showing the detailed configuration of the handy scanner 2, FIG. 5 is a block diagram showing the detailed configuration of the image processing device 1, and FIG. 6 is a diagram showing the detailed configuration of the control circuit 56 in FIG. FIG. 2 is a block diagram showing the configuration.

First, as shown in the figures, the handy scanner 2 shown in FIGS. 2 to 4 has an exterior formed of a lower cover 14 and an upper cover 15, so that it is possible to input as wide an image as possible, and it is easy to grip. For ease of operation, the width of the grip 16A is narrow and the width of the head 17B is wide.

As shown in FIG. 3, the lower cover 14 includes a rib 18 that contacts an image to be read, for example, a document P, a reading opening 19 (image reading opening window), and a reading opening 19.
A transparent cover 20 that covers the roller 9, an arc-shaped shielding cover 22 that houses the roller 21, and a plurality of ribs 23 are provided.

The upper cover 15 is provided with a viewing window 24 through which the state of the document P can be seen through the reading port 19, and a diagonal protrusion 25 formed on the rear periphery of the viewing window 24.

The viewing window 24 is covered with colored (smoked) translucent glass or synthetic resin 26 such as acrylic. When looking through the viewing window 24, for example, the roller 2
The reading reference position is set at a position that can be seen tangentially forward A of the arc-shaped shielding cover 22 that houses the sensor 1.

[0043] The handy scanner 2 having such a shape is
A roller 21 made of rubber or the like that contacts the original P and rotates around a rotation shaft 27, and a light source that irradiates light onto the original P, such as a light emitting element (LED array) that emits green light (or red light, etc.). ) 4, a reflection plate 29 such as a mirror that reflects light from the original P, an image input unit 30 that inputs the light from the reflection plate 29 and converts the light into an electrical signal, and a reading start button 7. A control board 31 is provided.

[0044] The roller 21 is provided between the LED array 4 and the image input section 30, and is arranged between the reflection plate 29 and the image input section 30.
It is lower than the optical path L between the LED array 4 and the entrance of the image input section 30, and projects higher than the straight line connecting the LED array 4 and the entrance of the image input section 30, and focuses on the document surface. It is designed to rotate.

As shown in FIG. 4, a gear 28 is attached to the rotating shaft 27 of the roller 21, and the clock plate 36 is driven via the gears 32 and 33 as the roller 21 rotates.

The clock plate 36 is provided with a plurality of holes equally spaced on a concentric circumference, and the amount of rotation is detected by a photo interrupter, and the amount of movement of the handy scanner 2 sliding on the document is detected by manual operation. It is designed to be detected as a position signal.

The LED array 4 and the reflection plate 29 are attached to a frame 37 that is inclined at, for example, 45 degrees with respect to the original P, as shown in FIG.

The image input unit 30 includes a lens unit 38 that collects light from the reflection plate 29, and a lens unit 38 that collects light from the reflection plate 29.
It is provided with a photoelectric conversion element, such as a CCD sensor 9 (image sensor), which receives the light focused by 8 and converts it into an electrical signal.

When the reading start button 7 is pressed, the position signal from the clock plate 36 is detected, and the reflected light from the document P input from the reading port 19 is synchronized with this position signal. The image is input to the CCD sensor 9 of the image input section 30 via the reflection plate 29, and the image on the document P is photoelectrically converted by the CCD sensor 9.

Next, the configuration of the image processing apparatus shown in FIG. 5 will be explained.

The image processing device 1 of this embodiment includes an amplifier 50 that amplifies the image signal VS output from the handy scanner 2, and converts the image signal VS amplified by the amplifier 50 into image data SD consisting of a plurality of bits. A-buffer memories 52 and 53 that temporarily store the image data SD output from the AD converter 51 alternately for each line in the main scanning direction, and the white level and black level of the image signal VS. A DA converter 54 converts the correction value SHD for normalizing into analog correction signals HSW and HSB.
, 55, and address signals BF・ADA and BF・A for writing and reading image data SD output from the AD converter 50 into and from the A and B buffer memories.
At the same time as outputting DB, each time the read/write operation of one line of image data (image data of a predetermined number of pixels) SD in the main scanning direction is completed, the A and B buffer memories 52 and 53
A control circuit 56 is provided for performing control such as switching one side to a read state and the other to a write state.

Further, there is a scanner power supply circuit 57 for driving the light emitting element 4 of the handy scanner 2 to blink under control from the control circuit 56, and a scanner power supply circuit 57 for transmitting and receiving image data SD and the like to and from the personal computer PC via the data bus 12. bus buffer 58 and address bus 1
An address decoder 59 that decodes a 10-bit address signal (A9 to A0) input from the personal computer PC via the PC 3 and the personal computer PC transfers image data SD, etc. in direct memory access format (DMA format ).

Here, the A and B buffer memories 52 and 53
As shown in FIG. 7, there is a memory block MB4 which temporarily stores the image data SD output from the AD converter 51 alternately for each line in the main scanning direction, and a memory block MB4 which normalizes the white level and black level of the image signal VS. Correction values HDW, HD to
The memory block MB1 and MB2 that store the image data SD and the memory block MB3 that stores the binarized slice level data SLD for binarizing the image data SD are provided.

As shown in FIG. 6, the control circuit 56 includes address counters 70 and 71, an address selector 72, a comparator 73, a shift register 74, a data selector 75, a controller 76, an address decoder 77, and a timing generator. It consists of section 78.

The address counter 70 outputs a write address signal WAD for writing image data SD into the A buffer memory 52 and the B buffer memory 53, and can specify a pixel address for one line in the main scanning direction. It is composed of an address counter section 70A and an upper address section 70B that specifies memory blocks MB1 to MB4.
The upper address section 70B is incremented by an increment signal ICW synchronized with one pixel period output from the controller 76, and the upper address section 70B is
Memory block specification data MBS that sequentially specifies MB4
Updated by W.

The address counter 71 receives a read address signal RAD for reading out the image data SD written in the A buffer memory 52 and the B buffer memory 53.
An address counter section 71A that can specify pixel addresses for one line in the main scanning direction and an upper address section 7 that specifies memory blocks MB1 to MB4.
1B, and the address counter section 71A receives an increment signal ICR output from the controller 76.
The upper address part 71B is updated by memory block designation data MBSR that sequentially designates memory blocks MB1 to MB4 from the controller 76.

The address selector 72 outputs the write address signal WAD (including the upper address) output from the address counter 70 and the read address signal RAD (including the upper address) output from the address counter 71 from the controller 76. A write address signal WAD is supplied as memory address signals BF and ADA to the A buffer memory 52 (or B buffer memory 53) in the write state, and the B buffer memory in the read state is selected by the select control signal SLM. 53 (or the A buffer memory 52), the read address signal RAD is supplied as the memory address signal BF/ADB.

Here, the address values of the address counter units 70A and 70B of the address counter 70 are set to the value "0" corresponding to the first pixel of one line by a clear signal (not shown) at the start of reading the original image in the main scanning direction. is set to 1, and then set to 1 by the increment signal ICW.
It is controlled by the controller 76 so that it changes to the value "n" corresponding to the final pixel by updating at the pixel period.

On the other hand, the address value of the address counter section 71A of the address counter 71 is updated in units of 8 pixels. This update is performed by an increment signal ICR, which is output from the controller 76 every time the personal computer PC sends an image data transfer command.

Furthermore, the upper address values output from the upper address sections 70B and 71B of the address counters 70 and 71 are changed during one pixel period as shown in the time chart of FIG. 8 by the memory block designation data MBSW and MBSB. The controller 76 updates the memory blocks MB1, MB2, MB3, and MB4 in the order of MB1, MB2, MB3, and MB4. This high-order address value is added to the high-order address value output from the address counter sections 70A and 71A, and the write address signal WAD,
Address selector 72 as read address signal RAD
is input. As a result, memory blocks MB1 to M
B4 is designated in a time-division manner during one pixel period.

Further, the selector control signal SLM input to the data selector 72 is controlled by the controller 76 as shown in FIG.
As shown in the time chart, the signal is switched to "0" or "1" for each line, and the write address signal WAD and read address RAD are alternately supplied to the A buffer memory 52 and the B buffer memory 53 for each line. It has become.

Next, the comparator 73 connects the AD converter 5
It binarizes the image data SD output from 1.
The slice level data SLD for binarization is provided from the third memory block MB3 of the buffer memory 52 or 53 which is in the writing state. This comparator 73 is a personal computer PC.
Binarization is performed only when the binarization mode is specified to transfer the binarized image data from SD2, and when the binarization mode is not specified, the image data input from the AD converter 51 is The image data SD is output as is.

The shift register 74 has a comparator 73
When the binarization mode is specified, the binarized image data SD2 of 1 bit per pixel is temporarily stored.
At the time when the binarized image data SD2 for pixels is stored,
These are collectively transferred to the A buffer memory 52 or B buffer memory 53 in the writing state via the buffer data bus BF/ADA or BF/ADB.

The data selector 75 selects a data transfer route between the AD converter 51, the A and B buffer memories 52 and 53, and the personal computer PC, and selects the data transfer route between the A and B buffer memories 52 and 53 and the personal computer PC.
Image data S for (or B buffer memory 53)
D is transferred via the AD converter 51 → data selector 75 → buffer data bus BF/ADA (or BF/ADB). Conversely, the image data SD (binarized image data SD2 in the case of binarization mode) read from the B buffer memory 53 (or A buffer memory 52) which is in the read state is transferred to the B buffer memory 53. (or A buffer memory 52)→data selector 75→bus buffer 58→personal computer PC.

Various command data from the personal computer PC are transferred to the controller 76 via the data selector 75, and status signals etc. output from the controller 76 are transferred to the data selector 75 and the bus buffer 5.
8 to the personal computer PC.

Next, the controller 76 determines the operating state of the handy scanner 2 based on the timing signal WR, reading start signal SP, reading start switch signal ST, and line pulse LP input from the handy scanner 2.
It switches the reading and writing states of the A buffer memory 52 and B buffer memory 53, updates the address counters 70 and 71, and switches the data transfer path of the data selector 75 depending on the operating state.
A write enable signal WEA is output when the A-buffer memory 52 is placed in a write state, and a read enable signal OEA is output when the A buffer memory 52 is placed in a read state. Furthermore, when the B buffer memory 53 is placed in a write state, a write enable signal WEB is output, and when placed in a read state, a read enable signal OEB is output.

Next, the address decoder 77 decodes the lower address bits A3 to A1 of the address signal on the address bus 13 of the personal computer PC, and the terminal data read signal IORD outputted from the personal computer PC is transmitted to the image processing apparatus. 1, and if it is for the own device 1, the data sent to the data bus 12 in synchronization with the signal IORD is retrieved and examined, and the data requests the transfer of various status signals. If it is a request to transfer various status signals of the handy scanner 2, a signal indicating that is sent to the controller 76, and the controller 7
6 to transfer various status signals through the data selector 75 and the data bus 12. In addition, image data S
If the transfer of data D is requested, a signal indicating this is given to the controller 76, the address counter 71 is started, and the image data SD of the A buffer memory 52 or the B buffer memory 53 which is in the read state is read out. start.

In this case, the address decoder 77
It is activated by the terminal data read signal IORD selectively output as the chip select signal CS from the selector 79 of the A control circuit 60, and the address bit A
Decipher 3-A1. Here, the various status signals include whether the reading operation of the handy scanner 2 has started,
This indicates whether reading of one line has been completed. Note that, when the terminal data read signal IORD is for the selector 79, the selector 79 selectively outputs the signal IORD as a chip select signal CS based on the output signal of the address decoder 59 that decodes address bits A9 to A4 and A0. .

On the other hand, various command data specifying the binarization mode, etc. are inputted from the personal computer PC to the controller 76 through the data selector 75, and are read into the controller 76 and processed by the terminal data write signal IOWR. In this case, various command data include the idle time between the end of reading one line and the start of reading the next line, that is, the idle time until the reading start signal SP of the next line is generated. A buffer memory 5 which was in the writing state at
2 (or B buffer memory 53) to the read state, and vice versa, the B buffer memory 53 (or B buffer memory 53) which was in the read state
Also included is a memory state switching command for switching the A-buffer memory 52) to a write state.

The timing generator 78 outputs various timing signals necessary for image data read/write operations and transfer operations.

Next, the DMA control circuit 60 of FIG.
is for transferring the data of the original image read by the handy scanner 2 to the personal computer PC at high speed, and the address bit A on the lower side of the address bus 13
3-A1, terminal data read signal IORD, and DM indicating that data can be accepted by DMA transfer.
A acknowledge signal DMAACK is input from the personal computer PC. Further, from the control circuit 56, a DMA transfer enable signal DMAOK indicating that data transmission by DMA transfer is possible is input. And on the personal computer PC side,
DMA request signal DMARQ, interrupt request signal IREQ
A direct access signal DAC is output to the control circuit 56 side to inform that the A buffer memory 52 or the B buffer memory 53 will be directly accessed.
S, a counter clear signal DCLR for clearing the address counter 71, a terminal data read signal IOR, and a select signal CS are output.

Note that the slice level data SLD for binarization and the correction data HDW, HDB for shading correction are written in advance from the personal computer PC.

<Operation> Next, the operation related to the above configuration will be explained.

(1) Reading operation of various data from personal computer PC As mentioned above, in the image processing apparatus 1 of this embodiment, before reading the original image, the white level and black level of the image signal VS are normalized. The correction values HDW and HDB to
, B buffer memory 52, 53 memory block MB1
．． It is necessary to write it to MB2. Furthermore, it is necessary to write binarized slice level data SLD for binarizing the image data SD into the memory block MB3 of both buffer memories 52 and 53. Further, when transferring the binarized image data SD2 to the personal computer PC side, it is necessary to instruct the controller 76 with command data instructing the binarization mode. Also, 1
When the line image reading is completed, the two buffer memories 52 and 53 are changed from the writing state to the reading state.
Alternatively, it is necessary to instruct the device to switch from the read state to the write state.

Therefore, these data are sent from the personal computer PC and stored or instructed in the following manner.

That is, the correction values HDW and HDB are
Memory blocks MB1 and M of buffer memories 52 and 53
When writing to B2, the personal computer PC:
The output of address counter 71 is A, B buffer memory 5
2 and 53, command data instructing this is sent to the data bus 12, and in synchronization with this, a terminal data write signal IOWR is output. Then, this command data is read into the controller 76 via the data selector 75. Then, the controller 76 sends a select control signal SLM to the address selector 72 so that the output of the address counter 71 is connected to the A and B buffer memories 52 and 53 according to the read command data.
Enter. As a result, the output of the address counter 71 is connected to the A and B buffer memories 52 and 53.

Next, personal computer PC sends command data for specifying memory block MB1 in the same manner as described above, and causes controller 76 to read it. Then, the controller 76 outputs memory block designation data MBSR that selects the memory block MB1 according to the read command data. As a result, the upper address portion 71B of the address counter 71 is set with the upper address value "0" indicating the memory block MB1. At this stage, the address corresponding to the first pixel of memory block MB1 is designated.

Next, the personal computer PC
, B buffer memories 52 and 53 are sent in the same manner as described above, and read by the controller 76. Then, the controller 76 reads the A and B buffer memories 52 and 53 according to this command data.
The write enable signal W is set to write state.
Output EA and WEB. As a result, the A and B buffer memories 52 and 53 enter the write state. Next, the personal computer PC sends the correction value HDW of the first pixel to the data bus 12, and at the same time sends the terminal data write signal IOWR. This correction value HDW is applied to the buffer data buses BF, DA and BF by the data selector 75.
・Sent to DB. As a result, the correction value HDW for the first pixel is written to the address corresponding to the first pixel of the memory block MB1 of the A and B buffer memories 52 and 53.

After writing the correction value HDW for the first pixel in this way, the correction value HDW for the second pixel is then written.
In order to write W, the personal computer PC transmits data instructing update of the write address to the data bus 12.
and causes the controller 76 to read it. Then,
The controller 76 sends an increment signal ICR to the address counter section 71A of the address counter 71 in accordance with this data. As a result, the address value of the address counter section 71A is updated by "1" address, and A
, the address corresponding to the second pixel of the memory block MB1 in the B buffer memories 52 and 53 is designated. Therefore, the personal computer PC
The correction value for the pixel is sent to the data bus 12 and stored in the memory block MB1 in the same manner as the correction value HDW for the first pixel. Thereafter, correction values HDW up to the final pixel are written in the same manner.

The correction value HDB for black level correction is the same as above, except that the designation of the memory block is different.

Note that the address counter 71 is normally used for reading out the image data SD, but the address counter 71 is used for reading out the image data SD.
This is used when writing DB or binary slice level data SLD. Of course, the address counter 70 may also be used.

Next, the binarized slice level data SLD
Writing is performed in the same manner as described above, with the only difference being the designation of the memory block and the content of the data.

Next, the case of specifying the binarization mode will be explained. In this case, the personal computer P
C sends out command data specifying the binarization mode, and at the same time outputs a terminal data write signal IOWR. The controller 76 that has read this command data switches the comparator 73 to an active state. This makes it possible to binarize and output the image data SD.

Next, the case of switching the read/write status of the A buffer memory 52 and the B buffer memory 53 will be explained. In this case, the personal computer PC confirms that reading in the main scanning direction has been completed and then issues a reading start signal for the next line. During the idle time until SP is generated, command data instructing the switching of the read/write state is sent to the data bus 12, and at the same time, the terminal data write signal IOWR is output. The controller 76 that has read this command data switches between select and control signal SLM. Also, read enable signals OEA, OEB and write enable signals WEA, WEB are switched to opposite sides, respectively. This switches the read/write status of the A buffer memory 52 and the B buffer memory 53.

(2) Image reading operation When the pre-processing necessary for image reading is completed as described above, the power to the handy scanner 2 is turned on, and the reading start button 7 is turned on, the buffer circuit of the handy scanner 2 is turned on. A reading start switch signal ST is output from 11. Note that when the power of the image processing device 1 is turned on, the controller 56 of the image processing device 1 switches the power ON/OFF signal to ON, puts the scanner power circuit 57 into an operating state, and drives the light emitting element 4 to emit light. Outputs signal LD. As a result, the light emitting element 4 emits light, illuminating the surface of the document.

In this state, when the handy scanner 2 is moved along the surface on which the image of the original to be read is formed,
The roller 21 starts rotating at a speed corresponding to the moving speed. Along with this, the clock plate 36 begins to rotate. As the clock plate 36 rotates, the line pulse LP is outputted from the line pulse circuit 6. Further, when the reading start button 7 is turned on, the buffer circuit 11 drives the CCD driver 8 and the CCD sensor 9
are made active in order from the first pixel. And this CC
In synchronization with the driving of the D sensor 9, the timing signal WR of one pixel period starts to be output. As a result, photoelectric conversion in the main scanning direction is started, and the signal VS of the read image is output in order from the first pixel.

On the other hand, the personal computer PC puts the A buffer memory 52 in the write state and the B buffer memory 53 in the read state during the idle time until the first read start signal SP is generated. Furthermore, the two address counters 70 and 71 are reset, and the lower address value is set to specify the first pixel. Furthermore, regarding the address counter 70 that outputs the write address signal WAD, the upper address value is set to specify the first pixel. specify.

In this state, when the first image signal VS is input to the AD converter 51 via the amplifier 50 and the timing signal WR synchronized with this is input to the controller 76, the controller 76 The A buffer memory 5 which is in the writing state in the pixel period
The read enable signal OEA and write enable signal WEA for No. 2 are switched in a time-division manner as shown in FIG. Furthermore, as shown in FIG. 10, the upper address values of the address counter 70 are set to "0", "1", "2",
Switch in time division in the order of "3".

As a result, the white level correction value HDW is used in the first time slot T1 of one pixel period, the black level correction value HDB is used in the second time slot T2, and the binarization value is used in the third time slot T3. Slice level data S
LD is read. and the fourth time slot T
4, writing of the image data SD is instructed by the write enable signal WEA becoming active only in this time slot T4.

Therefore, the correction value HDW of the first pixel is read out from the memory block MB1 in the first time slot T1, and the correction value HDW of the first pixel is read out from the memory block MB1 in the second time slot T2.
When the correction value HDB is read from 2, the controller 7
6 transfers these correction values to the bus buffer data buses BF and D.
A, DA converters 54, 55 through data selector 75
Transfer to. Then, the DA converters 54 and 55 convert these correction values HDW and HDB into corresponding analog level correction signals HSW and HSB, and supply them to the AD converter 51 as conversion reference voltages. Thereby, the AD converter 51 converts the image signal VS input from the handy scanner 2 into digital image data SD based on these correction signals HSW and HSB. That is, the image signal VS is the first,
The data is corrected by shading in the second time slots T1 and T2 and output as image data SD.

This image data SD is sent to the data selector 75.
, and are input to the A buffer memory 52 via buffer data buses BF and DA. This image data SD is written to the address corresponding to the first pixel of the memory block MB4 of the A buffer memory 52 by the write enable signal WEA in the fourth time slot T4.

In this way, the image data SD of the first pixel
When writing is completed, the controller 76 outputs the increment signal ICW, updates the lower address value of the address counter 70 by "1", and then writes the increment signal ICW corresponding to the second pixel of the memory blocks MB1 to MB4 of the A buffer memory 52. Controls the address specified. This switches to the writing state of the image data SD of the second pixel. Then, in the same manner, the image data SD up to the final pixel n is transferred to the memory block M of the A buffer memory 52.
Written to B4.

Then, the first line of image data SD
When the writing is completed, the personal computer PC
sends command data for switching the reading and writing states of the two buffer memories 52 and 53 to the controller 76 until the next read start signal SP for the second line is generated, and until now they have been in the writing state. A
The buffer memory 52 is switched to the read state, and the B buffer memory 53, which was in the write state, is switched to the write state.

Furthermore, the output of the address counter 70 is connected to the B buffer memory 53 which has newly entered the write state, and the output of the address counter 71 is connected to the A buffer memory 52 which has entered the read state. The address selector 72 is switched so that and,
In the same way as above, the two address counters 70 and 71 are reset so that the lower address value specifies the first pixel, and for the address counter 70 that outputs the write address signal WAD, the upper address value is set to specify the first pixel. Specify block MB1 and read address signal RA
The address counter 71 that outputs D is set to specify memory block MB4.

In this state, when the first image signal VS of the second line is input to the AD converter 51 and the timing signal WR synchronized with this is input to the controller 76, the controller 76 The read enable signal OEB and write enable signal WEB for the B buffer memory 53 which is in the write state in the period are switched in a time division manner as shown in FIG. Furthermore, the upper address value of the address counter 70 is shown in FIG.
As shown in 0, the time division switching is performed in the order of "0", "1", "2", and "3".

As a result, the image data of the first pixel of the second line is written to the address corresponding to the first pixel of the memory block MB4 of the B buffer memory 53 in the same manner as described above.

On the other hand, since the first line of image data SD has already been written in the A buffer memory 52 which is in the read state, the personal computer PC transfers this data SD to the personal computer PC side by writing the terminal data. A read signal IORD is output, and the lower address value of the address counter 71 is sequentially updated through the controller 76. This update is performed in units of 8 addresses using one terminal data read signal IORD. Therefore, in order to transfer the image data SD up to the final pixel n, n/8 terminal data read signals IORD must be output. In this case, the output cycle of the signal IORD is relative to the timing signal WR of the handy scanner 2.
It is asynchronous. That is, writing of the image data SD is executed at a speed corresponding to the image reading speed of the handy scanner 2, and transfer to the personal computer PC is executed at an original speed determined by the personal computer PC.

In this way, read address signal RAD
is updated, the image data SD stored in the A buffer memory 52 is read out, and the data selector 7
5, the data is transferred to the personal computer PC via the bus buffer 58 and the data bus 12.

Thereafter, image data SD is written in each main scanning line and transferred to the personal computer PC in the same manner. Then, when the movement of the handy scanner 2 on the document surface stops, reading of the document image is completed.

(3) Binarization mode When the binarized image data SD2 is to be transferred to the personal computer PC, the personal computer PC provides command data specifying the binarization mode to the controller 76, as described above. As a result, controller 7
6 supplies the binarized slice level data SLD read from the memory block MB3 to the comparator 73 at the third time slot T3 to binarize the image data SD. This binarized image data SD2 is temporarily stored in the shift register 74, and when eight pixels are collected, it is written to the memory block MB4 of the A buffer memory 52 or B buffer memory 53 in the writing state.

The binary image data SD2 thus written is read out in the next line and transferred to the personal computer PC.

(4) DMA transfer mode The image data SD described above is transferred to the personal computer PC by reading the image data SD written into the other buffer memory as terminal data while one buffer memory is writing. The signal IORD was read out by outputting it in units of 8 pixels and transferred to the personal computer PC, but the DMA transfer command was
In the DMA transfer mode, one line of image data is read by only outputting the data once. This DMA transfer mode is
The DMA control circuit 60 is instructed.

[0103] When the DMA transfer mode is specified, the DMA
The control circuit 60 generates a select signal CS and a direct access signal DACS, and after informing the controller 76 that direct access is to be started, outputs a counter clear signal DCLR, and the address counter 71
Reset. After this, the terminal data read signal IO
R is input to the controller 76 at a high-speed cycle, the controller 76 outputs an increment signal ICR at a high-speed cycle, and the address counter 71 outputs a read address signal RAD that changes at a high-speed cycle from the first pixel to the nth pixel of one line. let As a result, the A buffer memory 52 or B buffer memory 53 which is in the read state
The image data SD is read out at high-speed intervals from the data selector 75 and transferred to the personal computer PC via the data selector 75. After this transfer operation, the two buffer memories 52
, 53 are switched.

[0104] By providing a DMA transfer mode in this way, a personal computer PC capable of performing a DMA transfer operation can output a DMA transfer command once during the idle time between the line and the next line. By simply doing this, one line of image data can be transferred at high speed. This reduces the burden on personal computers,
Moreover, even when the amount of image data is large, it is possible to process the image data in a short time.

<Modifications> The present invention is not limited to the above-mentioned embodiments, and for example, the following modifications are possible. (1) In this embodiment, a function to binarize and transfer the image data SD is provided, but this may be added as necessary. (2) A dither mode may be provided instead of the binarization mode, and dithered image data may be transferred.

[0106]

As explained above, according to the configuration of the first aspect of the present invention, there is provided a memory for temporarily storing image data output from an AD converter, and a memory that normalizes the white level and black level of the image signal. A memory for storing correction values for the conversion is divided into blocks and aggregated into two storage means, and the data in these memories is generated by the write address signal and read address generated from the write address signal generation means and the read address generation means. Since it is configured to read and write using signals, the number of memories and address counters for reading and writing image data is reduced, and an external personal computer, etc. only manages the number of transferred image data, and does not require address management. become. As a result, the burden on an image utilization device such as a personal computer can be reduced.

Further, according to the configuration of the second invention, the memory storing the binarization slice level for binarizing image data is further divided into blocks and consolidated into two storage means, and the binarization Since the data binarized according to the slice level is stored in the first memory block, the binarization function can be easily incorporated.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram showing the input/output relationship of an image processing apparatus according to the present invention.

FIG. 2 is a perspective view of the handy scanner seen from above.

FIG. 3 is a perspective view of the handy scanner seen from the bottom side.

FIG. 4 is a side sectional view of the handy scanner.

FIG. 5 is an overall configuration diagram of an image processing device.

FIG. 6 is a detailed configuration diagram of a control circuit of the image processing device.

FIG. 7 is an internal configuration diagram of two buffer memories.

FIG. 8 is a time chart for explaining a method of specifying memory blocks of a buffer memory.

FIG. 9 is a time chart for explaining a method of switching to a read/write state of a buffer memory.

FIG. 10 is a time chart for explaining read/write operations of memory blocks of a buffer memory.

FIG. 11 is a block diagram showing the configuration of a conventional image processing device.

[Explanation of symbols]

1...Image processing device 2...Handy scanner 7...Reading start button 9...CCD sensor PC...Personal computer 30...Image input section 36...Clock board 51...AD converter 52...A buffer memory 53...B buffer memory 54...DA converter 55...DA converter 56...Control circuit 60...DMA control circuit 70...Address counter 71...Address counter 72...Address selector 73...Comparator 74...Shift register 75...Data selector 76...Controller MB1...Memory block MB2...Memory block MB3…Memory block MB4…Memory block WAD...Write address signal RAD...Read address signal

Claims (9)

[Claims] 1. An AD converter that converts an image signal obtained by scanning a document image into image data consisting of multiple bits;
A first memory block that temporarily stores image data output from this AD converter, and second and third memory blocks that store correction values for normalizing the white level and black level of the image signal. first and second storage means consisting of; and image data output from the AD converter;
, write address signal generation means for outputting an address signal for writing into the first memory block of the second storage means, and image data written to the first memory block of the first and second storage means. A read address signal generating means generates a read address signal for reading, and one of the first memory blocks of the first and second storage means reads out each time a read/write operation of image data of a predetermined number of pixels is completed. The other is a memory switching means that switches to a writing state, and the second and third memory blocks of the first or second storage means that are in a writing state by this memory switching means are designated by the current write address signal. control means for reading a correction value for normalizing the white level and black level from the address and inputting it to the AD converter as a conversion reference value,
An image processing apparatus configured to externally transfer image data read from a first memory block of the first or second storage means which is switched to a read state by the memory switching means. 2. The write address signal and the read address signal each consist of an upper address signal and a lower address signal, the upper address signal specifies the first to third memory blocks, and the lower address signal specifies a predetermined number of pixels. 2. The image processing apparatus according to claim 1, wherein the image processing apparatus sequentially specifies addresses corresponding to the image data. 3. The image processing apparatus according to claim 2, wherein the upper address signal goes around once in one pixel period. 4. The write address signal is updated at a cycle corresponding to the image reading speed of a reading device that reads the original image, and the read address signal is updated at a cycle corresponding to the image reading speed of an external image utilization device. An image processing apparatus according to any one of claims 1 to 3. 5. An AD converter that converts an image signal obtained by scanning an original image into image data consisting of multiple bits, and a first memory block that temporarily stores the image data output from the AD converter. and a second memory storing correction values for normalizing the white level and black level of the image signal.
, a third memory block, and a fourth memory block storing a binarization slice level for binarizing the image data; and the AD
write address signal generation means for outputting an address signal for writing image data output from the converter into a first memory block of the first and second storage means; a read address signal generating means for generating a read address signal for reading out the image data written in the first memory block; a memory switching means for switching one of the first memory blocks of the storage means to a read state and the other to a writing state; a binarization means for binarizing the image data output from the AD converter; and the memory switching means. The white level and black level are normalized from the address specified by the current write address signal among the second, third, and fourth memory blocks of the first or second storage means that are in the write state. A correction value and a binarization slice level are read out, the correction value is inputted to the AD converter as a conversion reference value, and the binarization slice level is inputted to the binarization means as a binarization reference value. and a second controller for writing binary image data outputted from the binarization means into the first memory block in place of the image data outputted from the AD converter in the binarization mode. control means, and is adapted to externally transfer image data read out from a first memory block of the first or second storage means switched to a read state by the memory switching means. . 6. The write address signal and the read address signal each consist of an upper address signal and a lower address signal, the upper address signal specifies the first to fourth memory blocks, and the lower address signal specifies a predetermined number of pixels. 6. The image processing apparatus according to claim 5, wherein the image processing apparatus sequentially specifies addresses corresponding to the image data. 7. The image processing apparatus according to claim 5, wherein the upper address signal goes around once in one pixel period. 8. The image processing apparatus according to claim 5, wherein the binary image data is written in units of a plurality of pixels to each address of the first memory block. 9. The write address signal is updated at a cycle corresponding to the image reading speed of a reading device that reads the original image, and the read address signal is updated at a cycle corresponding to the image reading speed of an external image utilization device. An image processing apparatus according to any one of claims 5 to 8.