JPH04246840A - Ic mounting method - Google Patents

Ic mounting method

Info

Publication number
JPH04246840A
JPH04246840A JP3011869A JP1186991A JPH04246840A JP H04246840 A JPH04246840 A JP H04246840A JP 3011869 A JP3011869 A JP 3011869A JP 1186991 A JP1186991 A JP 1186991A JP H04246840 A JPH04246840 A JP H04246840A
Authority
JP
Japan
Prior art keywords
chip
conductive adhesive
mounting method
circuit substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3011869A
Other languages
Japanese (ja)
Inventor
Toshiaki Takenaka
敏昭 竹中
Hikari Fujita
光 藤田
Akiyoshi Kawazu
河津 明美
Kunio Kishimoto
邦雄 岸本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3011869A priority Critical patent/JPH04246840A/en
Publication of JPH04246840A publication Critical patent/JPH04246840A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743Apparatus for manufacturing layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743Apparatus for manufacturing layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To provide the title IC mounting method of stable electrical connection solving the problem of defective connection due to the minor gap between the IC chip and a circuit substrate in relation to the connecting method of the IC chip applicable to electronic equipment to the circuit substrate such as liquid crystal panel, etc. CONSTITUTION:A spacer 6 thicker than the bump contacts 2 of an IC chip 1 is fixed between the IC chip 1 and a circuit substrate 5 using a bonding agent and then the bump contacts 2 of the IC chip 1 coated with a conductive bonding agent 4 and the electrode terminals 6 of the circuit substrate 5 are aligned and coupled with one another while said bonding agent 4 is thermoset so as to electrically connect the IC chip 1 to the circuit substrate 5.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、ICチップに代表され
る電気マイクロ回路素子の入出力パッド上に形成された
突起接点と回路基板上に形成された電極端子とを導電性
接着剤を用いて電気的に接続するIC実装方法に関する
[Industrial Application Field] The present invention uses a conductive adhesive to connect protruding contacts formed on input/output pads of electric microcircuit elements such as IC chips and electrode terminals formed on a circuit board. The present invention relates to an IC mounting method for electrically connecting.

【0002】0002

【従来の技術】従来、ICなどの電気マイクロ回路素子
と回路基板上の電極端子部との接続には半田付けが良く
利用されていた。しかしながら、近年例えばICフラッ
トパッケージなどにおいて、ICチップの小型化や接続
端子の増加等により接続端子間いわゆるピッチ間隔が次
第に狭くなり、従来の半田付け技術で対処することが困
難になってきた。また最近では電卓、電子設計または液
晶ディスプレイなどにおいて裸のICチップをガラス基
板上の電極に直付けして実装面積の効率的使用を図ろう
とする動きがあり、半田付けに代わる有効かつ微細な電
気的接続手段の開発が強く望まれていた。
2. Description of the Related Art Conventionally, soldering has been commonly used to connect electric microcircuit elements such as ICs to electrode terminals on circuit boards. However, in recent years, for example, in IC flat packages, etc., due to the miniaturization of IC chips and the increase in the number of connection terminals, the so-called pitch interval between connection terminals has become gradually narrower, and it has become difficult to cope with this problem using conventional soldering techniques. In addition, recently there has been a movement toward efficient use of mounting area by directly attaching bare IC chips to electrodes on glass substrates in calculators, electronic design, liquid crystal displays, etc.; There was a strong desire to develop a means of connection.

【0003】裸のICチップを回路基板上の電極と電気
的に接続する方法としてはICチップの電極パッド上に
形成した導電性の突起接点に導電性接着剤を塗布し、回
路基板の電極端子と位置合わせした後、接着硬化するこ
とでICチップと回路基板の電気的接続を図る技術があ
る(電子材料  1990年9月号「高密度化・多用化
のため低温プロセス実装技術」)。
[0003] A method for electrically connecting a bare IC chip to an electrode on a circuit board is to apply a conductive adhesive to the conductive protruding contacts formed on the electrode pad of the IC chip, and then connect the electrode terminals of the circuit board. There is a technology for electrically connecting the IC chip and the circuit board by aligning the IC chip and the circuit board and curing the adhesive (Electronic Materials, September 1990 issue, ``Low-temperature process mounting technology for higher density and greater versatility'').

【0004】以下に従来の液晶パネルにおけるIC実装
方法について図面を参照しながら説明する。
[0004] A conventional IC mounting method in a liquid crystal panel will be explained below with reference to the drawings.

【0005】図14〜図17は従来のIC実装方法を示
す工程図であり、図18は図17におけるX部の拡大断
面図である。図14〜図18において、1はICチップ
であり、150個の電極パッド(図示せず)にはメッキ
法で150μmピッチで高さ30μm、径80μmの金
の突起接点2が形成されている。3は柔軟性を有する導
電性接着剤4の膜を作成する支持体である。5は液晶パ
ネル等の回路基板であり、ICチップ1を接続するIT
O電極よりなる電極端子6が形成されている。
14 to 17 are process diagrams showing a conventional IC mounting method, and FIG. 18 is an enlarged sectional view of the X section in FIG. 17. 14 to 18, reference numeral 1 denotes an IC chip, and gold protrusion contacts 2 having a height of 30 μm and a diameter of 80 μm are formed on 150 electrode pads (not shown) at a pitch of 150 μm using a plating method. 3 is a support on which a flexible conductive adhesive 4 film is formed. 5 is a circuit board such as a liquid crystal panel, and an IT board to which the IC chip 1 is connected.
An electrode terminal 6 made of an O electrode is formed.

【0006】従来のIC実装方法は、まず図14に示す
ように、約25μmの導電性接着剤4の膜を形成した支
持体3上に電極パッドに突起接点2が形成されたICチ
ップ1を移動させ、図15に示すようにICチップ1の
突起接点2を前記導電性接着剤4の膜に2秒間浸積する
ことによって図16に示すように導電性接着剤4が突起
接点2に塗布される。その後、導電性接着剤4が塗布さ
れたICチップ1を液晶パネル5上のITO電極6と位
置合わせして結合し、100℃で3時間加熱することに
よって導電性接着剤4を硬化して接続が完了する。
In the conventional IC mounting method, as shown in FIG. 14, an IC chip 1 having protruding contacts 2 formed on electrode pads is first mounted on a support 3 on which a film of conductive adhesive 4 of about 25 μm is formed. The protruding contacts 2 of the IC chip 1 are immersed in the film of the conductive adhesive 4 for 2 seconds as shown in FIG. 15, so that the conductive adhesive 4 is applied to the protruding contacts 2 as shown in FIG. be done. Thereafter, the IC chip 1 coated with the conductive adhesive 4 is aligned and bonded to the ITO electrode 6 on the liquid crystal panel 5, and the conductive adhesive 4 is cured and connected by heating at 100° C. for 3 hours. is completed.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、上記従
来の方法では、X部拡大断面である図18に示すように
導電性接着剤4はITO電極6上に十分広がるものの、
突起接点2とITO電極6間の導電性接着剤4の膜は5
μm以下と薄く、熱衝撃試験(−40℃〜+80℃)な
どで液晶パネル5(熱膨張係数:約5×10−6/℃)
とICチップ1(熱膨張係数:約3×10−6/℃)の
熱膨張係数差によって生じる応力を導電性接着剤4の柔
軟性では十分吸収できず、50サイクル程度(目標20
0サイクル)で導電性接着剤4が剥離してオープン現象
が発生するという課題や、導電性接着剤4が広がりすぎ
て(最大120μm)隣接するITO電極6間でショー
トするという課題があった。
[Problems to be Solved by the Invention] However, in the conventional method described above, although the conductive adhesive 4 is sufficiently spread over the ITO electrode 6 as shown in FIG.
The film of conductive adhesive 4 between the protruding contact 2 and the ITO electrode 6 is 5.
Liquid crystal panel 5 (coefficient of thermal expansion: approx. 5 x 10-6/°C) has been tested in thermal shock tests (-40°C to +80°C) with a thickness of less than μm.
The flexibility of the conductive adhesive 4 cannot sufficiently absorb the stress caused by the difference in thermal expansion coefficient between the IC chip 1 and the IC chip 1 (thermal expansion coefficient: approx. 3 x 10-6/°C), and the
0 cycles), the conductive adhesive 4 peels off and an open phenomenon occurs, and the conductive adhesive 4 spreads too much (up to 120 μm), causing a short circuit between adjacent ITO electrodes 6.

【0008】本発明はこのような課題を解決するもので
あり、安定した電気的接続が得られる優れたIC実装方
法を提供することを目的とするものである。
[0008] The present invention is intended to solve these problems, and aims to provide an excellent IC mounting method that provides stable electrical connections.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明のIC実装方法は、ICチップと回路基板と
の間に突起接点の厚さより厚いスペーサを介在させる(
第1の方法)ことや導電性接着剤中にスペーサとしての
導電性または絶縁性の粒子粉末を混入する(第2の方法
)方法よりなるものである。
[Means for Solving the Problems] In order to achieve the above object, the IC mounting method of the present invention involves interposing a spacer thicker than the thickness of the protruding contact between the IC chip and the circuit board.
The first method is to mix conductive or insulating particles as a spacer into the conductive adhesive (the second method).

【0010】0010

【作用】したがって本発明によれば、ICチップと回路
基板との間に介在させたICチップ上の突起接点の厚さ
より厚いスペーサによってICチップの突起接点と回路
基板の電極端子との間に間隙を形成した状態で接続され
るため突起接点と電極端子間の導電性接着剤を厚くする
ことができ、導電性接着剤の柔軟性が高まり熱衝撃試験
などでの応力を吸収できるとともに電極端子との接触面
積が小さくなることで導電性接着剤の広がりが規制され
隣接する電極端子間のショートをなくすことができる。
[Operation] Therefore, according to the present invention, a spacer is provided between the IC chip and the circuit board and is thicker than the protrusion contact on the IC chip, thereby creating a gap between the protrusion contact of the IC chip and the electrode terminal of the circuit board. Since the conductive adhesive between the protruding contact and the electrode terminal can be thickened, the conductive adhesive becomes more flexible and can absorb stress during thermal shock tests, etc., and the electrode terminal By reducing the contact area, the spread of the conductive adhesive is restricted and short circuits between adjacent electrode terminals can be eliminated.

【0011】第2の方法においても導電性接着剤中に混
入したスペーサ粒子によって回路基板の電極端子とIC
チップの突起接点との間にスペーサ粒子分の間隙ができ
た状態で接続されるため第1の方法と同様の効果が得ら
れる。
In the second method as well, the spacer particles mixed in the conductive adhesive connect the electrode terminals of the circuit board and the IC.
Since the chip is connected with a gap equal to the spacer particle between the tip and the protruding contact point, the same effect as the first method can be obtained.

【0012】0012

【実施例】以下本発明の一実施例について同一機能を有
するものには同一番号を付して詳しい説明を省略し、相
違する点について説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, in an embodiment of the present invention, parts having the same functions will be given the same reference numerals, detailed explanations will be omitted, and differences will be explained.

【0013】(実施例1)図1〜図7は本発明の第1の
実施例のIC実装方法を示す工程図であり、図8は図7
中のX部拡大断面図である。図1〜図8において、7は
40μm径の樹脂ボールよりなるスペーサであり、紫外
線硬化型接着剤8(アクリル樹脂)で接着固定している
(Embodiment 1) FIGS. 1 to 7 are process diagrams showing an IC mounting method according to a first embodiment of the present invention, and FIG.
It is an enlarged sectional view of the X part inside. In FIGS. 1 to 8, 7 is a spacer made of a resin ball with a diameter of 40 μm, and is adhesively fixed with an ultraviolet curing adhesive 8 (acrylic resin).

【0014】上記構成において次にその実装方法を説明
する。まず図1に示すように、液晶パネル5上のITO
電極6の間にスタンピング法で厚さ約10μm以下の紫
外線硬化型接着剤8を転写、塗布し、図2に示すように
樹脂ボール7を適量散布した後、図3に示す様に出力8
0Wの紫外線ランプ9で30秒間照射し、硬化する。そ
の後に、図4の様に厚さ約25μmの導電性接着剤4の
膜を形成した支持体3上に電極パッドに突起接点2が形
成されたICチップ1を移動させ、図5、6に示す様に
ICチップ1の突起接点2を導電性接着剤4の膜に2秒
間浸積し、突起接点2に塗布する。その後、図7の様に
導電性接着剤4の塗布が完了したICチップ1を液晶パ
ネル5上のITO電極6と位置合わせし、結合する。そ
して、100℃3時間加熱することによって導電性接着
剤4を硬化して接続が完了する。
Next, a method of implementing the above configuration will be explained. First, as shown in FIG.
An ultraviolet curable adhesive 8 with a thickness of about 10 μm or less is transferred and applied between the electrodes 6 by a stamping method, and after an appropriate amount of resin balls 7 are sprinkled as shown in FIG. 2, an output 8 is applied as shown in FIG.
It is irradiated with a 0W ultraviolet lamp 9 for 30 seconds to cure. Thereafter, as shown in FIG. 4, the IC chip 1 with the protruding contacts 2 formed on the electrode pads was moved onto the support 3 on which a film of conductive adhesive 4 with a thickness of about 25 μm was formed, and as shown in FIGS. As shown, the protruding contacts 2 of the IC chip 1 are immersed in a film of conductive adhesive 4 for 2 seconds, and then applied to the protruding contacts 2. Thereafter, as shown in FIG. 7, the IC chip 1 on which the conductive adhesive 4 has been applied is aligned with the ITO electrode 6 on the liquid crystal panel 5 and bonded. Then, by heating at 100° C. for 3 hours, the conductive adhesive 4 is cured and the connection is completed.

【0015】本実施例において、ICチップ1と液晶パ
ネル5のITO電極6との間に突起接点2より大きい絶
縁性の樹脂ボール7を介在させているためX部拡大図で
ある図8に示すようにICチップ1の突起接点2と液晶
パネル5上のITO電極6との間隙は約10μm強と広
くなることから、ITO電極6と導電性接着剤4の接触
面積が小さくなり、接着剤広がり径も従来例における最
大120μmから100μmと小さくなり接続時の隣接
するITO電極6間のショート不良は皆無となった。ま
たICチップ1の突起接点2とITO電極6間の導電性
接着剤4の膜厚が従来の2倍以上となることから熱膨張
係数差による応力の吸収・緩和力が大きくなり、熱衝撃
試験(−40〜+80℃)200サイクル後においても
導電性接着剤4の剥離によるICチップ1のオープン現
象がないことが確認できた。
In this embodiment, an insulating resin ball 7 larger than the protruding contact 2 is interposed between the IC chip 1 and the ITO electrode 6 of the liquid crystal panel 5. As the gap between the protruding contact 2 of the IC chip 1 and the ITO electrode 6 on the liquid crystal panel 5 is wide, approximately 10 μm or more, the contact area between the ITO electrode 6 and the conductive adhesive 4 becomes small, and the adhesive spreads. The diameter was also reduced from the maximum of 120 μm in the conventional example to 100 μm, and there were no short-circuit defects between adjacent ITO electrodes 6 during connection. In addition, since the film thickness of the conductive adhesive 4 between the protruding contact 2 of the IC chip 1 and the ITO electrode 6 is more than twice that of the conventional one, the ability to absorb and relax stress due to the difference in thermal expansion coefficient increases, and the thermal shock test It was confirmed that even after 200 cycles (at −40 to +80° C.), there was no open phenomenon of the IC chip 1 due to peeling of the conductive adhesive 4.

【0016】(実施例2)図9〜図13は本発明の第2
の実施例のIC実装方法を示す工程図であり、図13は
図12中のX部拡大断面図である。図9〜図13におい
て、10はスチレン重合体にニッケル・金メッキを施し
た20μm径の導電性ボールよりなるスペーサであり、
導電性接着剤4中に5重量%混入している。
(Embodiment 2) FIGS. 9 to 13 show the second embodiment of the present invention.
FIG. 13 is a process diagram showing the IC mounting method of the embodiment, and FIG. 13 is an enlarged sectional view of the X section in FIG. 12. In FIGS. 9 to 13, 10 is a spacer made of a 20 μm diameter conductive ball made of styrene polymer plated with nickel and gold.
It is mixed in the conductive adhesive 4 in an amount of 5% by weight.

【0017】上記構成において次にその実装方法を説明
する。まず図9に示すように、導電性ボール10を混入
した導電性接着剤4の膜を形成した支持体3上に電極パ
ッドに突起接点2が形成されたICチップ1を移動させ
、図9、10に示すようにICチップ1の突起接点2を
導電性接着剤4の膜中に2秒間浸積し、図11の様に突
起接点2に塗布する。その後、図12に示す様に、導電
性接着剤4の塗布が完了したICチップ1を液晶パネル
5上のITO電極6と位置合わせし結合する。そして、
100℃3時間加熱によって導電性接着剤4を硬化して
接続が完了する。
Next, a method of implementing the above configuration will be explained. First, as shown in FIG. 9, the IC chip 1 with the protruding contacts 2 formed on the electrode pads is moved onto a support 3 on which a film of conductive adhesive 4 mixed with conductive balls 10 is formed. As shown in FIG. 10, the protruding contacts 2 of the IC chip 1 are immersed in a film of conductive adhesive 4 for 2 seconds, and the protruding contacts 2 are coated as shown in FIG. Thereafter, as shown in FIG. 12, the IC chip 1 on which the conductive adhesive 4 has been applied is aligned and bonded to the ITO electrode 6 on the liquid crystal panel 5. and,
The conductive adhesive 4 is cured by heating at 100° C. for 3 hours to complete the connection.

【0018】本実施例において、導電性接着剤4中に直
径20μmの導電性ボール10を混入していることによ
りX部拡大図である図13のに示すようにICチップ1
のいずれか複数個の突起接点2の下に導電性ボール10
が介在し、そのためICチップ1上の突起接点2と液晶
パネル5上のITO電極6との間隙は約20μm強と広
くなることで、ITO電極6と導電性接着剤4の接触面
積が小さくなり、接着剤広がり径が従来例における最大
120μmから100μmと小さくなり接続時の隣接す
るITO電極6間のショート不良は皆無となった。また
導電性接着剤4の熱膨張係数差による応力の吸収・緩和
力が大きくなり熱衝撃試験(−40〜+80℃)200
サイクル後においても導電性接着剤4の剥離によるIC
チップ1のオープン現象がないことが確認できた。
In this embodiment, the conductive balls 10 having a diameter of 20 μm are mixed into the conductive adhesive 4, so that the IC chip 1 is formed as shown in FIG.
A conductive ball 10 is placed under any one of the plurality of protruding contacts 2.
interposes, and as a result, the gap between the protruding contact 2 on the IC chip 1 and the ITO electrode 6 on the liquid crystal panel 5 becomes wide, approximately 20 μm or more, and the contact area between the ITO electrode 6 and the conductive adhesive 4 becomes smaller. The adhesive spreading diameter was reduced from the maximum of 120 μm in the conventional example to 100 μm, and there were no short-circuit defects between adjacent ITO electrodes 6 during connection. In addition, the stress absorption and relaxation power due to the difference in the thermal expansion coefficient of the conductive adhesive 4 increases, and the thermal shock test (-40 to +80°C) 200
IC due to peeling of the conductive adhesive 4 even after the cycle
It was confirmed that there was no open phenomenon of chip 1.

【0019】このように上記実施例によれば、ICチッ
プ1と液晶パネル5との間に突起接点2より大きい樹脂
ボール7または導電性ボール10を介在させているため
突起接点2とITO電極6との間隙が広くなって導電性
接着剤4の広がり径も小さくなり、したがって隣接する
ITO電極6間のショート不良が皆無となった。
As described above, according to the above embodiment, since the resin ball 7 or the conductive ball 10, which is larger than the protruding contact 2, is interposed between the IC chip 1 and the liquid crystal panel 5, the protruding contact 2 and the ITO electrode 6 are interposed between the protruding contact 2 and the ITO electrode 6. The gap between the conductive adhesive 4 and the conductive adhesive 4 became wider, and the spread diameter of the conductive adhesive 4 became smaller. Therefore, there were no short-circuit defects between adjacent ITO electrodes 6.

【0020】[0020]

【発明の効果】上記実施例より明らかなように本発明は
、ICチップと回路基板との間に突起接点より大きい絶
縁性のスペーサを介在させる(第1の方法)ことや導電
性接着剤中にスペーサ用の導電性または絶縁性の粒子粉
末を混入する(第2の方法)ことによってICチップ上
の電極パッド上に形成された突起接点と回路基板上の電
極端子との間隙は約20μm強と広くすることができ、
電極端子と導電性接着剤との接触面積が小さくなること
から、接着剤広がり径を小さくできるとともに導電性接
着剤の柔軟性が高まり熱衝撃試験などでの応力が吸収、
緩和され、したがって導電性接着剤の剥離によるショー
ト不良等の現象がない安定した電気的接続を得ることが
できる。
[Effects of the Invention] As is clear from the above embodiments, the present invention provides a method of interposing an insulating spacer larger than a protruding contact between an IC chip and a circuit board (first method) and using a conductive adhesive. By mixing conductive or insulating particles for a spacer (second method), the gap between the protruding contacts formed on the electrode pads on the IC chip and the electrode terminals on the circuit board is approximately 20 μm or more. and can be widened,
Since the contact area between the electrode terminal and the conductive adhesive becomes smaller, the adhesive spread diameter can be reduced, and the conductive adhesive becomes more flexible, absorbing stress during thermal shock tests, etc.
Therefore, it is possible to obtain a stable electrical connection without phenomena such as short-circuit failures due to peeling of the conductive adhesive.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の第1の実施例のIC実装方法における
接着剤の塗布工程図
[Fig. 1] Adhesive application process diagram in the IC mounting method of the first embodiment of the present invention.

【図2】同実施例におけるスペーサ散布の工程図[Figure 2] Process diagram of spacer dispersion in the same example

【図3
】同実施例における接着剤硬化の工程図
[Figure 3
] Process diagram of adhesive curing in the same example

【図4】同実施
例におけるICチップの移動積載工程図
[Figure 4] Diagram of the process of moving and loading IC chips in the same example

【図5】同実施
例における導電性接着剤の塗布工程図
[Figure 5] Diagram of the process of applying conductive adhesive in the same example

【図6】同実施例
における導電性接着剤の塗布工程図
[Figure 6] Diagram of the process of applying conductive adhesive in the same example

【図7】同実施例に
おけるICチップの位置合わせ・結合の工程図
[Figure 7] Process diagram for positioning and bonding IC chips in the same example

【図8】図7におけるX部の拡大断面図[Fig. 8] Enlarged sectional view of the X section in Fig. 7

【図9】本発明
の第2の実施例におけるICチップの移動工程図
FIG. 9 is a process diagram for moving an IC chip in the second embodiment of the present invention.

【図10】同実施例におけるICチップへの接着剤塗布
工程図
[Figure 10] Process diagram of applying adhesive to IC chip in the same example

【図11】同実施例におけるICチップへの接着剤の塗
布状態図
[Fig. 11] Diagram showing how adhesive is applied to the IC chip in the same example.

【図12】同実施例におけるICチップの位置合わせ・
結合の工程図
FIG. 12: Alignment of IC chip in the same example.
Joining process diagram

【図13】図12のX部の拡大断面図[Fig. 13] Enlarged sectional view of the X part in Fig. 12

【図14】従来例のIC実装方法におけるICチップの
移動積載の工程図
[Figure 14] Process diagram for moving and loading IC chips in a conventional IC mounting method

【図15】同従来例のIC実装方法におけるICチップ
への接着剤塗布工程図
[Figure 15] Process diagram for applying adhesive to an IC chip in the conventional IC mounting method

【図16】同従来例のIC実装方法におけるICチップ
への接着剤塗布状態図
[Fig. 16] Diagram showing how adhesive is applied to an IC chip in the conventional IC mounting method.

【図17】同従来例におけるICチップの位置合わせ・
結合の工程図
[Figure 17] Alignment of IC chip in the conventional example
Joining process diagram

【図18】図17のX部の拡大断面図[Fig. 18] Enlarged sectional view of the X part in Fig. 17

【符号の説明】[Explanation of symbols]

1  ICチップ 2  突起接点 4  導電性接着剤 5  液晶パネル(回路基板) 6  ITO電極(電極端子) 7  樹脂ボール(スペーサ) 10  導電性ボール(スペーサ) 1 IC chip 2 Protruding contact 4 Conductive adhesive 5 Liquid crystal panel (circuit board) 6 ITO electrode (electrode terminal) 7 Resin ball (spacer) 10 Conductive ball (spacer)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】ICチップの上に電極パッドに形成された
突起接点の頭頂部に導電性接着剤を用いて回路基板の電
極端子と突起接点とを接続するIC実装方法において、
前記ICチップと回路基板との間に前記ICチップの突
起接点の厚さより厚いスペーサを接着剤で固定した後、
導電性接着剤を塗布したICチップの突起接点と前記回
路基板の電極端子とを位置合わせして接続するIC実装
方法。
1. An IC mounting method in which an electrode terminal of a circuit board and a protruding contact are connected using a conductive adhesive on the top of a protruding contact formed on an electrode pad on an IC chip, comprising:
After fixing a spacer thicker than the thickness of the protruding contact of the IC chip between the IC chip and the circuit board with an adhesive,
An IC mounting method in which protruding contacts of an IC chip coated with a conductive adhesive are aligned and connected to electrode terminals of the circuit board.
【請求項2】導電性接着剤が突起接点の厚さより大きい
直径を有する導体または絶縁体からなる粒子粉末をスベ
ーサとして含有する請求項1記載のIC実装方法。
2. The IC mounting method according to claim 1, wherein the conductive adhesive contains particles of a conductor or insulator having a diameter larger than the thickness of the protruding contact as a base material.
JP3011869A 1991-02-01 1991-02-01 Ic mounting method Pending JPH04246840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3011869A JPH04246840A (en) 1991-02-01 1991-02-01 Ic mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3011869A JPH04246840A (en) 1991-02-01 1991-02-01 Ic mounting method

Publications (1)

Publication Number Publication Date
JPH04246840A true JPH04246840A (en) 1992-09-02

Family

ID=11789732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3011869A Pending JPH04246840A (en) 1991-02-01 1991-02-01 Ic mounting method

Country Status (1)

Country Link
JP (1) JPH04246840A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008226946A (en) * 2007-03-09 2008-09-25 Nec Corp Semiconductor device and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008226946A (en) * 2007-03-09 2008-09-25 Nec Corp Semiconductor device and its manufacturing method

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