JPH04243995A - Production of semiconductor crystal - Google Patents

Production of semiconductor crystal

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Publication number
JPH04243995A
JPH04243995A JP1046991A JP1046991A JPH04243995A JP H04243995 A JPH04243995 A JP H04243995A JP 1046991 A JP1046991 A JP 1046991A JP 1046991 A JP1046991 A JP 1046991A JP H04243995 A JPH04243995 A JP H04243995A
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JP
Japan
Prior art keywords
melt
impurities
crystal
impurity
crucible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1046991A
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Japanese (ja)
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JP2943341B2 (en
Inventor
Toshiro Nakanishi
俊郎 中西
Tetsuo Fukuda
哲生 福田
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Fujitsu Ltd
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Fujitsu Ltd
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Publication of JPH04243995A publication Critical patent/JPH04243995A/en
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Abstract

PURPOSE:To provide the title production by pull method using a crucible in such a way that the second impurities to compensate the effects of the increase in the concentration of the first impurities in a melt is melted in the melt along with the dissolution of the crucible's inner wall, thereby obtaining crystal with uniform resistivity distribution. CONSTITUTION:The production of the objective semiconductor single crystal (1) by pull method from a melt (3) containing the first impurities contributing to the first electrically conductive type. The process is as follows: the second impurities in the inner wall of a crucible (2) is dissolved in the melt (3) and incorporated into said crystal (1), and the decline in the resistivity of said crystal(1) due to the increase in the first impurities with the solidification of the melt (3) is compensated by the increase in the second impurities. And, the concentration distribution for the second impurities for the depth of said inner wall is so designed that the ratio of the rate of increase in the concentration of the first impurities in the melt (3) to that of increase in the concentration of the second impurities in said melt (3) due to the dissolution of said inner wall and solidification of said melt (3) come to 0.5-1.5 times the ratio of the segregation coefficient of the second impurities to that of the first impurities.

Description

【発明の詳細な説明】 【0001】 【産業上の利用分野】本発明は,ルツボを用いる引上げ
法により単結晶を製造する半導体製造方法に関する。 【0002】近年の半導体装置の微細化とそのチップの
大型化に伴い,電気的特性が精密に制御された半導体基
板が求められている。しかし,引上げ法により製造され
た単結晶は,融液が固化する際の不純物の偏析に起因し
て電気抵抗率の分布が生じ,このため製造された単結晶
の一部しか利用することができない。 【0003】そこで,不純物の偏析があっても電気抵抗
率の分布が均一である結晶を製造することが要求されて
いる。 【0004】 【従来の技術】従来の引上げ法による半導体結晶の製造
を図4を参照して説明する。図4は従来技術の実施例説
明図であって,図4(a)は引上げ法による半導体結晶
製造装置の主要部を断面図で示したものである。 【0005】ルツボ2A内に保持された融液3には第一
の不純物が所定量含まれる。この第一の不純物の融液3
中の濃度は,融液3が固化する際に不純物の偏析がある
ため結晶1A中に取り込まれなかった不純物が結晶1A
と融液3の界面から第一の不純物の増分4として融液中
に流入し,このため結晶製造の過程において連続的に増
加する。 【0006】この結果,結晶1Aの電気抵抗率は製造初
期の部分から製造終期の部分迄不純物濃度の分布に応じ
て連続的に変化することになる。かかる,固化率に依存
した不純物濃度の変化は以下のように表される。 【0007】結晶製造当初の融液の体積をV0,及び当
初の融液の不純物濃度をC0 とし,成長期間中は一定
の速さで単位時間当たり融液体積VG が固化するとき
,成長開始からt時間後の融液中の不純物濃度C1(t
)は,不純物の偏析係数k1 を用いて,  【0008】 【数1】C1 (t)=C0(1−VG t/V0)k
1−1となることが知られている。 【0009】而るに, 結晶1Aの成長開始からt 時
間後に成長する部分の不純物濃度CC (t) は融液
の固化の際の偏析に従い, 【0010】 【数2】CC (t)=k1 ×C1(t)となるから
, 数1に示されたC1 の変動に従って結晶1A中の
不純物濃度が変化するのである。 【0011】図4(b)は,従来技術により製造された
結晶1Aの引上げ軸方向の電気抵抗率の分布を示してい
る。なお,結晶1Aはシリコン,不純物としてB,ルツ
ボ2Aには石英が用いられた。 【0012】同図中の電気抵抗率の分布は,数1及び数
2から求められる分布と一致しており,従来技術にあっ
ては,不純物の偏析は半導体結晶の電気抵抗率を不均一
にする要因であることが明瞭に示されている。 【0013】かかる不都合を解決するために,結晶中の
不純物濃度と同一不純物濃度の原材料を固化した融液量
と同量を連続して追加する連続チャージ法,あるいは二
重ルツボ法が考案された。 【0014】しかし,いずれも装置が複雑になり,この
ため高価なものとなった。 【0015】 【発明が解決しようとする課題】上述したように従来技
術では,導電型及び電気抵抗率を決定するために添加す
る不純物の偏析係数が通常は1よりも小さいことから,
結晶製造の進行とともに融液中に不純物が濃縮され,結
晶中の不純物濃度が不均一になる結果,結晶中の電気抵
抗率は不均一になるという問題があった。 【0016】また,連続チャージ法及び二重ルツボ法は
複雑,高価な装置になるという欠点がある。本発明の目
的は,融液中の不純物濃度の増加に対して,これを補償
する不純物をルツボの溶解とともに融液中に溶融せしめ
ることにより,容易に均一な電気抵抗率分布を有する結
晶を成長させることができる半導体結晶の製造方法を提
供することにある。 【0017】 【課題を解決するための手段】図1は本発明の原理説明
図であり,引上げ法による半導体結晶製造装置の主要部
を断面図で示したものである。 【0018】本発明の半導体製造方法は,図1を参照し
て,半導体結晶1を第一の導電型とする第一の不純物を
含みルツボ2内に保持された融液3から,引上げ法によ
り単結晶を製造する半導体結晶の製造方法において, 
該ルツボ2の内壁に該結晶1を該第二の導電型とする第
二の不純物を含有させることを特徴として構成され,及
び,上記構成の半導体結晶の製造方法において, 上記
ルツボ2内壁中の厚さ方向についての上記第二の不純物
濃度を,該ルツボ2内壁の溶解及び上記融液3の固化に
より増加する該融液3中の該第二の不純物濃度C2 の
増加する速さdC2 /dtが,該融液3中の上記第一
の不純物濃度C1 の増加する速さdC1 /dt及び
該第一の不純物の偏析係数k1及び該第二の不純物の偏
析係数k2を用いて,   0.5 ×k2/k1<(dC1 /dt)/(d
C2 /dt)<1.5 ×k2/k1となるような分
布に生成することを特徴として構成される。 【0019】 【作用】本発明の構成の作用を,図1を参照して説明す
る。不純物を含有する融液3からの引上げ法による結晶
製造においては,融液3が固化して結晶1となるとき,
不純物の偏析係数が1より小さいことから結晶中に取り
込まれなかった不純物が融液3と結晶1との界面から不
純物の増分4として融液3中に流れ込み融液3中の不純
物濃度を上昇させる。 【0020】このため,結晶1中に不純物濃度の不均一
,即ち抵抗率の不均一を生ずるのである。他方本発明で
は,融液1と接触するルツボ2の内壁が溶解するため,
ルツボ2内壁に含有されていた第二の不純物が融液中に
溶け込む。 【0021】従って,融液3中には第一の不純物の他に
第2の不純物も同時に増加し、かかる融液3から固化し
た結晶1中には上記2種の不純物が固化率と共に増加し
て分布することになる。 【0022】かかる上記2種の不純物は,本発明におい
ては,結晶1中で互いに反対の導電型をもたらすキャリ
アを生成するものとされており,従ってドナー又はアク
セプタとして互いに補償し合う不純物である。 【0023】それゆえ,主たる不純物たる第一の不純物
の増加によるキャリアの増加は,それより少量の第二の
不純物の増加により補償される結果,第一の不純物の増
加に起因する抵抗率の変動が緩和されるのである。 【0024】従って,抵抗率の均一な結晶が製造できる
のである。なお,偏析による融液3中の不純物濃度の増
加は,第1及び第2の不純物について共に生ずるのであ
るが,第一の不純物は第二のものより高濃度なので,多
くの場合,絶対量は第一の不純物の方が速く増加するの
である。 【0025】このため,融液3中に不純物を追加しない
場合には第一と第二の不純物濃度の差は常に開くことに
なり,この差を補償するためには,本発明の構成にある
如く,ルツボ2内壁からの第二の不純物の供給が欠かせ
ないのである。 【0026】本発明の第二の構成は,結晶中の上記2種
の不純物濃度の差が一定となるように,ルツボ内壁に含
まれる第二の不純物についての深さ方向の濃度分布を形
成したものである。 【0027】以下,図1を参照して第二の構成の作用を
説明する。融液3に接するルツボ2内壁は通常ほぼ一定
の速度で溶解する。従って,単位時間当たりの溶解する
厚さをvc とすると,結晶製造開始からt時間後には
,vc tの厚さのルツボ内壁が溶解する。 【0028】よって,当初のルツボ内壁表面からの深さ
dの位置におけるルツボ材料中の第二の不純物濃度分布
をn(d)とするとき,ルツボ2内壁が融液3と接触し
て溶解することにより増加する融液3中の第二の不純物
濃度は,その融液3との接触する面積をS,融液3の体
積をVとするとき, 【0029】 【数3】vc n(vc t)S/V だけ単位時間当たり増加する。なお,半径Rのルツボ2
を使用するとき, 【0030】 【数4】 S=πR2 +2V/R,V=V0 (1−vg t)
で与えられる。 【0031】さらに,融液3の固化に伴う偏析係数k2
 の第二の不純物の融液3中の濃度増加は,VG /V
0 =vg とするとき, 単位時間当たり,【003
2】 【数5】C2 V0 (1−k2 )vg /Vである
から,結局第二の不純物の融液3中濃度の増加速度dC
2/dtは数3及び数5を加えて,【0033】 【数6】dC2/dt=vc n(vc t)S/V+
C2 V0 (1−k2 )vg /V となる。 【0034】一方,第一の不純物の融液3中濃度の増加
速度dC1/dtは,数1を微分して 【0035】 【数7】 dC1/dt=vg C0 (1−k1 )(1−vg
 t)k1−2=C1 V0 vg (1−k1 )/
Vである。ここでV=V0 (1−vg t)を用いた
。 【0036】本発明の第二の構成では,結晶製造のいか
なる時にも両不純物濃度の増加速度について,【003
7】 【数8】 (dC1/dt)/(dC2/dt)=k2/k1がほ
ぼ成立するようにn(d)を決定するのである。 【0038】上記の比のとき,結晶1中の両不純物の濃
度の差Dは,偏析の効果を考慮して 【0039】 【数9】D=k1・C1 −k2・C2 =一定となる
。 【0040】従って,本発明の第二の構成においては,
互いに補償する不純物の濃度差が結晶1中では常に一定
値Dであるから,キャリア濃度は一定であり,よって結
晶1全体について一定の抵抗率を有する結晶製造が可能
となるのである。 【0041】かかる効果を奏するためのルツボ2内壁中
の第二の不純物の濃度分布n(d)は,数8及び数9が
成立するように決定することができる。例えば,数8に
数9,数6及び数7を代入して, 【0042】 【数10】n(vc t)=(k1/k2)( vg/
vc )(C1 V0 /S)(1−k1 )×〔1−
(1−D/(k1 C1 ))(1−k2)/(1−k
1 )〕から,t=d/vc と置き換えることにより
決定される。ここでC1 は数1からSは数4から定ま
る。 【0043】 【実施例】図2は本発明の実施例であり,ルツボ内壁中
の第二の不純物濃度分布の一例を表している。 【0044】本発明を実施例に基づき,図1,図2を参
照して,説明する。半導体材料,例えばシリコンをルツ
ボ2にチャージし,第一の不純物を添加して加熱溶融す
る。ルツボ材料としては例えば石英を,第一の不純物と
しては例えばB,P,As,Sbを使用できる。 【0045】次いで引上げ軸方位が例えば<100>の
種結晶を融液3に浸し,引上げることにより半導体の単
結晶1を成長させる。ここで直径が略35cmの石英る
つぼ2を用い,チャージ量20kg,融液3中のBの初
期濃度を7×1014atom/gとするときの例では
,石英ルツボ2の内壁の溶解速度は7μm/hである。 【0046】第二の不純物としては例えばP,Asまた
はSbが利用でき,結晶の比抵抗を10Ωcmとすると
き,石英ルツボ2内壁内のP,AsまたはSbの濃度分
布は数10から図2中でそれぞれP,As,Sbとして
示される如く決定される。 【0047】かかる不純物の濃度分布をもつ石英ルツボ
2を製造するには,例えば石英ルツボ2内壁上へCVD
により不純物をドープしたSiO2 を堆積することに
より実現される。 【0048】Pを第二の不純物とするとき上記分布は,
例えば成長温度800℃,成長速度90nm/分の条件
下で,TEOS(Tetraethyl Orthos
ilicate) とPH3 との分圧比を,当初10
3 としその後分圧比を除々に増加して,SiO2 膜
が100μmの厚さのとき104 とすることで実現さ
れる。 【0049】図3は本発明の実施例説明図であり,上記
ルツボを使用して製造されたシリコン結晶の抵抗率の分
布の一例を示している。図3に示されるように,本発明
により均一な抵抗率の結晶が製造できるのである。 【0050】ここで,抵抗率を10Ωcmから10%以
内とするには,ルツボ内壁の不純物濃度分布を数10の
値の10%以内とすることが必要である。さらに,本発
明が特に有用とされるのは素子形成の際の障害とされる
欠陥が生成するおそれが少ない不純物の絶対量が少ない
場合であり,かかる場合に,結晶の抵抗率を10%以内
にするためには,数8の比がk2/k1の0.5〜1.
5倍であれば充分であった。 【0051】従って,ルツボ内壁の不純物濃度分布の許
容値が大きくとれるから,ルツボの製造が容易になると
いう効果がある。なお,As,B,Sbについても同様
のCVD法により所要の濃度分布とすることができ,こ
れらを第二の不純物として本発明を適用することができ
る。 【0052】また,図2中のBは,Pを第一の不純物と
し,Bを第二の不純物とするとき10式から計算される
ルツボ内壁のB濃度分布であり, 本発明をn型シリコ
ン結晶の製造に適用する例である。 【0053】さらに,本発明はシリコン以外の,例えば
化合物半導体にも同様に適応されるのは勿論である。ま
た,石英ルツボ内壁中の不純物分布が一定であっても,
従来技術よりも均一な結晶を製造できるという効果を奏
し得ることは当然である。 【0054】 【発明の効果】本発明によれば,偏析に起因する結晶製
造中の不純物濃度の増加に対して,これを補償する不純
物をルツボの溶解とともに融液中に溶融せしめることに
より,電導に寄与する結晶中のキャリア濃度の変動が補
償されるから,容易に均一な電気抵抗率分布を有する結
晶を製造できる半導体製造方法を提供することができ,
半導体装置の性能向上に寄与するところが大きい。
Description: [0001] The present invention relates to a semiconductor manufacturing method for manufacturing a single crystal by a pulling method using a crucible. With the recent miniaturization of semiconductor devices and the increase in the size of their chips, there is a demand for semiconductor substrates whose electrical characteristics are precisely controlled. However, single crystals produced by the pulling method have a distribution of electrical resistivity due to the segregation of impurities when the melt solidifies, and for this reason only a portion of the produced single crystal can be used. . [0003]Therefore, there is a need to produce crystals that have a uniform distribution of electrical resistivity even when there is segregation of impurities. 2. Description of the Related Art The production of semiconductor crystals by a conventional pulling method will be explained with reference to FIG. FIG. 4 is an explanatory diagram of an embodiment of the prior art, and FIG. 4(a) is a sectional view showing the main part of a semiconductor crystal manufacturing apparatus using a pulling method. [0005] The melt 3 held in the crucible 2A contains a predetermined amount of the first impurity. This first impurity melt 3
The concentration of impurities in crystal 1A is due to segregation of impurities when melt 3 solidifies, so impurities that were not incorporated into crystal 1A are
The first impurity increment 4 flows into the melt from the interface between the first impurity and the melt 3, and therefore increases continuously during the crystal production process. As a result, the electrical resistivity of the crystal 1A changes continuously in accordance with the impurity concentration distribution from the initial stage of manufacture to the final stage of manufacture. This change in impurity concentration depending on the solidification rate is expressed as follows. Let the volume of the melt at the beginning of crystal production be V0, and the initial impurity concentration of the melt be C0, and when the melt volume VG solidifies per unit time at a constant rate during the growth period, from the start of the growth Impurity concentration C1 in the melt after t time (t
), using the impurity segregation coefficient k1, [Formula 1]C1 (t)=C0(1-VG t/V0)k
It is known that the ratio is 1-1. [0009] Therefore, the impurity concentration CC (t) of the part that grows after t hours from the start of growth of crystal 1A follows the segregation during solidification of the melt, and is expressed as follows: [Equation 2] CC (t) = k1 Since ×C1(t), the impurity concentration in the crystal 1A changes according to the fluctuation of C1 shown in Equation 1. FIG. 4(b) shows the distribution of electrical resistivity in the direction of the pulling axis of the crystal 1A produced by the conventional technique. Note that silicon was used for the crystal 1A, B was used as an impurity, and quartz was used for the crucible 2A. The distribution of electrical resistivity in the figure matches the distribution obtained from Equations 1 and 2, and in the conventional technology, the segregation of impurities causes the electrical resistivity of the semiconductor crystal to become non-uniform. It has been clearly shown that this is a contributing factor. [0013] In order to solve this inconvenience, a continuous charging method or a double crucible method was devised in which the same amount of raw material as the solidified melt is continuously added with the same impurity concentration as the impurity concentration in the crystal. . However, in both cases, the devices are complicated and therefore expensive. [0015] As mentioned above, in the prior art, since the segregation coefficient of impurities added to determine conductivity type and electrical resistivity is usually smaller than 1,
As crystal production progresses, impurities are concentrated in the melt, and as a result, the impurity concentration in the crystal becomes non-uniform, resulting in a problem in that the electrical resistivity in the crystal becomes non-uniform. Furthermore, the continuous charging method and the double crucible method have the disadvantage that they require complicated and expensive equipment. The purpose of the present invention is to easily grow crystals with a uniform electric resistivity distribution by melting impurities into the melt as the crucible melts to compensate for the increase in impurity concentration in the melt. It is an object of the present invention to provide a method for manufacturing a semiconductor crystal that can be used to produce a semiconductor crystal. [Means for Solving the Problems] FIG. 1 is an explanatory diagram of the principle of the present invention, and is a sectional view showing the main parts of a semiconductor crystal manufacturing apparatus using a pulling method. Referring to FIG. 1, in the semiconductor manufacturing method of the present invention, a melt 3 containing a first impurity that makes a semiconductor crystal 1 have a first conductivity type and held in a crucible 2 is extracted by a pulling method. In a semiconductor crystal manufacturing method for manufacturing a single crystal,
In the method for producing a semiconductor crystal having the above structure, the inner wall of the crucible 2 contains a second impurity that makes the crystal 1 of the second conductivity type. The rate at which the second impurity concentration C2 in the melt 3 increases due to melting of the inner wall of the crucible 2 and solidification of the melt 3 is dC2 /dt. However, using the rate of increase of the first impurity concentration C1 in the melt 3, dC1 /dt, the segregation coefficient k1 of the first impurity, and the segregation coefficient k2 of the second impurity, 0.5 ×k2/k1<(dC1/dt)/(d
C2/dt)<1.5×k2/k1. [Operation] The operation of the structure of the present invention will be explained with reference to FIG. In crystal production by the pulling method from melt 3 containing impurities, when melt 3 solidifies to become crystal 1,
Since the segregation coefficient of impurities is smaller than 1, impurities that are not incorporated into the crystal flow into the melt 3 from the interface between the melt 3 and the crystal 1 as an impurity increment 4, increasing the impurity concentration in the melt 3. . For this reason, non-uniform impurity concentration, ie non-uniform resistivity, occurs in the crystal 1. On the other hand, in the present invention, since the inner wall of the crucible 2 that comes into contact with the melt 1 melts,
The second impurity contained in the inner wall of the crucible 2 dissolves into the melt. Therefore, in addition to the first impurity, the second impurity also increases in the melt 3, and in the crystal 1 solidified from the melt 3, the above two types of impurities increase with the solidification rate. The distribution will be as follows. [0022] In the present invention, these two types of impurities are said to generate carriers that bring about mutually opposite conductivity types in the crystal 1, and therefore are impurities that compensate for each other as donors or acceptors. Therefore, the increase in carriers due to the increase in the first impurity, which is the main impurity, is compensated for by the increase in the second impurity, which is a smaller amount, resulting in a change in resistivity caused by the increase in the first impurity. is alleviated. [0024] Therefore, a crystal with uniform resistivity can be manufactured. Note that the increase in impurity concentration in the melt 3 due to segregation occurs for both the first and second impurities, but since the first impurity has a higher concentration than the second, in many cases the absolute amount is The first impurity increases faster. For this reason, if no impurities are added to the melt 3, the difference between the first and second impurity concentrations will always be large, and in order to compensate for this difference, the structure of the present invention has Thus, the supply of the second impurity from the inner wall of the crucible 2 is essential. [0026] In the second configuration of the present invention, a concentration distribution in the depth direction of the second impurity contained in the inner wall of the crucible is formed so that the difference in the concentration of the two types of impurities in the crystal is constant. It is something. The operation of the second configuration will be explained below with reference to FIG. The inner wall of the crucible 2 in contact with the melt 3 usually melts at a substantially constant rate. Therefore, if the thickness to be melted per unit time is vc, then after t hours from the start of crystal production, the inner wall of the crucible having a thickness of vct will be melted. [0028] Therefore, when the second impurity concentration distribution in the crucible material at the position of depth d from the initial crucible inner wall surface is n(d), the inner wall of the crucible 2 contacts the melt 3 and melts. The second impurity concentration in the melt 3 increases as a result of this, where S is the contact area with the melt 3 and V is the volume of the melt 3. t) increases by S/V per unit time. In addition, crucible 2 with radius R
When using, [Equation 4] S=πR2 +2V/R, V=V0 (1−vg t)
is given by Furthermore, the segregation coefficient k2 accompanying the solidification of the melt 3
The increase in the concentration of the second impurity in the melt 3 is VG /V
When 0 = vg, per unit time, 003
2] [Equation 5] Since C2 V0 (1-k2)vg /V, the rate of increase in the concentration of the second impurity in the melt 3 is dC
2/dt is obtained by adding Equation 3 and Equation 5, [Equation 6] dC2/dt=vc n(vc t)S/V+
C2 V0 (1-k2)vg/V. On the other hand, the increasing rate dC1/dt of the concentration of the first impurity in the melt 3 can be calculated by differentiating the equation 1 as follows: dC1/dt=vg C0 (1-k1) (1- vg
t) k1-2=C1 V0 vg (1-k1)/
It is V. Here, V=V0 (1-vg t) was used. In the second configuration of the present invention, the rate of increase in both impurity concentrations at any time during crystal production is
7] n(d) is determined so that (dC1/dt)/(dC2/dt)=k2/k1 approximately holds true. At the above ratio, the difference D between the concentrations of both impurities in the crystal 1 becomes constant, taking into account the effect of segregation: D=k1.C1 -k2.C2 =. [0040] Therefore, in the second configuration of the present invention,
Since the concentration difference of impurities that compensate for each other is always a constant value D in the crystal 1, the carrier concentration is constant, and therefore it is possible to manufacture a crystal having a constant resistivity for the entire crystal 1. The concentration distribution n(d) of the second impurity in the inner wall of the crucible 2 to achieve this effect can be determined so that Equations 8 and 9 hold. For example, by substituting numbers 9, 6, and 7 into equation 8, we get
vc )(C1 V0 /S)(1-k1)×[1-
(1-D/(k1 C1))(1-k2)/(1-k
1)] by replacing it with t=d/vc. Here, C1 is determined from Equation 1 and S is determined from Equation 4. [Embodiment] FIG. 2 is an embodiment of the present invention, and shows an example of the second impurity concentration distribution in the inner wall of the crucible. The present invention will be explained based on an embodiment with reference to FIGS. 1 and 2. A semiconductor material such as silicon is charged in a crucible 2, a first impurity is added thereto, and the material is heated and melted. For example, quartz can be used as the crucible material, and B, P, As, or Sb can be used as the first impurity. Next, a seed crystal whose pulling axis direction is, for example, <100> is immersed in the melt 3 and pulled up to grow a semiconductor single crystal 1. Here, in an example using a quartz crucible 2 with a diameter of approximately 35 cm, a charge amount of 20 kg, and an initial concentration of B in the melt 3 of 7 x 1014 atoms/g, the dissolution rate of the inner wall of the quartz crucible 2 is 7 μm/g. It is h. As the second impurity, for example, P, As or Sb can be used. When the specific resistance of the crystal is 10 Ωcm, the concentration distribution of P, As or Sb in the inner wall of the quartz crucible 2 is calculated from the equation 10 as shown in FIG. are determined as shown as P, As, and Sb, respectively. In order to manufacture a quartz crucible 2 having such an impurity concentration distribution, for example, CVD is applied onto the inner wall of the quartz crucible 2.
This is achieved by depositing SiO2 doped with impurities. [0048] When P is the second impurity, the above distribution is
For example, under the conditions of a growth temperature of 800°C and a growth rate of 90 nm/min, TEOS (Tetraethyl Orthos)
Initially, the partial pressure ratio of
3 and then gradually increasing the partial pressure ratio to 104 when the SiO2 film has a thickness of 100 μm. FIG. 3 is an explanatory diagram of an embodiment of the present invention, and shows an example of the resistivity distribution of a silicon crystal manufactured using the above crucible. As shown in FIG. 3, a crystal with uniform resistivity can be manufactured according to the present invention. [0050] Here, in order to keep the resistivity from 10 Ωcm to within 10%, it is necessary that the impurity concentration distribution on the inner wall of the crucible be within 10% of several tens of values. Furthermore, the present invention is particularly useful when the absolute amount of impurities is small and there is little risk of producing defects that are considered to be obstacles during device formation, and in such cases, the resistivity of the crystal can be reduced to within 10%. In order to make the ratio k2/k1 0.5 to 1.
5 times was sufficient. [0051] Therefore, since a large permissible value can be taken for the impurity concentration distribution on the inner wall of the crucible, there is an effect that manufacturing of the crucible becomes easier. Note that As, B, and Sb can also be provided with a desired concentration distribution by the same CVD method, and the present invention can be applied to these as second impurities. B in FIG. 2 is the B concentration distribution on the inner wall of the crucible calculated from equation 10 when P is the first impurity and B is the second impurity. This is an example applied to the production of crystals. Furthermore, it goes without saying that the present invention is equally applicable to materials other than silicon, such as compound semiconductors. Furthermore, even if the impurity distribution in the inner wall of the quartz crucible is constant,
It goes without saying that the present invention has the advantage of being able to produce more uniform crystals than conventional techniques. [0054] According to the present invention, impurities that compensate for the increase in impurity concentration during crystal production due to segregation are melted into the melt at the same time as the crucible is melted, thereby improving electrical conductivity. Since fluctuations in the carrier concentration in the crystal that contribute to
It greatly contributes to improving the performance of semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の原理説明図[Figure 1] Diagram explaining the principle of the present invention

【図2】  本発明の実施例[Figure 2] Example of the present invention

【図3】  本発明の実施例説明図[Figure 3] Illustration of an embodiment of the present invention

【図4】  従来技術の実施例説明図[Figure 4] Illustration of an example of conventional technology

【符号の説明】[Explanation of symbols]

1,1A  結晶 2,2A  ルツボ 3  融液 4  第一の不純物の増分 5  第二の不純物の増分 1,1A crystal 2,2A Crucible 3 Melt liquid 4 Increment of first impurity 5 Increment of second impurity

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  半導体結晶(1)を第一の導電型とす
る第一の不純物を含みルツボ(2)内に保持された融液
(3)から,引上げ法により単結晶を製造する半導体結
晶の製造方法において, 該ルツボ(2)の内壁に該結
晶(1)を該第二の導電型とする第二の不純物を含有さ
せることを特徴とする半導体結晶の製造方法。
Claim 1: A semiconductor crystal in which a single crystal is produced by a pulling method from a melt (3) containing a first impurity that makes the semiconductor crystal (1) a first conductivity type and held in a crucible (2). A method for manufacturing a semiconductor crystal, characterized in that the inner wall of the crucible (2) contains a second impurity that causes the crystal (1) to have the second conductivity type.
【請求項2】  請求項1記載の半導体結晶の製造方法
において, 上記ルツボ(2)内壁中の厚さ方向につい
ての上記第二の不純物濃度を,該ルツボ(2)内壁の溶
解及び上記融液(3)の固化により増加する該融液(3
)中の該第二の不純物濃度C2 の増加する速さdC2
 /dtが,該融液(3)中の上記第一の不純物濃度C
1 の増加する速さdC1/dt及び該第一の不純物の
偏析係数k1及び該第二の不純物の偏析係数k2を用い
て,  0.5 ×k2/k1<(dC1 /dt)/
(dC2 /dt)<1.5 ×k2/k1となるよう
な分布に形成することを特徴とする半導体結晶の製造方
法。
2. The method for manufacturing a semiconductor crystal according to claim 1, wherein the second impurity concentration in the thickness direction in the inner wall of the crucible (2) is determined by melting the inner wall of the crucible (2) and melting the melt. The melt (3) increases due to solidification of (3).
) the rate of increase in the second impurity concentration C2 dC2
/dt is the first impurity concentration C in the melt (3)
1 using the increasing rate dC1/dt and the segregation coefficient k1 of the first impurity and the segregation coefficient k2 of the second impurity, 0.5 × k2/k1<(dC1/dt)/
A method for manufacturing a semiconductor crystal, characterized in that it is formed in a distribution such that (dC2/dt)<1.5×k2/k1.
JP1046991A 1991-01-31 1991-01-31 Manufacturing method of semiconductor crystal Expired - Lifetime JP2943341B2 (en)

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JP1046991A JP2943341B2 (en) 1991-01-31 1991-01-31 Manufacturing method of semiconductor crystal

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JPH04243995A true JPH04243995A (en) 1992-09-01
JP2943341B2 JP2943341B2 (en) 1999-08-30

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103451728A (en) * 2013-09-26 2013-12-18 江苏协鑫硅材料科技发展有限公司 N-type crystalline silicon and preparation method thereof
CN104790027A (en) * 2014-01-21 2015-07-22 英飞凌科技股份有限公司 Silicon ingot and method of manufacturing silicon ingot
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103451728A (en) * 2013-09-26 2013-12-18 江苏协鑫硅材料科技发展有限公司 N-type crystalline silicon and preparation method thereof
CN104790027A (en) * 2014-01-21 2015-07-22 英飞凌科技股份有限公司 Silicon ingot and method of manufacturing silicon ingot
US10724148B2 (en) 2014-01-21 2020-07-28 Infineon Technologies Ag Silicon ingot and method of manufacturing a silicon ingot
US10337117B2 (en) 2014-11-07 2019-07-02 Infineon Technologies Ag Method of manufacturing a silicon ingot and silicon ingot
US11242616B2 (en) 2014-11-07 2022-02-08 Infineon Technologies Ag Silicon ingot
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CN106591942B (en) * 2016-12-30 2019-06-11 江西赛维Ldk太阳能高科技有限公司 Crucible used for polycrystalline silicon ingot casting and preparation method thereof and polycrystal silicon ingot and preparation method thereof

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