JPH04241299A - Method and circuit for remedying defect of semiconductor memory and semiconductor memory having such circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of using remedy bit in remedy line and to reduce the occupied area of remedy line by replacing bit-related defect concerning a word line or a data line with a common remedy line by the unit of bit. CONSTITUTION:By a discriminating circuit 23, the stored information of X address, Y address and an address register 26 for remedying bit are compared, and when they are coincident, a remedy signal is asserted. When the remedy signal outputted from a discriminating circuit 23 is asserted, a normal word line which follows an input address is selected in an address multiplex system, and then the remedy data line, which is specified by the input address and the remedy signal, is selected. Also, in a non-address multiplex system, for both the word line and the data line, the remedy word line and the remedy data line, which correspond to the input address and the remedy signal, are selected. In either system, bit-related defect is consequentially replaced with the common remedy line by the unit of bit, and the bit-related defect is remedied.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a defect repair technique for repairing defects therein. Regarding effective technology applied to memory (memory).

0002

2. Description of the Related Art The capacity of DRAMs has been increasing year by year, and the density of manufacturing defects has also increased, making it difficult to obtain fully operational products from the beginning. Therefore, a method is generally adopted to repair defective bits by introducing redundancy within the chip. For example, defect repair in a conventional dynamic RAM is made possible by replacing word lines and data lines containing defective bits with repair lines line by line based on the fetched row address and column address.

[0003] Specifically, this is carried out as follows.

All bits are tested in advance, and based on the information obtained, the address of the word line or data line where the defective bit exists is stored in the registers of the row address comparison circuit and the column address comparison circuit, respectively. This register is one in which address information can be written by blowing an electric fuse or a laser fuse. In such dynamic RAM access, the fetched address and
The address information stored in the internal register (address information of the word line or data line where the defective bit exists) is compared, and if they match in this comparison, a normal word line or data line is selected. is prohibited, and a relief word line or relief data line is selected instead. As a result, the word line or data line in which the defective bit exists is replaced with a repair line without defects.

[0005] An example of a document describing defect repair in dynamic RAM is
There is an ``LSI Handbook'' published by Ohmsha Co., Ltd. in Japan.

[0006]

However, when the inventor of the present invention studied the above-mentioned conventional defect relief method, he found the following problems.

In the conventional defect repair described above, instead of selecting the word line or data line in which the defective bit exists, a repair word line or data line is selected, and thereby the word line or data line in which the defective bit exists is selected. By replacing the line with a non-defective relief line,
Since defect relief is performed, for example, in order to relieve a defect of one bit, one word line or data line containing the defective bit is replaced with the relief line. In other words, due to such replacement with a relief line, even bits that can be originally used are replaced with the relief bits of the relief line. The present inventor has revealed that such a relief method has a drawback in that the relief efficiency is low compared to the area occupied by the relief line, in other words, the efficiency of use of relief bits on the relief line is low. .

An object of the present invention is to provide a technique that can improve the efficiency of use of repair bits on repair lines.

Another object of the present invention is to provide a technique that can reduce the area occupied by a relief line for defect relief.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0011]

[Means for Solving the Problems] A brief overview of representative inventions disclosed in this application is as follows.

That is, bit defects associated with a plurality of mutually different word lines or a plurality of mutually different data lines are repaired by replacing each bit with a common repair line.

Furthermore, in order to make the above-mentioned relief method possible, a bit relief address register into which address information of a defective bit can be written, and the storage information of this bit relief address register and an externally input address are provided. Defect relief includes a bit relief determination circuit for comparing bit-related defects in word lines or data lines by replacing them with a common relief line bit by bit based on the comparison results. It forms a circuit.

[0014]Furthermore, bit-type defects related to word lines or data lines are repaired by replacing them bit by bit with a common repair line, and line-type defects in word lines or data lines are repaired by replacing the repair line in line units. This is a relief by replacing it with .

Furthermore, in order to make the above-mentioned repair method possible, a bit repair address register into which address information of a defective bit can be written, and a memory information of this bit repair address register and an input address from the outside are provided. A bit repair determination circuit for repairing a bit defect related to a word line or data line by replacing it with a common repair line bit by bit based on the comparison result, and a defective bit. A line relief address register in which address information of the word line or data line to be saved can be written is compared with the information stored in this line relief address register and an input address from the outside, and based on the comparison result, the word line is Alternatively, a defect relief circuit is formed including a line relief determination circuit for relieving a line defect in a data line by replacing it with a relief line line by line.

When the defect relief circuit is formed as described above, in order to minimize the increase in the area occupied by the relief memory cells in the semiconductor memory device including the defect relief circuit, the bit defect is relieved. A plurality of memory cells for bit relief are connected to a common relief line.

[0017]

[Operation] According to the above-mentioned means, replacing a bit defect related to a word line or a data line with a common repair line bit by bit means, for example, that the defective bit is included when repairing a 1-bit defect. Compared to the conventional method of replacing one data line with a relief line, the utilization efficiency of relief bits in the relief line can be improved and the area occupied by the relief line for defect relief can be reduced.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a DRAM to which a method according to an embodiment of the present invention is applied.

The DRAM shown in the figure is formed on a single semiconductor substrate, such as single crystal silicon, by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

Reference numeral 10 denotes a memory cell array, and this memory cell array 10 is made up of a plurality of one-transistor type dynamic memory cells arranged in a matrix, each having an N-channel type MOSFET and a storage capacitor connected in series, although this is not particularly limited. The memory cells have an equal number of data input/output terminals (MOSFE) on every other complementary data line laid out using the folded data line method.
The selection terminal (gate electrode of MOSFET) of each memory cell is coupled to the word line of the corresponding column. Note that this memory cell array 10 has redundancy introduced therein as will be described in detail later, and it is possible to repair defects by replacing defective bits.

Addressing of the memory cell array 10 involves driving a predetermined word line to a selected level based on the output of the word driver 14, and driving a pair of complementary data lines (not shown) based on the output of the Y switch driver 18. This is performed based on the operation of a switch circuit (not shown) that selectively connects to the complementary common data line.

Each complementary data line is coupled to a signal input terminal of the static sense amplifier 13, although this is not particularly limited. This sense amplifier 13 is configured by mutually cross-coupling the input and output terminals of a CMOS inverter circuit, but is not particularly limited thereto, and has a power switch MOS whose gate receives sense amplifier operation signals having mutually opposite phases.
It is designed to be driven via an FET. Such a sense amplifier 13 is coupled via an I/O (input/output) line 12 to a data input/output circuit 11 that enables data input/output.

Reference numeral 17 denotes an address input section for taking in an address signal from the outside, and this address input section 1
7, an X driver 16, an X decoder 15, a Y driver 20, and a Y decoder 19 are arranged to decode the X address and Y address in stages. Then, based on the decode output of the X decoder 15, the word driver 14 drives a predetermined word line to a selection level, and based on the decode output of the Y decoder 19, the Y switch driver 18 drives the data line for selective connection. switch circuit is driven.

FIG. 2 shows an example of the structure of the address input section 17.

The X address buffer 28 is a buffer for fetching an X address from the outside, and the X address fetched via this X address buffer 28 is sent to the X driver 16, the line repair X-system determination circuit 22, and the bit repair circuit. is input to the use determination circuit 23. This determination circuit 22 compares the X address fetched from the outside via the X address buffer 28 and the information stored in the line relief X-system address register 25, and asserts a relief signal if they match. . This relief signal is part of the X address of the memory cell array 10, and when this relief signal is asserted, a relief word line is selected instead of the regular word line selection according to the input address. Become. This makes it possible to repair line defects in word lines. Here, a linear defect means a defect in which a plurality of defective bits exist continuously in a line. Address information of the word line related to the defective bit detected based on the operation test results of the DRAM of this embodiment is written into the line repair X-system address register 25. This information writing is made possible by blowing out a predetermined fuse constituting the register 25, as will be described in detail later.

The Y address buffer 29 is a buffer for fetching a Y address from the outside, and the Y address fetched via this Y address buffer 29 is sent to the Y driver 20, the line repair Y system determination circuit 24, and the bit repair circuit. is input to the use determination circuit 23. This determination circuit 24 compares the Y address taken in from the outside via the Y address buffer 29 and the information stored in the line relief Y-system address register 27, and asserts a relief signal if they match. . This relief signal is part of the Y address of the memory cell array 10, and when this relief signal is asserted, a relief data line is selected in place of the regular data line that follows the input address. This makes it possible to repair line defects in the data line. The address information of the data line related to the defective bit detected based on the operation test result of the DRAM of this embodiment is written into the line repair Y-system address register 27. This information writing is made possible by blowing a predetermined fuse constituting the register 27, as will be described in detail later.

The determination circuit 23 compares the X address and Y address with the information stored in the bit rescue address register 26, and asserts a rescue signal if they match. When the relief signal output from the determination circuit 23 is asserted, the X, Y
In the address multiplex system in which addresses are taken in over time, a regular word line according to the input address is selected, and then a relief data line specified by the input address and the relief signal is selected. In addition, in the non-address multiplex method in which X and Y addresses are taken in from dedicated terminals, the word line and data line for relief are selected according to the input address and relief signal. Ru. In either method, as a result, bit defects are replaced with a common repair line in bit units, thereby making it possible to repair bit defects. The bit defects referred to here include not only single bit defects in one word line or data line, but also defects other than all bit defects (line defects) in one word line or data line. Can be done. In addition, information writing to the bit relief address register 26 is performed by writing the information to the bit relief address register 26 as described in detail later.
This is possible by blowing a predetermined fuse that constitutes the

Next, the determination circuit 22 and the line relief X
The detailed configuration of the system address register 25 will be explained.

When the number of relief word lines is four,
Correspondingly, the determination circuit 22 and line relief X-system address register 25 include four registers and determination sections 100, 101, 102, 103 and their outputs XR0, XR1, XR2, A NAND gate 200 that obtains the NAND logic of XR3. Here, the output XR of this NAND gate 200 is used as the relief signal, and when it is low level, word line selection is performed according to the input address, and conversely, when it is high level, normal word line selection is prohibited. , thereby making it possible to select a relief word line.

FIG. 4 shows the register and determination section 100.
The detailed configuration of is shown.

In the figure, fuses F1 to F14 form the X-system address register 25 for line relief (see FIG. 1), and these fuses F1 to F14 are designated as F1 to F14.
By selectively fusing 14, it is possible to write the X address of the defective bit. Specifically, it is possible to save the row active side by melting down those in which the subscript of F is an odd number (F1, F3, F5,...).
The subscript of F is an even number (F2, F4, F6,...)
By melting down the high active side, it is possible to rescue the high active side.

In FIG. 4, fuses F1 to F1
The circuit portions other than 4 belong to the determination circuit 22.

The X address input via the X address buffer 28 is a complementary signal, which is A0.
(A0*) to A6 (A6*) (* indicates low active), 2-input NAND gates 36 to 49 are arranged correspondingly, and the output terminals of these NAND gates 36 to 49 The fuses F1 to F14 are respectively coupled. Fuse F1 to F1
P-channel type MOSFETs Q7 to Q13 to which the high potential side power supply Vdd is applied, and further inverters 50 to 56 are coupled to the other end of 4, and N-channel type MOSFETs Q22 to Q28 are arranged at the subsequent stage. MOSF
A P-channel type MOSFET Q4 is coupled to ETQ22, and the MOSFETs Q4, Q22 to Q28 are connected in series between the high potential side power supply Vdd and the low potential side power supply Vss. P-channel type MOSFETQ14 to Q
20 is a line precharge MOSFET, which receives a precharge control signal X from a controller (not shown).
Controlled by DP. This control signal XDP is set to a low level during standby, and set to a high level when ready for operation. Thereby, the precharge is controlled by the control signal
This is performed during standby when DP is set to low level. With this configuration, all of the MOSFETs Q22 to Q28 are turned on only when the address information written in the fuses F1 to F14 matches the input address information, and thereby the control signal XRj* (j is 0 ~
6) is asserted to low level. There are four relief word lines, and the register section and judgment section are arranged correspondingly (see FIG. 3), so any one of the output control signals XR0 to XR3 of the register and judgment sections 100 to 103 When the level is set to low level, the output of the NAND gate 41 is set to high level, thereby prohibiting the selection of a normal word line, and instead enabling the selection of a predetermined relief word line.

In addition, in FIG. 4, power supplies Vdd and Vss
N-channel type MOSFETs Q1, Q2 and a fuse FO are connected in series, and an N-channel type MOSFET Q3 and an inverter 30 are connected thereto, followed by inverters 31, 32 and a two-input NAND gate 3.
3. An inverter 34 is installed. Above MOSFETQ
An internal clock signal that is at a high level during operation is input to the gate of No. 1. When the fuse F0 is blown, the output of the inverter 32 is set to a high level, and the repair enable signal XRE is asserted to a high level, thereby making it possible to repair the defect. Therefore, if bit relief is not required using this circuit, it is sufficient to set XRE to a low level without blowing fuse f0. Further, the relief control signal XRj* is inverted by an inverter 35 so that it can be output as XRj. A P-channel type MOSFET Q6 is coupled to this inverter 35, and the input terminal of the inverter 35 and the power supply Vd
A P-channel type MOSFET Q5 is arranged between the terminal and the terminal d.

By arranging four circuits as described above and further coupling them with a NAND gate 200, an X-system determination circuit 22 and a register 25 are formed (FIG. 2).
, see Figure 3).

In addition, the Y-system determination circuit 24 and the register 27
, furthermore, a determination circuit 23 and a register 26 for bit relief.
Similarly to the X-system, the circuit is also formed including the circuit shown in FIG. However, the determination circuit for bit relief and the register 26 have a circuit configuration that enables determination of the X address and the Y address in order to enable bit-by-bit defect relief. In other words, the circuit configuration includes all of the X-system and Y-system determination circuits 22 and 23 and registers 25 and 27.

Next, a specific example of defect relief will be explained with reference to FIGS. 5 to 13.

FIG. 5 schematically shows the memory cell array 10.

As shown in the figure, the memory cell array 1
0 includes a regular word line 63 that is driven to a selected level according to an externally input address, a regular data line 64 that is selectively coupled to a common data line according to an externally input address, and a defect relief line. As such, a bit relief word line 62, a line relief word line 61, a bit relief data line 65, and a line relief data line 66 are provided. Dynamic relief memory cells are coupled to them. In this embodiment, although not particularly limited, the word line 62 for bit relief and the data line 6 for bit relief
5 has a single structure, and the line relief word line 61 and the line relief data line 66 have a plurality of lines. According to the configuration of FIG. 3, the number of line relief word lines 61 and line relief data lines 66 are both four, corresponding to the number of registers and determination sections.

Defect relief in line units is performed as follows.

FIG. 6 shows how defects are relieved on a line-by-line basis on the line relief word line 61.

In the i-th regular word line 63i and the m-th regular word line 63m, a circle mark means a normal bit, and an x mark means a defective bit. A case will be considered in which defective bits exist in the normal word lines 63i and 63m and are repaired by line repair word lines 61b and 61c.

By blowing a predetermined fuse in the X-system address register 25 for line relief shown in FIG. 2, address information regarding the word lines 63i and 63m is written into the register 25. Thereby, the determination circuit 22 compares the address input from the outside via the X address buffer 28 and the information stored in the register 25, and if they match in the comparison, the address of the regular word line 63 is compared. Relief word line 6 instead of selection
1b is selected, and the relief word line 61c is selected in place of the regular word line 63m. Such word line replacement makes it possible to repair defects in the regular word lines 63i and 63m. Incidentally, such line-by-line repair is possible, apart from the case of line-based defects in which all bits of one word line are considered defective, as shown in Figure 6. If a bit (◯) exists, even the normal bit is replaced on the relief word line, which impedes the effective use of the relief word line. The same thing can be said about line-by-line defect relief for data lines for line relief.

FIG. 7 shows how a line-by-line defect is relieved on the data line for line relief.

In the i-th regular data line 64i and the p-th regular data line 64p, a circle mark means a normal bit, and an x mark means a defective bit. A case will be considered in which defective bits exist in the normal data lines 64i and 64p and are repaired using the line repair data lines 66b and 66c.

Address information regarding the data lines 64i and 64p is written into the register 27 by blowing out a predetermined fuse in the line relief Y-system address register 27 shown in FIG. Thereby, the determination circuit 24 compares the address input from the outside via the Y address buffer 29 and the information stored in the register 27, and if they match in the comparison, the regular data line 64i The relief data line 66b is selected instead of the selection of , and the relief data line 66c is selected instead of the normal data line 64p. By replacing such data lines, regular data lines 66i, 66p
defect relief is possible. Incidentally, such line-by-line repair is possible, except in the case of a line defect in which all bits of one data line are considered defective, as shown in FIG.
As shown in , there are defective bits (×) and normal bits (
○) exists, even the normal bits are replaced on the relief data line, which impedes effective use of the relief data line.

Next, a specific example of bit-by-bit defect relief will be explained.

In FIG. 8, regular data lines 64g, 6
When a plurality of consecutive defective bits are present on the 4k as indicated by cross marks, these defective bits are repaired by replacing them with a single bit repair data line in units of a plurality of bits. That is, the regular data lines 64g, 64
By replacing only the defective bits on k onto the common relief data line 65, the defective bits are relieved. Such defect repair in units of multiple bits is performed by the determination circuit 2.
This is possible by omitting a part of the row address input to 3 so that normal bits are not replaced. Thereby, the repair bit on the bit repair data line 65 can be accessed in place of the defective bit on the normal data lines 64g, 64k.

This kind of bit-by-bit defect relief differs from the above-described line-by-line defect relief (see FIG. 7) in that the replacement of normal bits in the regular data lines 64g and 64k is performed by the determination circuit 23. Excluded by judgment,
As a result, only the defective bit is replaced, and as a result, one repair line is sufficient to repair a bit defect included in two regular data lines, making effective use of the repair line. can.

As shown in FIG. 9, even when defective bits are scattered, a single bit relief data line 65
relief is possible. In this case, regular word line 6
3 is selected, the bit relief data line 65 is selected in accordance with the output of the determination circuit 23, thereby replacing the defective bits on the plurality of data lines onto the single relief data line 65.

The bit relief shown in FIG. 10 enables relief when a plurality of defective bits exist consecutively on each of a plurality of word lines using a single bit relief word line 62. be. Such relief can be achieved, for example, in the non-address multiplex system by the judgment circuit 2.
This is possible by omitting part of the column address input in 3.

Furthermore, as shown in FIG. 11, the defective bits can be relieved by replacing scattered defective bits with a single word line 62 for bit relief.

Furthermore, as an example of effectively utilizing the advantages of the non-address multiplex system, area defects can be repaired using a single repair line by replacing both row and column addresses with repair addresses. It can be done. For example, as shown in FIG. 12, area defects can be replaced with a single bit relief data line 65, and as shown in FIG. Bit relief word line 6
It can be saved by replacing it with 2.

According to the present invention, the following effects can be obtained.

(1) Bit-related defects are removed by a common repair line 62
For example, replacing one word line or data line containing the defective bit with a repair line line by line to repair one bit defect is more normal. Since even bits do not need to be replaced with relief lines, the utilization efficiency of the relief bits in the relief lines can be improved accordingly, and the area occupied by the relief lines for defect relief can thereby be reduced. .

(2) In line-by-line defect relief,
Although the number of replacement bits is large, the size of the judgment circuit and registers can be small, so bit-related defects in word lines or data lines can be repaired by replacing them bit by bit with the common repair line 62 or 65, and the word line Alternatively, it is possible to select a repair method according to the actual defect situation, such as repairing a linear defect in a data line by replacing it with a repair line line by line.
This method is considered to be extremely effective in improving relief efficiency and, furthermore, improving yield.

(3) Even if the number of relief bits is significantly increased due to the effect of (1) above, the increase in the area occupied by the relief memory cells is small, so an increase in chip size can be prevented.

(4) Compare the bit relief address register 26 into which address information of a defective bit can be written, and compare the stored information of this bit relief address register 26 with an input address from the outside, and based on the comparison result. , and a bit repair judgment circuit 23 for repairing bit defects related to word lines or data lines by replacing them with a common repair line in bit units, thereby making it possible to effectively repair defects in bit units. can be done.

(5) Compare the bit relief address register 26 into which address information of a defective bit can be written, and compare the stored information of this bit relief address register 26 with an input address from the outside, and based on the comparison result. , a bit repair determination circuit 23 for repairing a bit-related defect in a word line or data line by replacing it with a common repair line bit by bit; The line relief address register 25 or 27 in which address information can be written is compared with the memory information of this line relief address register 25 or 27 and the input address from the outside, and based on the comparison result, the word line or data The inclusion of the line repair determination circuit 22 or 24 for repairing linear defects in lines by replacing them with repair lines on a line-by-line basis means that the defect relief on a bit-by-bit basis and the defect relief on a line-by-line basis are included. can be performed well.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, in order to keep the layout area of the determination circuits 22, 23, 24 and the registers 25, 26, 27 as small as possible, it is preferable to configure the registers with an electrically rewritable EPROM. In this case,
The EPROM may be housed together with the DRAM in a common package, or it may be placed on-chip on the DRAM to form one LSI.

Note that the above-mentioned defect relief method is based on the determination circuit 2.
2, 23, 24 and registers 25, 26, 27, the defect relief method is not limited by such a configuration.

[0063] In the above explanation, the invention made by the present inventor will be mainly explained in relation to DRA, which is the application field that is the background of the invention.
Although the present invention has been described for the case where it is applied to M, the present invention is not limited thereto, and can be widely applied to semiconductor devices such as static RAM and other semiconductor memories, and furthermore, data processing devices that include them. can.

The present invention can be applied to conditions including at least a plurality of memory elements.

[0065]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, by replacing a bit defect related to a word line or data line with a common repair line bit by bit, for example, in order to repair a 1-bit defect, one data line containing the defective bit is used. Compared to the conventional method of replacing the relief line with a relief line, the utilization efficiency of relief bits in the relief line can be improved and the area occupied by the relief line for defect relief can be reduced.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration block diagram of a DRAM that is an embodiment of the present invention.

FIG. 2 is a configuration block diagram of an address input section in FIG. 1;

FIG. 3 is a block diagram of the main parts in FIG. 2;

FIG. 4 is a detailed circuit diagram of the main parts in FIG. 3;

FIG. 5 is a schematic diagram of a memory cell array.

FIG. 6 is an explanatory diagram of line-by-line defect relief for line relief word lines.

FIG. 7 is an explanatory diagram of line-by-line defect relief for line relief data lines.

FIG. 8 is an explanatory diagram of relief of a plurality of consecutive defective bits to a data line for bit relief.

FIG. 9 is an explanatory diagram of relief of scattered defective bits to a bit relief data line.

FIG. 10 is an explanatory diagram of relief of continuously existing defective bits to a word line for bit relief.

FIG. 11 is an explanatory diagram of relief of scattered defective bits to word lines for bit relief.

FIG. 12 is an explanatory diagram of relief of an area defect on a data line for bit relief.

FIG. 13 is an explanatory diagram of relief of an area defect to a word line for bit relief.

[Explanation of symbols]

10 Memory cell array 11 Data input/output circuit 12 I/O line 13 Sense amplifier 14 Word driver 15 X-system address register for relief 26 Address register for bit relief 27 Y-system address register for line relief 28 X-address buffer 29 Y-address buffer 61 Word line for line relief 62 Word line for bit relief 63 Regular word line 64 Regular data line 65 Data line for bit relief 66 Data line for line relief

Claims (5)

[Claims] 1. A defect repair method for a semiconductor memory device in which a plurality of memory cells are coupled to a word line and a data line, in which a bit-type defect in a word line or a plurality of data lines is fixed to a common repair line. A method for repairing defects in a semiconductor memory device, characterized in that repair is performed by replacing units. 2. In a defect repair method for a semiconductor memory device in which a plurality of memory cells are connected to a word line and a data line, bit defects in the word line or the data line are repaired bit by bit to a common repair line. 1. A defect repair method for a semiconductor memory device, characterized in that the defect is repaired by replacement, and a line defect in a word line or data line is repaired by replacing the repair line line by line. 3. In a defect relief circuit for a semiconductor memory device in which a plurality of memory cells are coupled to a word line and a data line, a bit relief address register in which address information of a defective bit can be written; To compare the information stored in the address register with the input address from the outside and, based on the comparison result, repair bit defects in the word line or data line by replacing them with a common repair line bit by bit. 1. A defect relief circuit for a semiconductor memory device, comprising a determination circuit for bit relief. 4. In a defect relief circuit for a semiconductor memory device in which a plurality of memory cells are coupled to a word line and a data line, a bit relief address register in which address information of a defective bit can be written; To compare the information stored in the address register with the input address from the outside and, based on the comparison result, repair bit defects in the word line or data line by replacing them with a common repair line bit by bit. a bit repair determination circuit, a line repair address register into which address information of a word line or data line connected to a defective bit can be written, and a line repair address register that stores information stored in the line repair address register and an input address from the outside. A semiconductor characterized in that it includes a line repair determination circuit for comparing and repairing a line defect in a word line or data line by replacing it with a repair line line by line based on the comparison result. Memory device defect relief circuit. 5. A semiconductor memory device comprising the defect relief circuit according to claim 3 or 4, and in which a plurality of bit relief memory cells for relief of the bit-type defects are coupled to a common relief line.