JPH04235636A - Microprocessor - Google Patents

Abstract

PURPOSE:To obtain a microprocessor capable of executing the exclusive control only by combining a small number of simple instructions. CONSTITUTION:A data storage part of the microprocessor is provided with an SR flip-flop 403 stored that whether a memory 200 is locked or not. Thus it is possible to prevent such a case where the same resources are simultaneously locked owing to the conflict of test-and-lock instructions which are produced in plural processes since the flip-flop 403 stores a fact whether the memory 200 is kept in a lock state or not. Then a test-and-set instruction is divided into simple instructions and can be executed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a microprocessor, and more particularly to the structure of its data storage section.

0002

[Background Art] With the advancement of VLSI technology, the price of microprocessors has decreased and their reliability has improved, so parallel processing in which multiple microprocessors are connected to perform high-speed data processing has become popular. There is. However, if the processes divided among a large number of microprocessors are processed completely independently, problems may occur. In particular, when multiple processes (hereinafter referred to as processes) use a shared resource, such as a storage device, at the same time, it is important to limit the number of processes that can be used at the same time to one and run them exclusively. is often not guaranteed.

In order to solve these problems, conventional microprocessors have managed processor resources using, for example, test-and-set instructions.

[0004] For example, "Mitsubishi M3" published by Mitsubishi Electric Co., Ltd.
2 family MPU M32/100M33210
Pages 222 to 223 of "User's Manual" describes the BSETI command for realizing exclusive control. The function of the BSETI instruction is to set bits with interlocks (setbi
t with interlock), and the inverted value of the specified bit is set as the Z flag (Z flag).
g), then that bit is set. At this time, these two operations are performed with the bus locked.

[0005] Also, Prentice Hall Co.
ntice-Hall Inc. (Englewood
Series 32000 Programmer's Reference Manual (Series 32000 Pro) published by Cliffs, NJ 07632)
Grammer's Reference Manua
There is a similar description on pages 6-185 to 6-187 of ``l)'', which states that after the contents of memory or registers are copied to the F flag of the processor status register (PSR) by the SBITI instruction, the contents are set to 1. During this time, the CPU's Interlocked Operation
n) It is stated that the output pin is in the active state and access to the semaphore bits is interlocked.

The above-mentioned conventional example is a so-called CISC (Co
complex Instruction Set Com
It is a microprocessor belonging to the type putter),
Macro instructions such as BSETI and SBITI are realized by executing a multi-step microprogram. To prevent processing from being interrupted by interrupts from other processors during the execution of these instructions, and to prevent the consistency of instruction execution from being guaranteed, the bus is locked,
Activating the connection operation signal.

However, if such a method is adopted, in the case of a general processor with a pipeline processing structure that performs instruction fetch, data fetch, execution, result storage, etc. in a flow processing manner, the pipeline stages of instruction execution are As the number of execution cycles increases, the stage following the pipeline stage becomes empty, and data movement in the preceding stage stops, resulting in pipeline blockage (pipeline stall) and decreasing processing efficiency. will decrease.

[0008] In order to solve this problem, so-called RISC (Reduced Inst.
A RISC architecture-based processor has been proposed, and commercial microprocessors based on the RISC architecture are already on the market.

The instruction set of the Am29000, known as a typical RISC microprocessor, was published by Nikkei B.
MC1-303- from page MC1-303-151 of “Nikkei Data Pro Microprocessor” published by Company P
It is disclosed on page 163. In the case of the Am29000, which executes instructions in one clock cycle, instructions that require the execution of complex procedures such as test and set are not supported. According to the above-mentioned publicly known document, by activating the 9th bit of a dedicated register (current processor status register) that can only be accessed in a privileged mode called supervisor mode, the LOCK pin of the processor becomes active and other The bus is controlled not to be released even if a bus release request by the BREQ signal is input from the processor. This feature allows you to maintain consistency in processing.

0010

As described above, conventional CISC processors have a problem in that pipeline processing efficiency decreases when complex instructions such as test-and-set are executed. Conversely, 1 instruction is 1
In the case of a RISC processor that executes in clock cycles, there is a problem in that complex instructions such as test and set cannot be implemented in hardware.

In the case of the above-mentioned Am29000, when attempting to realize exclusive control, first set the supervisor mode, write to the dedicated register, activate the LOCK signal pin, occupy the bus, and perform exclusive control. Read the memory address that represents the resource to be used, and judge the read result. For example, if the read result is "0", write "1" to the same address, and then rewrite to the dedicated register. LOC
Software must take steps to deactivate the K signal pin and release the bus to other processors. As described above, since a complicated procedure must be executed, the efficiency of program execution is extremely low, and there is a strong possibility that the execution of other processes will be hindered because the bus will continue to be occupied during this time.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a microprocessor that can realize exclusive control by combining a small number of simple instructions.

[0013]

[Means for Solving the Problems] A microprocessor according to the present invention is capable of executing a series of instructions of the same type by introducing means for storing information that a series of instructions used to realize exclusive control is being executed. A microprocessor is provided with a data storage device that delays the process.

[0014]

[Operation] In this invention, for example, test and
Data storage that is granted to the microprocessor only when this data storage device is not in the locked state when a lock command is given, and the data is "0" as a result of reading the memory according to the address given at the same time. Puts the device in the locked state (second state) and outputs "0" as the condition code, and the resulting condition code is "0".
Accordingly, when a set and unlock command is given, "1" is written to the above address and at the same time the data memory is unlocked and brought into an unlocked state (first state).

[0015]

[Embodiments] Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

FIG. 1 shows a data storage section of a microprocessor according to the present invention. In the figure, 1 is a data storage section, 100 is an input latch, 101, 102,
103 is its control bit latch section, address latch section,
This is an input data latch. Reference numeral 200 denotes a memory section 30 as a first storage means of an addressing type, that is, data can be read and written by specifying an address.
0 is an output latch section, 301 and 302 are its condition code latch section, output data latch section, and 303 is a lock state latch section. Also, 401 is a NAND gate, 4
02 is in the unlocked state (first
403 is a set/reset flip-flop as a second storage means; 404, 406, 408 are inverters; 405
is an AND gate, and 407 is a NOR gate.

Next, the operation will be explained. When information having control information, an address, and data arrives at the data memory section 1 according to pipeline control, the control bit section 101 of the input latch 100 receives a control signal (( R/bar W, T&L, S&U) is address part 1
02 contains a memory address pointing to data representing the resource subject to exclusive control, and the data section 103 contains:
Data to be written into the memory is latched in accordance with the rising edge of the timing signal φ.

Of the instruction set of a microprocessor,
When a test and lock command is given, the control bit of the control bit section 101 is R/W=
1, T&L=1, S&U=0. At this time, the least significant bit of the data read from memory 200 is inverted by inverter 406 and input as the second input of NAND gate 401. The other two inputs of the NAND gate 401 are the T&L bit and the inverted output of the locked state latch 303 output. When all these inputs become "1", the output of the NAND gate 401 becomes "0" and the SR flip-flop 403 (hereinafter referred to as SRFF) is set to store that the memory is in a locked state. That is, when a test and lock instruction is given, the content of the data indicated by the address accompanying this instruction is "0", and the memory is in an unlocked state,
Controlled to transition to the locked state.

Furthermore, even if a test-and-lock instruction is given, if the address has already been set (referred to as lock-unable state 1), or if the memory has already been locked by a preceding test-and-lock instruction. (referred to as unlockable state 2), OR
Since the output of the gate 407 becomes "1", the output of the AND gate 405 becomes "1", "1" is latched in the condition code section 301 of the output latch 300, and the execution of the test and lock instruction is unsuccessful. I remember that it was. Further, at this time, the SRFF 403 is neither set nor reset, so the original state is saved in the lock state latch section 303.

[0020] As a result of executing the test and lock instruction, if the condition code becomes "0" and the execution is successful,
A set and unlock instruction is then issued. The set-and-unlock instruction is accompanied by the memory address and data "1" used when executing the paired test-and-lock instruction. Further, the control bits of the control bit section 101 are R/W=0, T&L=
0, S&U=1. At this time, input latch 1
Data "1" latched at 00 is written to the address to indicate that the resource to be exclusively controlled is being occupied. Further, the S&U signal is inverted by an inverter 404 and further passed through an AND gate 402 to an SRFF 403.
is given to reset SRFF and release the locked state.

As is clear from the above explanation, "lock" in this embodiment means prohibition of execution of new test-and-lock instructions during the lock period, and is different from conventional microprocessors. It completely prohibits bus acquisition requests and does not inhibit the execution of other processes.

Next, after the set-and-unlock instruction is executed, processing using exclusively allocated resources is executed. After executing exclusive processing, "0" is written to the above address to release the resource to other processes.

The above procedure for exclusive process execution is shown in the flowchart of FIG.

In FIG. 2, a test and lock instruction is executed in step S1, and it is determined in step S2 whether the condition code CC is 1 or not. If the determination result is 1, the process returns to step S1, and if the determination result is other than 1, the process proceeds to step S3. Step S3
, execute a set and unlock instruction,
In step S4, the exclusive execution section is executed. Then, in step S5, a zero write instruction for resetting is executed. Note that in step S2, the delay operation of the test-and-set instruction that returns to step S1 is actually performed by software.

[0025] In Fig. 2, [A] indicates that the target address is address A, and [A, 0] indicates that the address is address A and the data value is "0". .

As described above, in the above embodiment, the data storage section is provided with a flip-flop for storing whether or not it is in a locked state, and in the locked state, execution of a new instruction requesting a lock is delayed. The following effects can be obtained.

In other words, the number of clock cycles required for processing is large, such as the test and set instruction, and it is necessary to guarantee processing consistency (always outputting correct results without being affected by other processes). During the execution of an instruction, a flip-flop indicates that the data storage is locked, which prevents instructions that require a lock from being executed at the same time, and allows multiple instructions that require processing consistency to be executed simultaneously. can be divided into simple instructions and executed, improving pipeline execution efficiency.

Furthermore, while the divided instructions are being executed, the data storage unit is in a locked state, but it is possible to mix the execution of instructions belonging to other processes, and the data storage unit is shared between processes. Since only the execution of instructions that disturb the consistency of the divided instruction execution using resources is automatically delayed, it is possible to realize parallel execution of multi-processes including exclusive execution parts without special control. can.

Therefore, as shown in FIG. 6, a data-driven (data flow) microprocessor in which the instruction execution order is dynamically determined according to data dependencies and which realizes parallel execution of multiple processes at the instruction level parallelism is required. It is especially effective when applied. In addition, in this Figure 6, 60
1 is an input control section, 602 is a queue memory section, 603 is a data storage section, 604 is an arithmetic processing section, 605 is a program storage section, and 606 is an output control section.

Furthermore, in the above embodiment, one instruction (test and lock) determines the data stored at the address and sets the lock state, and also rewrites the data value at the address and sets the lock state. Since each release is a single instruction (set and unlock), the overall number of instructions is reduced, compared to conventional RI.
Even compared to SC processors, more efficient processing is possible.

In the above embodiment, only the decoded signals (R/W, T&L, S&U) are shown.
Although the instruction decoder is not shown, the instruction decoder may be included in this memory section. Also, each control signal may be directly applied without an instruction decoder.

In the above embodiment, the data read from the memory is input to the data section 302 of the output latch, but as shown in FIG. 3, either the input data or the memory read result can be selectively latched. Alternatively, the same effect as in the above embodiment can be obtained. In FIG. 3, 409 is a data buffer with output tri-state control, and 410 is an inverter.

Furthermore, in the above embodiment, the clock signal φ
However, as shown in FIG. 4, the latch signal may be generated by handshake circuits 500 and 501 made up of C elements that detect coincidence or mismatch between two input signals. Regarding the circuit configuration example and operation of this C element, please refer to Japanese Unexamined Patent Application Publication No. 63-204 by the present applicant.
The circuit configuration is described in detail in Japanese Patent No. 355, and FIG. 5 shows an example of the circuit configuration extracted from this publication. In the figure, 10
13 (1014) is a C element, R-S flip-flops 1015, 1016 (1017, 1018), 4-input NAND gate 1131 (1141), inverter buffers 1134, 1135, 1139 (1144,
1145, 1149), 2-input NAND gate 1138
(1148). In addition, 1011 (1
012) is a 40-bit data latch, and the 1-bit latch 1110 (1120) is the inverter buffer 1111, 1112, 1113 (1121, 1122,
1123) and transfer gates 1114, 111
5 (1124, 1125).

FIG. 7 shows the configuration of a general data processing device using the C element shown in FIG.
The same reference numerals as in FIG. 5 indicate the same parts. In the figure, 11
01 is a memory, and 1102 is a combinational logic circuit.

Further, in the above embodiment, a 1-bit condition code is output, but if the test and lock instruction ends in failure, the condition code indicates that the condition is caused by the above-mentioned "unlockable state 1". The condition code may be made of multiple bits in order to identify whether the condition is due to the lock condition or the “unlockable state 2”.

Furthermore, in the above embodiments, it is not specified whether the data storage device is an external memory, an internal memory, or a register, but the present invention applies to any of these storage devices. Needless to say, it is also applicable.

Furthermore, in the above embodiment, only the test-and-set instruction that compares one bit has been explained, but consistency in execution of compound instructions such as the compare-and-set instruction that involves comparison of multiple bits is important. It is widely applicable in cases where the

[0038]

As described above, in the microprocessor according to the present invention, the data storage section is provided with a flip-flop for storing whether or not the data storage section is in the locked state, and when the data storage section is in the locked state, a new Since the execution of instructions that request a lock is delayed, the test
Multiple instructions, such as AND and set instructions, that require a large number of clock cycles to process and that must guarantee processing consistency (always outputting the correct result without being affected by other processes) It can be divided into simple instructions and executed, improving pipeline execution efficiency.

Furthermore, while the divided instructions are being executed, the data storage unit is in a locked state, but it is possible to mix the execution of instructions belonging to other processes, and the data storage unit is shared between processes. Since only the execution of instructions that disturb the consistency of the divided instruction execution using resources is automatically delayed, it is possible to realize parallel execution of multi-processes including exclusive execution parts without special control. This will have the effect of providing an effective technique for realizing exclusive use of shared resources in the parallel processing field in the future.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a data storage section of a microprocessor according to the present invention.

[Figure 2] Test and set, test and set
FIG. 12 is a flowchart when a lock instruction, a set-and-unlock instruction, a comparison instruction, and a memory write instruction are divided and executed.

FIG. 3 is a block diagram illustrating an example of the configuration of the data storage unit having the configuration shown in FIG. 1, in which a path for storing and outputting input data is added.

4 is a diagram showing an example in which the output of a handshake control circuit (C element) is used as a control signal for an input/output latch instead of a clock signal φ in the data storage section having the configuration shown in FIG. 1;

FIG. 5 is a logic circuit diagram showing an example of a circuit configuration of a C element and data latch control using the C element.

FIG. 6 is a block diagram showing a configuration example of a data-driven microprocessor to which the present invention can be applied.

7 is a block diagram showing the configuration of a general data processing device using the C element shown in FIG. 5. FIG.

[Explanation of symbols]

100 Input latch 101 Control bit latch section 102 Address latch section 103 Input data latch section 200 Memory section 300 Output latch section 301 Condition code latch section 302 Output data latch section 303 Lock state latch section 401 NAND gate 402 AND gate 403 Set/reset/ flip flop 4
04 Inverter 405 AND gate 406 Inverter 407 NOR gate 408 Inverter 409 Data buffer with output tristate control 410 Inverter 500 C element 501 C element

Claims (1)

[Claims] Claim 1: Addressable first storage means;
a second storage means for storing the state of the first storage means;
In response to a first instruction accompanied by an address for the first storage means, when the value of data stored at the address is in the first state, the state of the second storage means is changed to a second state.
, and in response to a second instruction accompanied by an address for the first storage means, sets the value of the data stored at the address to the second state, and the second storage means set the state to the first state, and set the state to the first state.
1. A microprocessor comprising: a data storage section having an address for the storage means; and control means for controlling the writing of data to the address in response to a write command accompanied by data.