JPH0423076A - Preprocessing system for hardware automatic design system - Google Patents

Abstract

PURPOSE:To efficiently perform the design work by unifying a language for verification and a language for function description. CONSTITUTION:Function specifications used for verification of logic circuit functions are inputted to an input part 11 as they are, that is, function specifications where an algorithm is described in the C language (language for function description) are inputted there, and the same processing as a preprocessor in the C language processing system like file inclusion, character string substitution, macro substitution, or conditional compilation indicated by #inc/ude, #define, #ifdef, or the like is performed, and the results are transferred to an analyzing part 12. The analyzing part 12 performs deletion processing of parts unnecessary for logic design out of function specifications, memory information request, structure analysis, or the like while having conversations with a user through a user interface part 13, and the results are stored in an analysis result storage part 15. Thus, misconversion between two languages is eliminated to efficiently perform the design work.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a preprocessing method for an automatic hardware design system for designing hardware from functional specifications of a logic circuit.

[Prior Art] In recent years, as LSIs have become larger and more customizable, combinators have been used in logic design to improve efficiency and popularize the design. Generally, these systems are called automatic hardware design systems, and are systems in which the functions of the hardware to be designed are described, automatically synthesized as a logic circuit, and verified through simulation. For such systems, a method C (hereinafter, such a language will be referred to as a function description language) is known in which hardware functions are described in a special language. For example, in Japanese Patent Laid-Open No. 2-39376, a special RTL language is prepared as an input for logic synthesis. Also, in general, when describing hardware functions using such a language, it is necessary to verify whether the algorithm is correct.
Currently, this is verified by programming using a high-level programming language (hereinafter such a language will be referred to as a verification language), which is a general-purpose computer language.

[Problem to be solved by the invention] As described above, when attempting to implement a devised algorithm into hardware, the algorithm is usually verified by using a computer to verify whether it works normally using a verification language that is a high-level programming language. We are currently checking. After this confirmation work, we will rewrite the description in the functional description language and then create the logic circuit using the automatic hardware design system, so we will have to learn two languages, write the functional specifications again, and rewrite them. There was a problem that conversion errors were introduced.

In order to solve the above problems, the present invention integrates a verification language and a function description language so that hardware designers do not have to learn two languages. The purpose is to eliminate conversion errors between the two and to streamline the entire design process.

``Means for Solving EaM'' To achieve the above object, the invention described in claim 1 includes an input unit for inputting functional specifications of a logic circuit, and a bidirectional interface for controlling conversation with a user. a CAD data generating section that generates CAD data for a logic synthesis system from the analysis results, and synthesizes a logic circuit from the functional specifications of the logic circuit. In automatic hardware design system,
The input section inputs the functional specifications used when verifying the logic circuit function as is, obtains instructions on unnecessary parts of the functional specifications and memory usage information from the user interface section, and inputs/outputs variables, connection relationships, and calculations. The present invention is characterized in that it analyzes the order of occurrence, etc., and generates CAD data for an automatic hardware design system.

[How it works: First, the devised algorithm is written in a verification language and verified by a computer.

Next, the algorithm written in the verification language is input as it is written in the functional description language, and after obtaining unnecessary parts and information necessary for hardware implementation through a conversation with the user, the analysis section Analyze the structure and generate and output CAD data that can be used in automatic hardware design systems.

[Example] An example of the present invention will be described below in detail with reference to the drawings. In this embodiment, C language is used as the verification language/function description language, but it goes without saying that other high-level programming languages may be used.

FIG. 1 is a block diagram showing an embodiment of an automatic hardware design system according to the present invention.

10 is a functional specification written in a functional description language, 11 is an input section, 12 is an analysis section, 13 is a user interface section, 14 is a CAD data generation section, 15 is an analysis result storage section, 16 indicates a CAD data storage section.

The input unit 11 inputs a functional specification in which an algorithm is written in C language (a functional description language), and inputs s+nclude,
=define, :1fdef etc. to perform the same processing as the briprocessor of the C language processing system, such as inclusion of the file specified by ↓, character string replacement, tuna replacement, and conditional compilation. The results are sent to the analysis section 12 twice.

The analysis unit 12 performs deletion processing, requests for memory information, structural analysis, etc. while communicating with the user through the user interface unit 13 for parts of the functional specifications that are unnecessary for logical design.
The analysis results are stored in the storage section 15.

FIG. 2 is a flowchart showing the processing flow of the analysis section in this embodiment.

An example of circuit design for the quick sort algorithm shown in FIG. 3 will be explained in more detail using FIG. 2.

Step 1 The user interface section 13 prompts the user to input parts unrelated to hardware implementation in the form of questions.

If unnecessary parts are deleted from this instruction, the result will be as shown in Fig. 4.

Step 2 Furthermore, as shown in FIG. 5, the user interface unit 13, through a conversation with the user, obtains information (types) about the type of memory to be used for the memory area secured by memory allocation such as an array.

size, configuration, speed, etc.).

Step 3 For the functional specifications from which unnecessary parts were removed in Step 1, identifiers, keywords, constants, character strings, operators, delimiters, etc. are determined, and a correspondence table between input words and their attributes is created. Perform lexical analysis.

Step 4 Perform structural analysis using the following steps based on the functional specifications and the results of lexical analysis.

- Divide into function units.

- Variables are classified and extracted into the following two types depending on the location where they are defined.

When outside a function: external variable.

Internal variables when inside a function.

When used as an operator, the inputs and outputs related to it A pair of variable name and operator.

・Sentence sequences and control sentences 1f-then, for, wh
ile.

The order in which operations occur is analyzed from the order in which do-while, gol, o, function calls, etc. appear.

(However, recursive calling of functions is realized using a stack.) Step 5 The analysis results are stored in the analysis result storage section 15.

The CAD data generation unit 14 inputs the analysis results stored in the analysis result storage unit 15 into the automatic hardware design system (for example, data flow and time charts as shown in FIG. 6, and memory information as shown in FIG. 7). etc.) and stores it in the CAD data storage section 16.

[Effects of the Invention] As described above, according to the invention described in claim 1, it is no longer necessary to learn a special language for hardware design, and the five-pronged algorithm can be verified, allowing the user to concentrate on the design. Because the user language is entered as is, conversion errors are eliminated and the overall design time is also reduced. Even system engineers who are not familiar with hardware design will be able to design hardware. Furthermore, by incorporating the preprocessing method based on the present invention into a unique automatic hardware design system, an automatic hardware design system using general-purpose high-level programming language input can be constructed.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a flowchart showing the processing flow of the analysis section, and Fig. 3 is a circuit design algorithm written in a verification language (functional description language). Example program shown. FIG. 4 shows an example of a program with unnecessary parts deleted, FIG. 5 shows an example of conversation in the user interface section, FIG. 6 shows an example of data flow and time chart generation, and FIG. 7 shows an example of memory information generation. 10 - Functional specifications, 11 - Input unit, 12 - Analysis unit, 13 User interface unit, 14 - C, AD data generation unit, 15 - Analysis result storage unit, +6 - CAD data storage unit.

Claims (1)

[Claims] 1. An input section for inputting the functional specifications of the logic circuit, a user interface section for controlling conversation with the user, an analysis section for analyzing the functional specifications of the logic circuit, and CAD data for the logic synthesis system based on the analysis results. In an automatic hardware design system that synthesizes a logic circuit from the functional specifications of the logic circuit, the input section inputs the functional specifications used when verifying the logic circuit functions as they are, and generates CAD data. Obtain instructions on unnecessary parts of specifications and memory usage information from the user interface section, analyze input/output and coupling relationships of variables, order of occurrence of operations, etc., and generate CAD data for an automatic hardware design system. A preprocessing method for an automatic hardware design system characterized by the following.