JPH04229651A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To ensure the sufficient area of a capacitor by a method wherein an electrode layer to be used as a lower-part electrode for the capacitor is connected to an impurity region situated between an element isolation region and a gate electrode and it is formed on a sidewall and a second insulating layer. CONSTITUTION:A conductive layer 8 is connected to an impurity region 3 situated between gate electrodes 5; it is formed on the gate electrodes 5 so as to be spread and extended via a first insulating layer 12. A second insulating layer 9 is formed on the conductive layer 8. Sidewalls 13, 14 are formed on sidewall parts of the gate electrodes 5, the conductive layer 8 and the second insulating layer 9. An electrode layer 6 to be used as a lower-part electrode for a capacitor is connected to the impurity region situated between an element isolation region 2 and the gate electrodes 5; it is formed on the sidewalls 13, 14 and the second insulating layer 9. Thereby, the surface area of the capacitor is increased in the same plane area as in conventional cases by utilizing the difference in level of the conductive layer, and it is possible to ensure the sufficient area of the capacitor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, impurity regions are formed at predetermined intervals in a region surrounded by an element isolation region on a semiconductor substrate, and the impurity regions are The present invention relates to a semiconductor device in which a gate electrode is formed with a gate insulating film interposed therebetween, and a method for manufacturing the same.

0002

2. Description of the Related Art Conventionally, with the remarkable spread of information equipment such as computers, the demand for semiconductor memory devices has rapidly expanded. In addition, semiconductor memory devices are required to have a functionally large storage capacity and to be capable of high-speed operation. Along with this, technological development regarding high integration, high speed response, and high reliability of semiconductor memory devices is progressing.

Among semiconductor memory devices, DRAM (Dynamic RAM) is one that allows random input/output of storage information.
ic Random Access Memory
y) is known. Generally, a DRAM is composed of a memory cell array section which is a storage area that stores a large amount of stored information, and a peripheral circuit section necessary for input/output with the outside. FIG. 26 is a plan view showing a memory cell array section of a conventional DRAM. 27 and 28 are cross-sectional structural diagrams for explaining the manufacturing process of the cross-sectional section taken along line AA of the memory cell array section shown in FIG. 26.

First, the structure of a conventional memory cell array section will be described with reference to FIGS. 26 and 28.

The memory cell array section includes a LOCOS oxide film 2 for element isolation formed on a semiconductor substrate 1, and an L
An impurity region 3 formed at a predetermined interval in a region surrounded by an OCOS oxide film 2, a gate electrode 5 formed between the impurity regions 3 with a gate oxide film 4 interposed therebetween, and a side wall portion of the gate electrode 5. The sidewall 13 formed on the gate electrode 5, the silicon oxide film 12 formed on the gate electrode 5,
A storage node 6 is connected to the impurity region 3 located between the OS oxide film 2 and the gate electrode 5 and is formed to extend on the sidewall 13 and the silicon oxide film 12. An opening is formed on the cell plate 7 formed through a dielectric film (not shown) and the impurity region 3 formed on the entire surface of the semiconductor substrate 1 so as to cover the cell plate 7 and located between the gate electrodes 5. The bit line 11 is connected to the impurity region 3 in the opening of the interlayer film 10 and is formed to extend over the cell plate 7 .

Here, the cross-sectional structure shown in FIG.
When viewed in plan with reference to 6, bit lines 11 are arranged in the horizontal direction, and gate electrodes 5 serving as word lines are arranged in the vertical direction. A storage node 6 is formed to cover the two gate electrodes 5. Storage node 6 is connected to impurity region 3 through storage node contact portion 51 located in a region surrounded by two gate electrodes 5 . This storage node contact portion 51 is located in a field cutout portion 54 which is an active region where the LOCOS oxide film 2 is not formed. The semiconductor substrate 1 and the bit line 11 are connected to the bit line/substrate contact part 6
1 is connected to impurity region 3 . This bit line/substrate contact portion 61 is located in a cell plate cutout portion 62, which is a region where the cell plate 7 is not formed.

Next, the manufacturing process will be explained with reference to FIGS. 27 and 28. First, a LOCOS oxide film 2 for element isolation is formed on a semiconductor substrate 1. L.O.
A multilayer film consisting of an oxide film 4, a gate electrode 5, and a silicon oxide film 12 is formed in a region surrounded by the COS oxide film 2 at predetermined intervals. After forming an insulating film over the entire surface, a portion that will become the bit line/substrate contact portion 61 (see FIG. 26) is covered with a resist (not shown). By performing anisotropic etching, sidewalls 13 are formed at sidewall portions where gate electrodes 5 on LOCOS oxide film 2 and gate electrodes 5 formed in the active region face each other. Using the formed sidewall 13, storage node 6, which becomes the lower electrode of the capacitor, is formed so as to be connected to impurity region 3 in a self-aligned manner.

Next, as shown in FIG. 28, a cell plate 7 is formed on the storage node 6 with a thin dielectric film (not shown) interposed therebetween. An interlayer film 10 is formed on the entire surface of the cell plate 7.
A contact hole is formed in a portion where a bit line/substrate contact portion 61 (see FIG. 26) is to be formed. A bit line 11 is formed in a contact hole formed in interlayer film 10 so as to be connected to impurity region 3 .

In this way, conventionally, after forming the storage node 6 and cell plate 7 that serve as capacitors, the bit line 11 is formed, and then the bit line 11 is electrically connected directly onto the impurity region of the semiconductor substrate 1. It was formed to connect.

0010

As described above, in the memory cell array section of a conventional DRAM, the bit line 11 is formed after the storage node 6 and cell plate 7 constituting the capacitor are formed. The bit line 11 was formed in direct contact with the impurity region 3 of the semiconductor substrate 1.

However, as semiconductor devices become more integrated and the elements become finer, there is a problem in that a sufficient capacitor area cannot be obtained with such a conventional structure. That is, conventionally, contact holes for bit lines 11 are formed after storage nodes 6 and cell plates 7 are formed. Therefore, storage node 6
and bit line/substrate contact section 6 of cell plate 7
The end position on the first side is defined by the size of the contact hole for the bit line 11. In other words, the shapes of the storage node 6 and cell plate 7 that constitute the capacitor are defined by the contact hole for the bit line 11 that will be formed later, so that a sufficient capacitor area can be obtained when the device is miniaturized. I won't be able to do that.

Furthermore, since the bit line 11 is directly connected to the semiconductor substrate 1 at the bit line/substrate contact portion 61, the aspect ratio of the contact hole of the bit line 11 increases as the device becomes finer. There were also some inconveniences.

The present invention was made in order to solve the above-mentioned problems, and provides a semiconductor device and a method for manufacturing the same that can ensure a sufficient capacitor area even when elements are miniaturized. The purpose is to

[0014]

[Means for Solving the Problem] A semiconductor device according to claim 1 is formed such that the semiconductor device is electrically connected to an impurity region located between gate electrodes and extends over the gate electrode via a first insulating layer. between the conductive layer formed on the conductive layer, the second insulating layer formed on the conductive layer, the gate electrode, the sidewalls formed on the sidewalls of the conductive layer and the second insulating layer, the element isolation region, and the gate electrode. and an electrode layer that is electrically connected to the impurity region located on the sidewall and serves as a lower electrode of the capacitor formed on the sidewall and the second insulating layer.

A method for manufacturing a semiconductor device according to claim 2 includes the steps of: forming an active region and an isolation region by forming an isolation oxide film in a predetermined region on a semiconductor substrate; A step of forming a gate electrode wiring layer extending at a predetermined interval, and forming a signal transmission line layer and the signal transmission line layer at a predetermined interval so as to intersect with the gate electrode wiring layer and surround the active region. Insulating the sidewalls of the gate electrode wiring layer and the signal transmission line layer is performed by forming an upper insulating film on top, and then performing anisotropic etching after forming an insulating layer to cover the active region and isolation region. forming an opening over the active region surrounded by the gate electrode wiring layer and the signal transmission line by leaving a layer remaining; and forming a conductive layer on the insulating layer and in the opening so as to electrically connect with the active region. and a step of forming.

[0016]

In the semiconductor device according to the first aspect of the present invention, the conductive layer is connected to the impurity region located between the gate electrodes and is formed so as to extend over the gate electrodes via the first insulating layer. A second insulating layer is formed on the conductive layer. Sidewalls are formed on the sidewalls of the gate electrode, the conductive layer, and the second insulating layer. An electrode layer serving as a lower electrode of the capacitor is connected to the element isolation region and the impurity region located between the gate electrodes, and is formed on the sidewalls and the second insulating layer. As a result, the surface area of the capacitor can be increased with the same planar area as the conventional method by utilizing the step difference in the conductive layer.

In the method for manufacturing a semiconductor device according to claim 2, a gate electrode wiring layer is formed extending over the active region and the isolation region at a predetermined interval, and intersects with the gate electrode wiring layer and extends over the active region. A signal transmission line layer is formed at a predetermined distance to surround the signal transmission line layer, and an upper insulating film is further formed on the signal transmission line layer. After the insulating layer is formed to cover the active region and the isolation region, anisotropic etching is performed. By doing so, an insulating layer remains on the side walls of the gate electrode wiring layer and the signal transmission line layer, thereby forming an opening over the active region surrounded by the gate electrode wiring layer and the signal transmission line layer. Then, a conductive layer is formed within the insulating layer and the opening so as to be electrically connected to the active region. That is, by forming the signal transmission line layer to surround the active region, the opening in the insulating layer above the active region is formed in a self-aligned manner using anisotropic etching.

[0018]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 shows a DRAM according to an embodiment of the present invention.
FIG. 3 is a plan view of a memory cell array section of FIG. FIG. 2 is a cross-sectional structural diagram taken along line AA of the memory cell array section shown in FIG. FIG. 3 shows B of the memory cell array section shown in FIG.
-B is a cross-sectional structure diagram. The configuration of the memory cell array section of this embodiment will be described with reference to FIGS. 1 to 3.

First, referring to FIG. 2, A-A shown in FIG.
The cross-sectional structure of will be explained. The memory cell array section in this cross section includes a semiconductor substrate 1 and a semiconductor substrate 1.
A LOCOS oxide film 2 for element isolation formed above, an impurity region 3 formed at a predetermined interval in a region surrounded by the LOCOS oxide film 2, and an adjacent impurity region 3.
A gate electrode 5 formed through a gate oxide film 4 between
between the silicon oxide film 12 formed on the gate electrode 5, the sidewall 13 formed on the side wall portion of the gate electrode 5, and the gate electrode 5 formed in the area surrounded by the LOCOS oxide film 2. A polysilicon pad 8 connected to the located impurity region 3 and extending on the gate electrode 5 via the silicon oxide film 12, a silicon oxide film 9 formed on the polysilicon pad 8, and a polysilicon The sidewall 14 formed on the sidewall portion of the pad 8 and the silicon oxide film 9 is connected to the impurity region 3 located between the LOCOS oxide film 2 and the gate electrode 5.
It includes a storage node 6 formed to extend upward, a cell plate 7 formed on the storage node 6, and an interlayer film 10 formed on the cell plate 7.

Next, referring to FIG. 3, B- shown in FIG.
The cross-sectional structure at B will be explained. The memory cell array section in the cross section taken along line B-B includes the semiconductor substrate 1 and
LOCOS oxide film 2 formed on semiconductor substrate 1 and L
Gate electrodes 5 formed on the OCOS oxide film 2 at predetermined intervals, polysilicon pads 8 formed on the LOCOS oxide film 2 located between the gate electrodes 5, and polysilicon pads 8 formed on the polysilicon pads 8. The polysilicon pad 8 and the sidewall 14 formed on the sidewall portion of the silicon oxide film 9, and the area of the LOCOS oxide film 2 other than the area where the gate electrode 5 and the polysilicon pad 8 are formed. the cell plate 7, the interlayer film 10 formed on the cell plate 7, and the silicon oxide film 9.
, sidewalls 15 formed on sidewall portions of cell plate 7 and interlayer film 10, and bit lines 11 formed in regions surrounded by sidewalls 15 of polysilicon pads 8.

Next, referring to FIG. 1, the cross-sectional structure explained in FIGS. 2 and 3 will be observed in a plan view. That is, gate electrodes 5 are arranged at predetermined intervals in the vertical direction, and storage nodes 6 are formed to cover two adjacent gate electrodes 5. The storage node 6 and the semiconductor substrate 1 (see FIG. 2) are connected through a storage node contact portion 51. The storage node contact portion 51 is located in a field cutout portion 54 which is an active region where the LOCOS oxide film 2 (see FIG. 2) is not formed. Further, in this embodiment, a polysilicon pad 8 is provided between the bit line 11 (see FIG. 3) and the semiconductor substrate 1 (see FIG. 3). Connection between polysilicon pad 8 and semiconductor substrate 1 is made at pad/substrate contact portion 53 . Furthermore, connection between bit line 11 (see FIG. 3) and polysilicon pad 8 is made at bit line/pad contact portion 52.

In this way, in this embodiment, the bit line 11
A polysilicon pad 8 is interposed between the impurity region 3 and the impurity region 3. As a result, sidewalls 14 are formed using the steps of polysilicon pads 8. By using this sidewall 14, the surface area for the same planar area of the storage node 6, which serves as the lower electrode of the capacitor, can be increased compared to the conventional case. As a result, a sufficient capacitor area can be secured even when elements are miniaturized as semiconductor devices become more integrated. Further, by interposing the polysilicon pad 8 between the bit line 11 and the impurity region 3, the aspect ratio of the contact hole of the bit line 11 can be reduced.

FIGS. 4 to 8 are cross-sectional structural views for explaining one embodiment of the manufacturing process of the memory cell array section shown in FIG. 2. A manufacturing process for the memory cell array section shown in FIG. 2 will be described with reference to FIG. 1 and FIGS. 4 to 8.

First, as shown in FIG. 4, a LOCOS oxide film 2 for element isolation is formed on a semiconductor substrate 1. A silicon oxide film 4 that will become a gate oxide film, a polysilicon 5 that will become a gate electrode, and a silicon oxide film 12 are sequentially formed. A resist 21 is placed on the area where the gate electrode will eventually be formed.
form. Anisotropic etching is performed using reactive ion etching using the resist 21 as a mask. As a result, a gate oxide film 4 and a gate electrode 4 as shown in FIG.
And a silicon oxide film 12 is formed. Gate electrode 5
Then, a silicon oxide film 23 is formed on the entire surface so as to cover the silicon oxide film 12. A resist 22 is formed in a region where an opening 53 for a bit line contact is not formed. An opening 53 is formed by anisotropically etching the resist 22 by reactive ion etching. Thereafter, as shown in FIG. 6, polysilicon 8 and silicon oxide film 9 are sequentially formed. A resist 24 is formed in a predetermined region on the silicon oxide film 9. By performing anisotropic etching by reactive ion etching using the resist 24 as a mask, a polysilicon pad 8 having a desired shape as shown in FIG. 7 is formed above the opening 53. A silicon oxide film 25 is formed on the silicon oxide film 9 formed on the polysilicon pad 8 so as to cover the polysilicon pad 8 . Then, by etching the entire surface by reactive ion etching without using a mask, as shown in FIG.
4 is formed. The sidewall 14 is connected to the gate electrode 5
It is integrated with the sidewall 13 formed on the sidewall portion of the. A storage node contact 51 for connecting a storage node 6 to the semiconductor substrate 1, which will be described later, is formed in a self-aligned manner by the sidewalls 13 and 14. Finally, as shown in FIG.
4 and silicon oxide film 14. Storage node 6 is formed to extend over silicon oxide film 14. After forming the cell plate 7 on the storage node 6, the interlayer film 1 is formed on the cell plate 7.
form 0.

Although polysilicon is used as the gate electrode 5 and the polysilicon pad 8 in this embodiment, the present invention is not limited to this, and the present invention is not limited to this. Any of the following membranes may be used. Further, in this embodiment, the sidewalls 13 and 14 made of silicon oxide films were formed on the sidewalls of the gate electrode 5 and the polysilicon pad 8, but the present invention is not limited to this, and the present invention is not limited to this. The sidewall may be formed by Furthermore, in this embodiment, as element isolation, LOCOS
Although LOCOS isolation using an oxide film is used, the present invention is not limited to this, and field shield isolation using a plate electrode, trench isolation, or other isolation methods may be used.

FIG. 9 is a plan layout diagram showing a semiconductor device according to another embodiment of the present invention. FIG. 10 is a partially enlarged view of the semiconductor device shown in FIG. 9. Figure 11 is Figure 10
FIG. 2 is a cross-sectional view taken along line A-A of the semiconductor device shown in FIG. FIG. 12 is a cross-sectional view taken along line BB of the semiconductor device shown in FIG. FIG. 13 shows C of the semiconductor device shown in FIG.
-C is a sectional view.

The semiconductor device of this other embodiment is a semiconductor device using a so-called buried bit line in which a bit line is buried.

First, referring to FIGS. 9 and 10, an isolation region 102 (LOCOS oxide film) is formed in a predetermined region on a semiconductor substrate 101 (not shown) so as to surround a plurality of active regions.
is formed. Word lines (
A gate electrode) 104 is formed. word line 104
Bit lines 111 are formed at predetermined intervals so as to intersect with word line 104 and surround the active region together with word line 104 . The bit line 111 is connected to the bit line contact portion 11
0 and is electrically connected to the active region. A storage node 115 is formed on an active region surrounded by two adjacent word lines 104 and two bit lines 111. Storage node 115 is electrically connected to the active region at storage node contact portion 114 .

Next, with reference to FIG. 11, the cross-sectional structure of the semiconductor device shown in FIG. 10 taken along line AA will be described. The semiconductor device in this cross section includes a semiconductor substrate 101 and a LOCO formed in a predetermined area on the semiconductor substrate 101.
Impurity regions 106 and 108 are formed at a predetermined interval in a region surrounded by the S oxide film 102 and the LOCOS oxide film 102, and a gate is formed between the impurity regions 106 and 108 with a gate oxide film 103 interposed therebetween. The electrode 104, the upper oxide film 105 and sidewalls 107 formed to cover the gate electrode 104, and the upper oxide film 10
5 and sidewalls 107, and a gate electrode 104 in the active region.
Bit line 111 (buried bit line) formed to be electrically connected to impurity region 106 in between and bit line 1
A silicon oxide film 112 formed on the top of the silicon oxide film 11, a sidewall 113 formed on the sidewall portions of the silicon oxide film 109, the bit line 111, and the silicon oxide film 112.
and a storage node 115 forming a lower electrode of a capacitor formed in a region surrounded by sidewalls 113 so as to be electrically connected to impurity region 106 .

Next, referring to FIG. 12, the cross-sectional structure of the semiconductor device shown in FIG. 10 taken along line BB will be described. The semiconductor device in this B-B is a semiconductor substrate 101
and a LOCO formed in a predetermined region of the semiconductor substrate 101.
The impurity regions 106 and 108 formed between the S oxide film 102 and the adjacent LOCOS oxide film 102 and the LOCOS
Silicon oxide film 1 formed to cover oxide film 102
09, a bit line 111 formed in a predetermined area on the silicon oxide film 109, a silicon oxide film 112 formed on the bit line 111, and a side wall formed on the side wall portions of the bit line 111 and the silicon oxide film 112. wall 1
13, and a storage node 115 formed in a region surrounded by sidewalls 113 so as to be electrically connected to impurity regions 106 and 108 of semiconductor substrate 101.

Referring to FIGS. 10, 11 and 12,
Storage node contact portion 114 is defined by adjacent gate electrode 104 and adjacent bit line 115 formed to intersect gate electrode 104 and surround storage node contact portion 114 . In this way, the bit line 111 is connected to the storage node contact section 11.
By forming the storage node contact portion 114 in a shape that surrounds 4, the storage node contact portion 114 can be easily formed in a self-aligned manner as described later.

Next, with reference to FIG. 13, the cross-sectional structure of the semiconductor device shown in FIG. 10 taken along line CC will be described. The semiconductor device in this CC is a semiconductor substrate 101
and a LOC formed in a predetermined area on the semiconductor substrate 101.
OS oxide film 102 and adjacent LOCOS oxide film 102
The impurity regions 106 and 108 formed between the LOCO
The S oxide film 102 and the silicon oxide film 109 formed in a predetermined area on the surface of the semiconductor substrate 101 and the LOCOS
Impurity region 10 in the active region where oxide film 102 is not formed
6, 108, and the LOCOS oxide film 10
2, a silicon oxide film 112 formed on the bit line 111, and a sidewall 113 formed to fill in the space between the adjacent bit line 111 and silicon oxide film 112. It is equipped with As described above, in this embodiment, the distance between adjacent bit lines 111 is formed to be narrow in the CC cross section. This makes it possible to use the sidewalls 113 to fill in the spaces between adjacent bit lines 111, thereby achieving good flatness.

FIGS. 14 to 20 are similar to FIGS. 10 and 1.
A planar layout diagram (A) and a cross-sectional diagram along A-A (
B). Further, FIGS. 21 to 25 are cross-sectional views taken along line BB during the manufacturing process shown in FIGS. 16 to 20.

A manufacturing process for a semiconductor device according to another embodiment will be described with reference to FIGS. 14 to 20 and 21 to 25.

First, referring to FIG. 14, the semiconductor substrate 10
A LOCOS oxide film 102 is formed in a predetermined region on 1. As a result, an isolation region (a region where a LOCOS oxide film is formed) 102 and an active region are formed.

Next, as shown in FIG.
2 and a gate oxide film 1 at a predetermined interval in the active region.
03, a multilayer film consisting of a gate electrode 104 and an upper oxide film 105 (silicon oxide film) is formed. Upper oxide film 1
05 and the LOCOS oxide film 102 as a mask, the semiconductor substrate 1 is implanted at a relatively low concentration by ion implantation.
An impurity region 106 having a conductivity type opposite to that of 01 is formed.

Next, as shown in FIGS. 16 and 21,
A sidewall 107 made of a silicon oxide film is formed on the sidewall portion of the gate electrode 104. side wall 10
7 and LOCOS oxide film 102 as a mask, ion implantation is performed to form a relatively high concentration impurity region 108. As a result, source/drain regions constituting the transistor are formed.

Next, as shown in FIGS. 17 and 22,
After forming a silicon oxide film 109 on the entire surface of the semiconductor substrate 101 using the CVD method, an opening (bit line contact portion 110) is formed between adjacent gate electrodes 104 in the active region.

Next, as shown in FIGS. 18 and 23,
A bit line 11 made of a high melting point metal is arranged in the bit line contact portion 110 to be electrically connected to the impurity region 106.
1 and a silicon oxide film 112 is formed thereon. Here, the planar layout of the bit line 111 in this case is arranged so as to surround the region BB in FIG. 18A (the region where the storage node contact portion 114 will be formed in a later step). That is, as shown in FIG. 18A, the bit line 111 has a concave planar shape such that the distance between adjacent bit lines 111 is wider in the region B-B than in other regions. be done.

Next, as shown in FIGS. 19 and 24,
A silicon oxide film 113 is formed to cover the entire surface.

Next, as shown in FIGS. 20 and 25,
The entire surface of the silicon oxide film 113 is anisotropically etched by reactive ion etching. As a result, the silicon oxide film 109, the bit line 111 and the silicon oxide film 11
A sidewall 113 is formed at the sidewall portion of No. 2. By over-etching at the same time, storage node contact portions 114 are formed in a self-aligned manner. Finally, as shown in FIGS. 10, 11, and 12, storage node contact portion 114 is electrically connected to impurity region 106 and bit line
A storage node 115 is formed to extend above 1.

As described above, in this embodiment, the bit line 111 is arranged so as to surround the storage node contact portion 114.
By arranging the storage node contact portion 114, the bit line 114 and the word line (gate electrode) 1
04. By forming a sidewall 113 on the sidewall portion of the bit line 111, a storage node contact portion 114 is formed in a self-aligned manner. Furthermore, in the cross section taken along line C-C shown in FIG. The area between lines 111 can be filled. Thereby, a semiconductor device having good flatness can be easily obtained.

[0044]

According to the invention as set forth in claim 1, the conductive layer is formed so as to be connected to the impurity region located between the gate electrodes and to extend over the gate electrodes via the first insulating layer. . A second insulating layer is formed on the conductive layer, and sidewalls are formed on sidewall portions of the gate electrode, the conductive layer, and the second insulating layer. An electrode layer serving as a lower electrode of the capacitor is connected to the element isolation region and the impurity region located between the gate electrode, and is formed on the sidewall and the second insulating layer. As a result, the surface area of the capacitor can be increased using the step difference in the conductive layer with the same planar area as the conventional one, so that even when elements are miniaturized, a sufficient capacitor area can be secured.

According to the second aspect of the invention, the signal transmission line layer and the upper part of the signal transmission line layer are arranged at a predetermined interval so as to intersect with the gate electrode wiring layer and surround the active region. An insulating layer is formed to cover the active region and isolation region, and then anisotropic etching is performed to leave the insulating layer on the side walls of the gate electrode wiring layer and the signal transmission line layer. An opening is formed on the active region surrounded by the gate electrode wiring layer and the signal transmission line layer, and a conductive layer is formed on the insulating layer and in the opening so as to be electrically connected to the active region. As a result, an opening is easily formed over the active region defined by the gate electrode wiring layer and the signal transmission line layer. Furthermore, by narrowing the spacing between adjacent signal transmission line layers other than the area where the opening is formed, the area between the adjacent signal transmission line layers can be separated from the sidewall of the gate electrode wiring layer and the sidewall of the signal transmission line layer. It can be easily embedded using the insulating layer left behind. As a result, a semiconductor device having good flatness can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a memory cell array portion of a DRAM according to an embodiment of the present invention.

FIG. 2 is a cross-sectional structural diagram taken along line AA of the memory cell array section shown in FIG. 1;

FIG. 3 is a cross-sectional structural diagram taken along line BB of the memory cell array section shown in FIG. 1;

FIG. 4 is a cross-sectional structural diagram showing a first step in the manufacturing process of the memory cell array section shown in FIG. 2;

5 is a cross-sectional structural diagram for explaining a second step of the manufacturing process of the memory cell array section shown in FIG. 2; FIG.

6 is a cross-sectional structural diagram for explaining a third step of the manufacturing process of the memory cell array section shown in FIG. 2; FIG.

7 is a cross-sectional structural diagram for explaining a fourth step in the manufacturing process of the memory cell array section shown in FIG. 2; FIG.

8 is a cross-sectional structural diagram for explaining a fifth step of the manufacturing process of the memory cell array section shown in FIG. 2; FIG.

FIG. 9 is a plan layout diagram showing a semiconductor device according to another embodiment of the present invention.

FIG. 10 is a partially enlarged view of the semiconductor device shown in FIG. 9;

11 is a cross-sectional view taken along line AA of the semiconductor device shown in FIG. 10. FIG.

12 is a cross-sectional view taken along line BB of the semiconductor device shown in FIG. 10. FIG.

13 is a cross-sectional view taken along line CC of the semiconductor device shown in FIG. 10. FIG.

14A and 14B are plan layout diagrams (A) and A-A showing the first step of the manufacturing process of the semiconductor device shown in FIG. 10;
FIG.

15A and 15B are plan layout diagrams (A) and A-A showing the second step of the manufacturing process of the semiconductor device shown in FIG. 10;
FIG.

16A and 16B are plan layout diagrams (A) and A-A showing the third step of the manufacturing process of the semiconductor device shown in FIG. 10;
FIG.

17A and 17B are plan layout diagrams (A) and A-A showing the fourth step of the manufacturing process of the semiconductor device shown in FIG. 10;
FIG.

FIG. 18 is a plan layout diagram (A) and A-A showing the fifth step of the manufacturing process of the semiconductor device shown in FIG. 10;
FIG.

19A and 19B are plan layout diagrams (A) and A-A showing the sixth step of the manufacturing process of the semiconductor device shown in FIG. 10;
FIG.

FIG. 20 is a plan layout diagram (A) and A-A showing the seventh step of the manufacturing process of the semiconductor device shown in FIG. 10;
FIG.

FIG. 21 is a sectional view taken along line BB during the third manufacturing process shown in FIG. 16;

FIG. 22 is a sectional view taken along line BB during the fourth manufacturing process shown in FIG. 17;

23 is a cross-sectional view taken along line BB during the manufacturing process of the fifth step shown in FIG. 18. FIG.

24 is a cross-sectional view taken along line BB during the manufacturing process of the sixth step shown in FIG. 19. FIG.

25 is a sectional view taken along line BB during the manufacturing process of the seventh step shown in FIG. 20. FIG.

FIG. 26 is a plan view showing a memory cell array section of a conventional DRAM.

27] A-A of the memory cell array section shown in FIG. 26;
It is a cross-sectional structure diagram for explaining the first step of the manufacturing process of the cross-sectional part in FIG.

28] A-A of the memory cell array section shown in FIG. 26;
It is a cross-sectional structural diagram for explaining the second step of the manufacturing process of the cross-sectional part in FIG.

[Explanation of symbols]

1 Semiconductor substrate 2 LOCOS oxide film 5 Gate electrode 6 Storage node 7 Cell plate 8 Polysilicon pad 11 Bit lines 13, 14, 15 Sidewall 51 Storage node contact section 52 Bit line/pad contact section 53 Pad/substrate contact section 54 Field Cutout 61 Bit line/substrate contact 62 Cell plate cutout 102 Isolation region (LOCOS oxide film) 104 Word line (gate electrode) 110 Bit line contact 111 Bit line 114 Storage node contact 115 Storage node , the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] 1. A semiconductor device in which impurity regions are formed at predetermined intervals in a region surrounded by an element isolation region on a semiconductor substrate, and a gate electrode is formed between the impurity regions with a gate insulating film interposed therebetween. a conductive layer electrically connected to the impurity region located between the gate electrodes and extending over the gate electrode via a first insulating layer; and a conductive layer formed on the conductive layer. Electricity is applied to the impurity region located between the gate electrode, the conductive layer, and the sidewalls of the second insulating layer, the element isolation region, and the gate electrode. an electrode layer that is connected to the sidewall and serves as a lower electrode of a capacitor formed on the sidewall and the second insulating layer. 2. A plurality of gate electrode wiring layers and a plurality of signal transmission line layers are arranged to intersect on a semiconductor substrate,
A method of manufacturing a semiconductor device in which an opening is formed in an insulating layer provided on an active region located in a region surrounded by the gate electrode wiring layer and the signal transmission line layer, the method comprising: a step of forming an active region and an element isolation region by forming an element isolation oxide film in the region; a step of forming a gate electrode wiring layer so as to extend over the active region and the isolation region at a predetermined interval; , intersects the gate electrode wiring layer and surrounds the active region,
After forming a signal transmission line layer and an upper insulating film on the signal transmission line layer at predetermined intervals, and forming an insulating layer to cover the active region and isolation region, anisotropic etching is performed. By doing so, by leaving the insulating layer on the sidewalls of the gate electrode wiring layer and the signal transmission line layer, an opening is formed on the active region surrounded by the gate electrode wiring layer and the signal transmission line layer. and forming a conductive layer on the insulating layer and in the opening so as to be electrically connected to the active region.