JPH04225393A - Automatic changeover circuit for polarity of synchronizing signal of monitor device - Google Patents

Abstract

PURPOSE:To decrease an operator's burden by providing a deciding circuit which automatically decides the polarity of the synchronizing signal inputted from an external device. CONSTITUTION:The output signal e of a 1st averaging circuit 16a is always smaller than the output signal f of a 2nd averaging circuit 16b over the entire period of one period. Consequently, a comparator circuit 21 continuously transmits the polarity decision signal g of a low level to a polarity changeover circuit 22 and a changeover switch 22a is connected to a terminal a side. Then, the synchronizing signal a of the negative polarity inputted from the external device is inverted in signal level by an inverter 22b and is converted to the synchronizing signal h of the negative polarity. This signal is outputted from an output terminal 23. Even if the synchronizing signal a inputted to the monitor device in such a manner is either of the positive polarity or the negative polarity, the polarity is automatically matched with the polarity of the synchronizing signal to be used in the monitor device.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a monitor device that displays an image on a display screen by receiving an image signal and horizontal and vertical synchronization signals from an external device such as a computer.
In particular, the present invention relates to an automatic synchronization signal polarity conversion circuit for a monitor device that automatically matches the polarity of each synchronization signal input from an external device to the polarity of a synchronization signal used within the own device.

0002

2. Description of the Related Art In general, as shown in FIG. 6, a monitor device 1 incorporated in an information processing system is, for example, a host computer or engineering workstation
It is connected to a main body device 2 such as EWS) via a connection terminal 3, a connection socket 4, and a signal cable 5. This monitor device 1 houses, for example, a CRT display tube 6, a horizontal deflection circuit, a vertical deflection circuit, an image output circuit, and the like. Then, an image signal, a horizontal synchronization signal, and a vertical synchronization signal are sent from the main device 2 to the monitor device 1. The monitor device 1 drives a horizontal deflection circuit and a vertical deflection circuit with the inputted horizontal synchronization signal and vertical synchronization signal, and displays an image corresponding to the inputted image signal on the CRT display tube 6.

By the way, the horizontal and vertical synchronization signals sent from the main device 2 are processed by the device as shown in FIGS. 7(a) and 7(b).
As shown in the figure, there are two types each, and there are four types in combination. FIG. 7(a) shows a negative polarity synchronization signal in which the pulse indicating the synchronization timing is lower in signal level than at other positions.
FIG. 7B shows a positive-polarity synchronization signal in which the pulse indicating the synchronization timing is higher in signal level than at other positions. Therefore, the horizontal deflection circuit and the vertical deflection circuit incorporated in the monitor device 1 should be configured to operate normally with each polarity synchronization signal output from the main device 2.

However, if the manufacturer of the main device 2 and the manufacturer of the monitor device 1 are different, the polarity of each synchronization signal output from the main device 2 and the polarity used in each deflection circuit built into the monitor device 1 may differ. The polarity of the synchronization signal may not match.

Conventionally, in order to eliminate such inconveniences, an inverting circuit for inverting the polarity of the synchronizing signal outputted before the connection terminal 3 of the main unit 2 is incorporated, and the polarity of the synchronizing signal outputted by, for example, the operation of a dip switch is incorporated. The polarity of the synchronization signal can be selected, or an inverting circuit for inverting the polarity of the input synchronization signal can be built into the monitor device 1, so that each input synchronization signal can be changed by operating a changeover switch. A method of matching the polarity used in each deflection circuit has been put into practical use.

[0006]

However, as described above, it is quite complicated for the operator to switch the polarity on the main body device 2 side and the monitor device 1 side. In particular, when it becomes necessary to monitor the status of multiple main units 2 by switching connections with one monitor unit 1 as necessary,
It is necessary to perform a polarity switching operation each time. Particularly, when the switching operation is performed on the main device 2 side, the dip switch is generally arranged inside the device, and it is difficult to easily set the switching from the outside.

[0007] Furthermore, if only one of the main device 2 and the monitor device 1 has a polarity switching function and the fixed polarity of the other is unknown, check the polarity of the other side and then set the correct polarity. Must be set. Therefore, the burden on the operator increases.

The present invention has been made in view of the above circumstances, and by providing a circuit that automatically determines the polarity of a synchronization signal input from an external device, the synchronization signal output from the external device can be No matter which polarity the monitor device has, it can automatically match the polarity of the synchronization signal used within the device itself, eliminating conventional switching operations and greatly reducing the burden on the operator. The purpose of this invention is to provide an automatic signal polarity conversion circuit.

[0009]

[Means for Solving the Problems] In order to solve the above problems, in the synchronization signal polarity automatic conversion circuit of the monitor device of the present invention, the average current value of the signal level of each synchronization signal input from an external device is used as a reference. An input buffer circuit to set the level, and a synchronization signal output from this input buffer circuit, a signal level higher than the reference level is set to high level,
A first binarization circuit that binarizes a signal level lower than the reference level as a low level, and a synchronization signal output from the input buffer circuit, sets a signal level lower than the reference level as a high level and converts the synchronization signal into a signal higher than the reference level. a second binarization circuit that binarizes the level as a low level; a first averaging circuit that obtains a signal level proportional to the average signal level of the output signal of the first binarization circuit; A second averaging circuit that obtains a signal level proportional to the average signal level of the output signal of the binarization circuit, and a comparison that compares the magnitude of each signal level obtained by the first and second averaging circuits. circuit and
The apparatus includes a polarity conversion circuit that converts the polarity of each input synchronization signal into the polarity of a synchronization signal used within the monitor device in accordance with the output signal of the comparison circuit.

0010

[Operation] With the synchronization signal polarity automatic conversion circuit of the monitor device configured as described above, each input synchronization signal is set to the average current value of the signal level by the input buffer circuit as the reference level. That is, in each of the horizontal and vertical synchronization signals, the pulse width of the pulse indicating the synchronization timing is much smaller than the time width at other positions. Therefore, the duty ratio, which is the ratio of the high level period to one cycle of the negative polarity synchronization signal shown in FIG. 7(a), has a very high value exceeding 0.9. On the other hand, the duty ratio of the positive polarity synchronization signal shown in FIG. 7(b) is a very small value of less than 0.1. Therefore, the reference level of the negative polarity synchronization signal is near the top of the signal waveform,
The reference level of the positive polarity synchronization signal is near the lower end of the signal waveform.

Therefore, if the input synchronization signal has positive polarity, the first and second binarization circuits output binarized signals having different signal levels. Therefore, when the signal level of each binarized signal is averaged, the average level differs greatly between positive polarity and negative polarity. By comparing these signal levels, it is possible to reliably determine the polarity of the input synchronization signal. Based on this determination result, it becomes possible to automatically match the polarity of the input synchronization signal with the polarity of the synchronization signal used internally.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an automatic synchronization signal polarity conversion circuit built into a monitor device. Note that the actual monitor device incorporates two circuits shown in FIG. 1, each of which automatically switches the polarity of a horizontal synchronizing signal and a vertical synchronizing signal. It is assumed that each deflection circuit of this monitor device operates with a synchronization signal of negative polarity.

Horizontal and vertical synchronizing signals a outputted from a host computer as an external device are inputted to the (+) side input terminal of the first buffer amplifier 12 via the input terminal 11. The (-) side input terminal of this first buffer amplifier 12 is grounded. This first buffer amplifier 1
2 is an amplifier with a voltage gain of 1 that converts input impedance to low impedance. The synchronizing signal a output from the first buffer amplifier 12 is input to the (+) side input terminal of the second buffer amplifier 14 via a filter 13 consisting of a capacitor 13a and a resistor 13b whose one end is grounded. This second buffer amplifier 14 is an amplifier with a voltage gain of 1 whose (-) side input terminal is grounded. Filter 13 and second buffer amplifier 14 constitute an input buffer circuit.

The synchronizing signal b output from this input buffer circuit is input to the (+) side input terminal of the first binarization circuit 15a, and is also input to the (-) side input terminal of the second binarization circuit 15b. input to the terminal. (− of the first binarization circuit 15a)
) side input terminal and the (+) side input terminal of the second binarization circuit 15b are commonly grounded. First and second binarization circuits 15a. 15b has the same configuration, and outputs a high level signal of, for example, 5V from the output terminal when the input signal level of the (+) side input terminal is higher than the signal level of the (-) side input terminal. Conversely, when the input signal level of the (+) side input terminal is lower than the signal level of the (-) side input terminal, a low level signal such as 0V, for example, is output from the output terminal.

The output signal c of the first binarization circuit 15a is input to the first averaging circuit 16a. As shown in the figure, this first averaging circuit 16a includes two resistors 17a, 1
8a, a diode 19a for preventing backflow inserted between the resistors 17a and 18a, and a capacitor 20a connected in parallel to the resistor 18a. A resistor 18a and a capacitor 2 each have one side grounded.
The terminal voltage of 0a is output as the output signal e of the comparator circuit 21 (+
) side input terminal. In addition, the ground side resistor 18a
The resistance value is set to a considerably larger value than the resistance value of the input side resistor 17a.

The first averaging circuit 16a having such a configuration
Since the charging circuit is constituted by the resistor 17a and the capacitor 29a, it functions as a kind of low-pass filter. Therefore, a signal e having a signal level corresponding to the average signal level of the input signal c whose signal level changes periodically is output.

The output signal d of the second binarization circuit 15b is input to the second averaging circuit 16b. This second averaging circuit 16b has the same configuration as the first averaging circuit 16a described above, and includes two resistors 17b and 18b, a diode 19b, and a capacitor 20b. Then, a signal f having a signal level corresponding to the average signal level of the output signal d of the second binarization circuit 15b is sent to the (-) side input terminal of the comparison circuit 21.

The comparison circuit 21 compares the magnitude of each output signal e and f and outputs a polarity determination signal g. That is, when the signal level of the output signal e is higher than the signal level of the output signal f, the polarity determination signal g becomes high level, indicating that the input synchronization signal a has negative polarity. Conversely, the output signal e
When the signal level of the output signal f is lower than the signal level of the output signal f, the polarity determination signal g becomes low level, indicating that the input synchronization signal a is of positive polarity.

The polarity determination signal g output from the comparison circuit 21 is input to the polarity conversion circuit 22 as a switching control signal for the changeover switch 22a of the polarity conversion circuit 22. That is, when the polarity determination signal g is at a high level, the changeover switch 22a is connected to the terminal b side, and when the polarity determination signal g is at a low level, the changeover switch 22a is connected to the terminal a side. The synchronizing signal a outputted from the first buffer amplifier 12 is input to the filter 13 and also to this polarity conversion circuit 22, and is then input to the inverter 22.
The signal is input to one terminal a of the changeover switch 22a via terminal b. In addition, the synchronization signal a remains unchanged at the changeover switch 22a.
is input to the other terminal b. And selector switch 2
The synchronizing signal h is transmitted from the common terminal c of 2a through the output terminal 23.
is output.

The operation of the synchronizing signal polarity automatic conversion circuit configured as described above will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows a case where a synchronization signal a of negative polarity is input. The average signal level of the negative polarity synchronization signal a is located near the upper end of the waveform as shown. Therefore, the reference level indicated by 0V of the output signal b of the input buffer circuit composed of the filter 13 and the second buffer amplifier is located near the upper end of the waveform. the result,
The output signal c of the first binarization circuit 15a has a signal level of 5V except for the pulse position indicating the synchronization timing, and the output signal d of the second binarization circuit 15b has a signal level of 5V except for the pulse position indicating the synchronization timing. The signal level becomes 0V.

The output signal e of the first averaging circuit 16a is 1
This results in a continuous signal level close to 5V over the entire period of the cycle. Conversely, the output signal f of the second averaging circuit 16b is 1
This results in a continuous signal level close to 0V over the entire period of the cycle. Therefore, over the entire period of one cycle, the output signal e of the first averaging circuit 16a is always the same as that of the second averaging circuit 16.
It becomes larger than the output signal f of b. As a result, comparison circuit 2
1 continuously sends a high-level polarity determination signal g to the polarity conversion circuit 22. Therefore, the changeover switch 22a is connected to the terminal b side. Therefore, the negative polarity synchronization signal a input from the external device is outputted as is via the output terminal 23.

On the other hand, the operation of each section when a positive polarity synchronization signal a is input will be explained using the time chart shown in FIG. The average signal level of the positive polarity synchronization signal a is located near the lower end of the waveform as shown. Therefore, the reference level indicated by 0V of the output signal b of the input buffer circuit is located near the lower end of the waveform. As a result, the output signal c of the first binarization circuit 15a has a signal level of 0V except for the pulse position indicating the synchronization timing, and the second
The output signal d of the binarization circuit 15b has a signal level of 5V except at the pulse position indicating the synchronization timing. Therefore, over the entire period of one cycle, the first averaging circuit 1 is always
The output signal e of the second averaging circuit 16a becomes smaller than the output signal f of the second averaging circuit 16b.

As a result, the comparison circuit 21 continues to send the low level polarity determination signal g to the polarity conversion circuit 22. Therefore, the changeover switch 22a is connected to the terminal a side. Therefore, the negative polarity synchronization signal a input from the external device
The signal level is inverted by the inverter 22b, converted into a negative polarity synchronization signal h, and output from the output terminal 23.

In this way, regardless of whether the polarity of the synchronization signal a input to the monitor device is positive or negative, the polarity of the synchronization signal used inside the monitor device is automatically changed. is matched to Therefore, the operator does not need to check the polarities of the synchronization signals of the main device and the monitor device and perform a switching operation to match the polarities of both synchronization signals. As a result, the efficiency of connecting the monitor device to the main device can be greatly improved. Furthermore, synchronization signals having different polarities will not be connected by mistake.

Furthermore, by providing an input buffer circuit consisting of the filter 13 and the second buffer amplifier 14, the overall signal level (amplitude) including the height of the pulse indicating the synchronization timing in the input synchronization signal a is Even if the value is small, the average level of the synchronizing signal a can be reliably set to a reference level such as 0V.

Note that if the synchronization signal used inside the monitor device is of positive polarity, the selector switch 22a may be set to be switched to the terminal a side by the high-level polarity determination signal g.

FIG. 4 is a block diagram showing a schematic configuration of a synchronizing signal polarity automatic conversion circuit of a monitor device according to another embodiment of the present invention. The same parts as in FIG. 1 are given the same reference numerals. Therefore, detailed explanation of the overlapping parts will be omitted.

In this embodiment circuit, the first averaging circuit 25a which obtains a signal level proportional to the average signal level of the output signal c of the first binarizing circuit 15a is combined with the sawtooth wave generating circuit 26a. Hold (S/H) circuit 27
It consists of a. Note that the second averaging circuit 25b that obtains a signal level proportional to the average signal level of the output signal d of the second binarization circuit 15b is also the same as the first averaging circuit 25.
It is composed of a sawtooth wave generation circuit 26b and a sample hold (S/H) circuit 27b, which have the same configuration as that of a.

As long as a high level signal is applied to the reset terminal R, the sawtooth wave generating circuit 26a outputs a signal whose signal level increases continuously over time to the output terminal Q.
Output from. Then, when the signal level of the reset terminal R changes to low level, the signal level of the output signal is changed to 0V.
to control. Therefore, this sawtooth wave generating circuit 26a
As shown in FIG. 5, the output signal c has a sawtooth waveform that continuously increases up to approximately 5 V from the falling time of the pulse indicating the synchronization timing in one cycle to the falling time of the pulse of the next synchronization timing. outputs a signal i having

Further, the sample hold circuit 27a
In response to the fall timing of the output signal c of the binarization circuit 15a from high level to low level, the signal level of the output signal i of the sawtooth wave generation circuit 26a is held and held until the next fall timing. do. Therefore, an output signal k having a constant signal level of about 5V is sent from this sample and hold circuit 27a to the next comparison circuit 21.

The second binarization circuit 15b is input to the sawtooth wave generation circuit 26b constituting the second averaging circuit 25b.
As shown in FIG. 5, the output signal d of is at a high level only during the duration of the pulse indicating the synchronization timing. Therefore, an output signal j having a sawtooth waveform is obtained only during this short high level period. Therefore, although the maximum signal level of this output signal j depends on the duty ratio of the input synchronizing signal, it is usually 10% or less, so it is approximately 0.5V. The sample hold circuit 27b responds to the falling timing of the output signal c of the second binarization circuit 15b from a high level to a low level, and generates a sawtooth wave generating circuit 26b.
The signal level of the output signal j is held until the next falling timing. Therefore, an output signal m having a constant signal level of about 0.5V is sent from the sample and hold circuit 27b to the next comparison circuit 21.

Output signal k from the first averaging circuit 25a
Since the signal level of the second averaging circuit 25b never becomes lower than the signal level of the output signal m from the second averaging circuit 25b, the comparing circuit 2
The polarity determination signal g from 1 to high level is output to the polarity conversion circuit 22.
sent to.

Therefore, the negative polarity synchronization signal a inputted from the external device is outputted via the output terminal 23 as is.

Further, when a positive polarity synchronization signal a is input from an external device, a low level polarity determination signal g is sent from the comparison circuit 21 to the polarity conversion circuit 22. As a result, the negative polarity synchronization signal a inputted from the external device has its polarity converted and is outputted from the output terminal as a negative polarity synchronization signal h. Therefore, it is possible to obtain substantially the same effect as the embodiment shown in FIG.

Note that the present invention is not limited to the embodiments described above. In the embodiment, a case where the application is applied to a monitor device incorporating a CRT display tube has been described. The monitor device may include a liquid crystal display incorporating an interface circuit that converts each synchronization signal into a control signal indicating the display position of data to be displayed on the liquid crystal display.

[0038]

As described above, the synchronization signal polarity automatic conversion circuit of the present invention is provided with a determination circuit that automatically determines the polarity of a synchronization signal input from an external device. Therefore, no matter which polarity the synchronization signal output from the external device has, it can automatically match the polarity of the synchronization signal used within the own device, eliminating the conventional switching operation and allowing the operator to can significantly reduce the burden on

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a schematic configuration of a synchronization signal polarity automatic conversion circuit of a monitor device according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the same embodiment circuit.

FIG. 3 is a time chart showing the operation of the same embodiment circuit.

FIG. 4 is a circuit diagram showing a schematic configuration of a synchronization signal polarity automatic conversion circuit of a monitor device according to another embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the same embodiment circuit.

FIG. 6 is a diagram showing a connection relationship between a general main body device and a monitor device.

FIG. 7 is a signal waveform diagram showing types of general synchronization signals.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Monitor device, 12... First buffer amplifier, 13...
Filter, 14...second buffer amplifier, 15a...first
Binarization circuit, 15b...Second binarization circuit, 16a, 2
5a...first averaging circuit, 16b, 25b...second averaging circuit, 21...comparison circuit, 22...polarity conversion circuit.

Claims (1)

[Claims] 1. A synchronization signal polarity automatic conversion circuit for a monitor device that displays an image by receiving an image signal and vertical and horizontal synchronization signals from an external device, the circuit comprising: a signal level of a synchronization signal input from the external device; an input buffer circuit (13, 14) that sets the average current value of the reference level to a reference level; and a synchronization signal outputted from the input buffer circuit, a signal level higher than the reference level is set as a high level, and a signal level lower than the reference level is set as a high level; A first binarization circuit (15a) that binarizes the level with a low level, and a synchronization signal outputted from the input buffer circuit, with a signal level lower than the reference level as a high level, and a signal level higher than the reference level. A second digitizer that binarizes the signal level as a low level.
a digitization circuit (15b); a first averaging circuit (16a, 25a) for obtaining a signal level proportional to the average signal level of the output signal of the first binarization circuit;
A second averaging circuit (16b, 25b) that obtains a signal level proportional to the average signal level of the output signal of the value converting circuit, and the magnitude of each signal level obtained by the first and second averaging circuits. and a polarity conversion circuit (22) that converts the polarity of each of the input synchronization signals into the polarity of the synchronization signal used in the monitor device according to the output signal of the comparison circuit. Automatic synchronization signal polarity conversion circuit for monitor equipment.