JPH04223784A - Method and device for processing movement adaptive type signal - Google Patents

Abstract

PURPOSE:To facilitate integration by band-restricting a signal from a signal processing part constituted by means of two phases in a filter, adding the signal of two phases, executing equivalent 1/2-thinning and detecting movement from the added signal. CONSTITUTION:The outputs of the filters 31 and 32 and the outputs of the filters 33 and 34 are respectively added in adders 35 and 36. Then, the synthesized signal f1S of 'post-field' and the synthesized signal f-1S is of 'pre-field' can be obtained. Since the signals f1S and f-1S have a time difference for one frame and therefore an intra-one frame difference signal is obtained if a difference between both signals is obtained in a subtracter 37. A movement detection circuit 38 detects the movement of a picture based on the intra-one frame difference signal and the signal f1S. A movement signal being the output of the circuit 38 is distributed and is inputted to a movement adaptive n type time spatial filter 13 so as to control a signal processing. A movement detection part 7 operates by all the clocks of 20MHz and therefore detection can be realized in TTL and MOS.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to motion adaptive signal processing of digital image signals, and in particular, it is possible to configure all circuits of a processing device with circuits with half the clock frequency without deteriorating performance. The present invention relates to a method and a device that facilitate miniaturization and/or integration of a device.

0002

[Background Art] In recent years, in order to improve the signal processing performance of image signals, motion adaptive signal processing that changes the processing method between still image parts and moving image parts of image signals has been used in devices for various purposes. has been done. At this time, high-definition (HD)
In signal processing devices that handle wideband image signals such as TVs, the signal clock frequency is extremely high, several tens of MHz.
stor logic), MOS (Metal ox
ECL (
The device was realized using high-speed logic elements such as emitter-coupled logic.

0003]

[Problems to be Solved by the Invention] However, high-speed logic elements such as ECL are expensive, consume large amounts of power, and have low integration density, resulting in expensive and large signal processing devices. was. In normal signal processing devices, in such cases, the circuit is configured with two phases, the clock frequency is lowered, and TTL, MOS, etc. are used in order to make the device smaller and cheaper.However, motion adaptive signal processing devices In this case, in addition to the signal processing unit itself, the motion detection unit that detects the movement of the image signal must be made into two phases, which makes the signal exchange between blocks complicated, or the effect of miniaturization and cost reduction is small, or If only the motion detection section is reduced to one phase by simple thinning, there is a problem in that the accuracy of motion detection decreases due to aliasing distortion.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and to perform motion-adaptive signal processing of a digital image signal with a high clock frequency by reducing the signal processing section, including the motion detection section, at half the clock frequency. It is an object of the present invention to provide a motion adaptive signal processing method and device that is composed of operating two-phase circuits, has simple signal exchange between blocks, and can be easily miniaturized and integrated.

[0005]

[Means for Solving the Problem] In order to achieve this object, the motion adaptive signal processing method according to the present invention provides a two-phase signal obtained by sampling an input digital image signal at a clock frequency that is half the clock frequency of the input digital image signal. and the decomposed 2
Each of the phase signals is subjected to motion-adaptive signal processing by two motion-adaptive signal processing units, and the signal related to one of the two-phase signals extracted from the two processing units is converted to the original signal. A signal related to the other of the two-phase signals is supplied to a filter having an odd-numbered impulse response of a filter impulse response designed in the clock frequency domain, and a signal having an even-numbered impulse response of the impulse response of the filter. detecting the motion of the input image signal from a signal obtained by adding the output signals of the two filters, and controlling the motion adaptive signal processing of the two motion adaptive signal processing units using the detected signal;
The present invention is characterized in that the outputs of the two motion adaptive signal processing sections are combined to obtain a final output signal.

The motion adaptive signal processing device according to the present invention is a device for motion adaptive signal processing of an input digital image signal, in which the device processes the input digital image signal at a clock frequency that is half the clock frequency of the input digital image signal. A serial-to-parallel converter for decomposing the sampled two-phase signals, two motion-adaptive signal processing units for motion-adaptive signal processing of each of the decomposed two-phase signals, and two motion-adaptive signal processing units for motion-adaptive signal processing of each of the decomposed two-phase signals. comprising a motion detection section that supplies a motion detection signal for controlling motion adaptive signal processing of the motion adaptive signal processing section, and a parallel-to-serial converter that combines the outputs of the two motion adaptive signal processing sections; The motion detection section converts a signal related to one of the two-phase signals extracted from the two motion adaptive signal processing sections into an odd-numbered impulse response of a filter designed in the original clock frequency domain. The filter is characterized by comprising a filter that causes an impulse response, and a filter that causes a signal related to the other of the two-phase signals to respond to an even-numbered impulse response of the impulse response of the filter.

[0007]

[Operation] According to the method and apparatus of the present invention, the main body of the motion adaptive signal processing unit is composed of two-phase circuits that operate at a clock frequency that is half the original clock frequency, and the signal obtained from each of the two-phase circuits is After limiting the band using a filter consisting of two phases, the output signals of these two phases are added together to perform equivalent 1/2 thinning processing, and the motion of the image is detected from the added signal. Since the motion adaptive signal processing of the two-phase signal processing circuit is controlled based on the received signal,
The signal clock frequency of all components of the device is reduced by half, and the exchange of signals between blocks is also simplified, thereby achieving the object of the present invention.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of examples with reference to the accompanying drawings.

FIG. 1 shows a configuration diagram of an apparatus according to an embodiment of the present invention. In this embodiment, from a high-definition (HDTV) signal with 1125 scanning lines to a current broadcast (N) signal with 525 scanning lines.
It also has a system conversion function (scanning line number conversion) to signals used in the TSC standard system. First, Figure 2
An overview of this conversion function is explained below.

FIG. 2 shows the state of image conversion. Figure 2
The high-definition image in (a) has 1125 scanning lines and is a horizontally long image with an aspect ratio of 9:16. In contrast, the current broadcasting system NTSC
The image used in the standard method has 525 scanning lines, as shown in Figure 2(b), and the aspect ratio is 3:4.
It is. Therefore, in order to convert a high-definition image into an image that can be used for current broadcasting, one method is to thin out the scanning lines from 1125 to 525, and to make the aspect ratio the same, the shaded area in Figure 2(a) is Just cut it off. However, if the scanning lines are simply thinned out, aliasing distortion occurs in the vertical direction and the image quality deteriorates, so before thinning out, the band is usually limited using a pre-filter for the vertical spatial frequency before thinning out. At this time, if a higher quality converted image is desired, a motion adaptive spatiotemporal filter is generally used as a pre-filter that changes the method of band limiting between the still image portion and the moving image portion of the image signal.

[0011] This spatio-temporal filter is a filter for high-definition signals before conversion, and the clock frequency of the circuit inevitably becomes high. An example would be the following values. Generally, in the NTSC standard system, a digital signal with a clock frequency of about 14.3 MHz is used to facilitate the production of carrier color signals. Therefore, if the clock frequency of the output signal of the device configured in Figure 1 is set to 14.3 MHz, the clock frequency of most of the circuits including the input signal and the spatio-temporal filter will be 14.3 MHz.

0012

A frequency of approximately 40 MHz is required, such that: At this frequency of 40 MHz, TTL and MOS
It is extremely difficult to realize high-speed signal processing circuits such as spatio-temporal filters and motion detection circuits using economical and highly integrated elements such as the above.

Next, an embodiment according to the present invention having the configuration shown in FIG. 1 will be described. The illustrated configuration is broadly divided into an A/D converter 1, a serial/parallel (s→p) converter 2, a signal processing section A3, a signal processing section B4, and a parallel/serial (s→p) converter 2.
→s) It consists of seven elements: a converter 5, a D/A converter 6, and a motion detection section 7 (see also FIG. 3).

A high-definition signal with 1125 scanning lines and an aspect ratio of 9:16 is digitized by the A/D converter 1 with a 40 MHz clock, and is converted into a two-phase 20 MHz clock signal in the serial/parallel converter 2. Decomposed. At this time, it is assumed that each sample is decomposed into two phases, such that, for example, the odd-numbered sample signal of the 40 MHz clock is on one side, and the even-numbered signal is on the other side. The signal processing units A, B, 3, and 4 each perform signal processing on the two decomposed signals, and generate the scanning line 52.
It is converted into a signal with 5 lines and an aspect ratio of 3:4. The two converted signals are processed in the parallel/serial converter 5 in the opposite way to that in the serial/parallel converter 2, and are combined into one signal. The combined signal is D/A
The signal is D/A converted by the converter 6 and becomes an output signal of the device. In the signal processing unit A3, a field memory (fM) 1
1 and 12, and delay the input signal at f1A, f0A,
A signal of three consecutive fields of f −1A is obtained. Generally, f0A is treated as a signal in the same field as the output signal (current field signal). These signals are input to a motion adaptive spatio-temporal filter 13. Filter 13
outputs a band-limited signal in terms of spatio-temporal frequency according to the motion signal from the motion detection section 7. The processing method and circuit of this motion adaptive spatio-temporal filter 13 are already known. The output of filter 13 is still 1125 scanning lines,
Although the signal has an aspect ratio of 9:16, scanning line thinning and aspect ratio conversion are performed in the buffer memory 14 by appropriately controlling writing to or reading from the memory. As a result, a signal with 525 scanning lines and an aspect ratio of 3:4 is outputted from the memory 14, that is, the signal processing section A3.

The circuits of the above elements 11 to 14 are connected to the memory 1.
The readout side circuit of 4 is 1/2 of 14.3 MHz.
．． All 20 M except operate at 15 MHz
It operates with a clock frequency of Hz. At 20 MHz, it is easy to realize an advanced signal processing circuit using elements such as TTL and MOS. Element 2 in signal processing section B4
The contents and operations of elements 1 to 24 are exactly the same as those of elements 11 to 14. The motion detection section 7 receives four signals f1A, obtained from the signal processing section A3 and the signal processing section B4.
Image motion is detected from f1B, f-1A, and f-1B. These four signals are each filtered by LPF
(Low pass filter) A31, LPFB32, LPFA
33, is input to LPFB34. These filters 31
The operations in steps 34 to 34 will be described later.

The outputs of the filters 31 and 32 and the outputs of the filters 33 and 34 are added by adders 35 and 36, respectively, and the synthesized "later field" signal f1S and the synthesized "previous field" signal f- 1S is obtained. Since the signals f1S and f-1S have a time difference of one frame, by calculating the difference between the two using the subtracter 37, a one-frame difference signal can be obtained. The motion detection circuit 38 performs image motion detection based on this one-frame difference signal and the signal f1S. The processing method and circuit of the motion detection circuit 38 are known. The motion signal output from the detection circuit 38 is distributed and input to the motion adaptive spatio-temporal filter 13 to control signal processing. The motion detecting section 7 consisting of the above elements 31 to 38 all operates with a 20 MHz clock, so they can all be implemented using TTL, MOS, or the like.

Next, the characteristics of the filters 31 to 34 will be explained with reference to FIG. 4 showing an example of the impulse response of the filters. First, the left side of FIG. 4 shows the impulse response of a 7-tap (seventh-order) digital filter (original filter) designed in the clock frequency region of 40 MHz. hn indicates the coefficient value of the tap at each time point. This original filter
By decomposing hn into odd and even numbers with respect to n, the responses of filters A and B on the right side of the figure are obtained. This 2
f1A, which is a two-phase signal for each filter,
If applied to f1B or signals f-1A, f-1B, the band-limiting filter in the 40 MHz region becomes 2
This was achieved using a two-phase circuit with a 0 MHz clock. Therefore, the coefficients of filter A in FIG. 4 may be assigned to the LPFAs 31 and 33 in FIG. 1, and the coefficients of filter B may be assigned to the LPFBs 32 and 34. At this time, in the serial-parallel converter 2 of Fig. 1, the signal on the B side is 25n higher than the signal on the A side.
If it is designed to be delayed by s, it is sufficient to make the processing times of the coefficients h0 and h-1 the same as shown in FIG. (In the opposite case, align coefficients h0 and h1)
.

Filters 31 to 34 can be realized, for example, by the circuit shown in FIG. The input signal of the filter is, for example, an 8-bit digital signal. Elements 41, 42, and 43 are each 8-bit D registers, elements 44 to 47 are coefficient units, and element 48 is an adder. Since the operations of these elements 41 to 48 are well known, their explanations will be omitted. However, in the LPFAs 31 and 33, the coefficient α is assigned h-2 to α1, h0 to α2, h0 to α3, and zero to α4, and the LPFA
In FB32 and 34, α1 has h-3, α2
A filter can be realized by assigning h-1 to , h1 to α3, and h3 to α4.

Next, the principle of operation of this filter section will be explained with reference to FIG. FIG. 6(a) shows the principle of signal processing that this portion of the circuit is attempting to perform. A of the device
The clock frequency of the /D converter is 40 M in this example.
Hz, the input signal X (m) of this part is 4
It is a discrete signal sampled at 0 MHz (m is an integer). This signal is filtered by the filter shown in Fig. 6(a), for example,
If the band is limited to 0 MHz or less, aliasing distortion will not occur even if the output signal y (m) of the filter is thinned out to 1/2 to 20 MHz using the switch shown in the figure. If we decide to detect a motion signal from the thinned out signal, the motion detection circuit will need two
It can be configured with a single phase circuit with a clock frequency of 0 MHz, making it easier to implement the device.

FIG. 6(b) shows a configuration in which a circuit equivalent to that in FIG. 6(a) is implemented using two phases. The filter has two-phase input signals x(2n), x(2n-1) (n is an integer)
and two-phase output signals y (2n), y (2n-1)
have. Since the filter is also composed of two phases, the
It can be configured with a MHz circuit, and the entire circuit is all 2
It is a 0 MHz circuit. Therefore, it is easier to realize the device. Since the output of the filter is thinned out, only the output signal y(2n) is inputted to the working detection circuit and used for motion detection. Here, if the impulse response of the filter is h(m), then

[Math. 2] Therefore, to create y(2n), the filter input x(2n) is convolved with the even-numbered impulse response, x(2n-1) is convolved with the odd-numbered impulse response, and then added. Figures 1 and 6 and equation (3
), signals f1A, f-1A become input signal x(2n), signals f1B, f-1B become input signal x(2n-1), and LPFA31, 33 become input signal x(2n-1), and LPFA31, 33 become input signal x(2n-1). , LPFB32, 34 correspond to the second term.

Next, FIG. 7 illustrates the effect of this filter using a signal spectrum. FIG. 7(a) shows the spectrum of the signal (original signal) digitized by the A/D converter 1 in FIG. Since the clock frequency is 40 MHz, it is assumed that the input signal is band-limited to 20 MHz by an analog filter in the A/D converter and then digitized. In this state, as shown by the dotted line in FIG. 7(a), aliasing components due to sampling exist above 20 MHz, and no aliasing distortion occurs. Motion detection is performed from signals obtained by decomposing this signal into two phases, but in order to use only one motion detection section, we simply use one side of the two phases, signals f1A and f-1A, or signals f1B and f-.
If you try to perform motion detection only from 1B, this means thinning the signal with a clock frequency of 40MHz to 1/2, so the signal used for motion detection is as shown in Figure 7.
As shown in (b), the original signal component and the aliasing component overlap, causing aliasing distortion. Therefore, if motion detection is performed from this signal, malfunctions such as erroneous detection or omission of motion may occur, which in turn leads to deterioration of converted image quality of the apparatus. However, if the filters shown in FIGS. 4 and 5 are designed as low-pass filters with a cutoff frequency of 10 MHz and this embodiment is applied, the signals used for motion detection (signals f1s and f- in FIG. 1) 1s) is shown in Figure 7 (c
) become that way. Since this signal does not have aliasing distortion, highly accurate motion detection is possible without degrading the performance of the device.

The present invention is not limited to the embodiments described here, but can also be used in various other devices. Further, even if the device has the same purpose as the embodiments described here, it can be realized using a circuit and a clock frequency different from those of the embodiments. For example, the procedure for determining the band limit of the filter and the interframe difference in the motion detecting section 7 of FIG. 1 may be reversed, and the interframe difference signal may be obtained in two phases, and the band limit may be applied to it. Also, regarding the clock frequency, for example, 112
When converting from a 5-line sequential scanning signal to a 1125-line 2:1 interlaced signal (normal high-definition), the clock frequency is converted from 129.6MHz to 148.5MHz, and conventional devices cannot process complex motion-adaptive signals. Although it has been impossible to realize a processing circuit, according to the present invention, the clock frequency of the signal processing section can be changed from 64.8 MHz to 74 MHz.
．． The frequency becomes 25 MHz, which is a frequency that can be realized by ECL.

[0023]

Effects of the Invention As described above in detail, according to the present invention, after band-limiting the signal from the signal processing unit composed of two phases with a filter composed of two phases, the two-phase signals are added together. By performing equivalent 1/2 decimation processing and performing motion detection from the added signals, the scale of the motion detection circuit can be reduced and the clock frequency of the circuit can be reduced without deteriorating motion detection performance due to aliasing distortion. can be reduced to 1/2, thereby making it easier to integrate the constituent circuits of the motion adaptive signal processing device.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the state of image conversion.

FIG. 3 is a diagram schematically showing only the main parts of the configuration according to the present invention.

FIG. 4 is a diagram for explaining an example of an impulse response of a filter according to the present invention.

FIG. 5 is a diagram showing a circuit example of a filter according to the present invention.

FIG. 6 is a diagram for explaining the operating principle of the filter portion according to the present invention.

FIG. 7 is a signal spectrum diagram for explaining the effect of the filter according to the present invention.

[Explanation of symbols]

1 A/D converter (A/D) 2 Serial/parallel converter (s→p) 3
Signal processing unit A 4 Signal processing unit B 5 Parallel/serial converter (p→s) 6
D/A converter (D/A) 7 Motion detection unit 11 12 Field memory (fM) 13 Motion adaptive spatiotemporal filter 14 Buffer memories 21, 22 Field memory (fM) 23 Motion adaptive spatiotemporal filter 24 Buffer memory 31 , 33 Low pass filter A (LPFA) 3
2, 34 Low pass filter B (LPFB) 35
, 36, 48 Adder 37 Subtractor 38 Motion detection circuit 41-43 D Register 44-47 Coefficient unit

Claims (6)

[Claims] 1. An input digital image signal is decomposed into two-phase signals sampled at a clock frequency that is half the clock frequency of the input digital image signal, and each of the decomposed two-phase signals is processed by two motion adaptive signal processing units. The signals related to one of the two-phase signals extracted from the two processing units are subjected to motion-adaptive signal processing using the odd-numbered impulse response of the filter designed in the original clock frequency domain. supplying a signal related to the other of the two-phase signals to a filter having an even-numbered impulse response of the impulse response of the filter, and adding the output signals of the two filters. detecting the motion of the input image signal from the detected signal, controlling the motion adaptive signal processing of the two motion adaptive signal processing units using the detected signal, and combining the outputs of the two motion adaptive signal processing units. A motion adaptive signal processing method characterized in that a final output signal is obtained by 2. An apparatus for motion-adaptive signal processing of an input digital image signal, wherein the apparatus decomposes the input digital image signal into two-phase signals sampled at a clock frequency that is half the clock frequency of the input digital image signal. Serial of
A parallel converter, two motion-adaptive signal processing units that perform motion-adaptive signal processing on each of the decomposed two-phase signals, and controlling the motion-adaptive signal processing of the two motion-adaptive signal processing units. a motion detection section that supplies a motion detection signal;
a parallel-to-serial converter for synthesizing the outputs of the two motion adaptive signal processing sections;
a filter that causes a signal related to one of the two-phase signals extracted from the two motion adaptive signal processing units to have an odd-numbered impulse response of a filter designed in the original clock frequency domain; A motion adaptive signal processing device comprising: a filter that causes a signal related to the other of the two-phase signals to have an even-numbered impulse response of the impulse responses of the filter. 3. The motion adaptive signal processing device according to claim 2, wherein each of the two motion adaptive signal processing units includes two field memories and a motion adaptive spatiotemporal filter. . 4. The apparatus according to claim 3, wherein each of the two motion adaptive signal processing units further includes a buffer memory for converting the number of horizontal scanning lines and the aspect ratio of the input image signal. A motion adaptive signal processing device characterized by: 5. The apparatus according to claim 2, wherein the motion detection signal detected by the motion detection section comprises:
A motion adaptive signal processing device characterized in that the signal is obtained from an interframe difference signal of an input image signal. 6. The apparatus according to claim 2, wherein when the clock frequency of the input digital image signal is 40 MHz, the clock frequency of the input digital image signal is 40 MHz. A motion adaptive signal processing device characterized in that all clock frequencies do not exceed 20 MHz.