JPH04223771A - Image sensor - Google Patents

Abstract

PURPOSE:To improve an original read rate by accurately digital-processing an analog electric signal from a photodetector element array in an image sensor. CONSTITUTION:Charges accumulated in respective photodetector elements E1, E2,... constituting the light-receiving element array 18 are sequentially outputted to picture charge lines 26 by transfer gates TR1, TR2,... and they are amplified by a difference with a reference voltage by an operand amplifier 34 and they are inputted to a sample and hold circuit 36. A hold gate 36a in the sample and hold circuit 36 executes switching synchronized with a clock signal controlling a transfer gate, charges a hold capacitor 36b at every period of the clock signal and holds the value. The held analog electric signal is outputted from an output terminal OUT and is digitalized in a held period.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor, and more particularly to an image sensor that optically reads data such as characters and symbols on a document and sequentially outputs it as an analog electrical signal.

0002

[Prior Art] Conventionally, an LED that irradiates light onto the surface of a document has been used.
It has a light-receiving element array in which a plurality of image sensor elements that receive light reflected from a light source such as an array and a document surface are arranged in parallel, and an optical system that forms an image on this light-receiving element array. Image sensors for facsimiles and the like that optically read document data such as symbols are well known.

FIG. 3 shows a schematic configuration diagram of such an image sensor, and includes an LED array 10 as a light source.
The light passes through the glass plate 12 and is irradiated onto the original 14. The reflected light from the original 14 enters a cylindrical lens array SLA16, and is focused on a light receiving element array 18 in which a plurality of light receiving elements such as CCD and MOS are arranged in parallel.

The document information photoelectrically converted by the light receiving element array 18 and output as an analog electrical signal is further subjected to desired electrical processing in the circuit board 20, and the document information is read.

[0005] Here, when sequentially outputting analog electrical signals from the light receiving element array 18 to the circuit board 20, this is normally done by supplying a timing signal as shown in FIG. That is, the serial in signal S shown in FIG. 4(a)
When the analog electrical signal output is commanded by I, the signal shown in Fig. 4 (b
) The light receiving element array 18 sequentially outputs the accumulated charges and outputs the analog signal AO shown in FIG. 4(c) as serial data. Note that 500 KHz is mainly used as the clock signal CLK.

[0006]

As described above, conventionally, the analog electrical signal output from the light-receiving element array 18 is further converted into a digital signal using an A/D converter or the like to read document information. As shown in c), the output stabilization time (s in the figure) of the analog electrical signal output from the light receiving element array 18 is extremely short, 200 to 300 ns, and therefore the analog electrical signal is converted into a digital signal by an A/D converter, etc. There was a problem in that the sampling timing had to be set extremely accurately even when converting to . Particularly, in optical reading devices such as image sensors, there is a problem in that such a sampling timing shift causes variations in the gray level, which in turn leads to a decrease in the document reading rate.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide an image sensor that can accurately digitize analog electrical signals output from a light receiving element array and improve the document reading rate. It is about providing.

[0008]

Means for Solving the Problems In order to achieve the above object, the image sensor of the present invention is characterized in that it is provided with a sample and hold circuit that holds an analog electrical signal from a light receiving element array for a predetermined period of time.

[0009]

[Operation] As described above, the image sensor of the present invention can directly A
Rather than digitally converting the data using a /D converter or the like, the original reading rate is improved by holding the data for a predetermined time using a sample hold circuit and then digitizing it.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the image sensor according to the present invention will be described below with reference to the drawings.

The overall configuration of the image sensor of this embodiment is almost the same as that of the conventional one, and as shown in FIG. Cylindrical lens array SLA
16 condenses light onto a light receiving element array 18 and converts it into an electrical signal. The analog electrical signal output from the light receiving element array 18 is subjected to predetermined processing such as digital conversion on the circuit board 20, and the information on the document 14 is read.

A feature of this embodiment is that when digitizing the analog electrical signal output from the light receiving element array 18, the analog electrical signal output from each light receiving element of the light receiving element array 18 is held for a predetermined period of time. The reason is that a sample and hold circuit is provided to facilitate this digitization.

The sample and hold circuit of this embodiment will be explained in detail below using the circuit diagram of FIG. In FIG. 1, the light-receiving element array 18 is composed of a plurality of light-receiving elements, and in this embodiment, 1728 light-receiving elements are arranged in consideration of reading an A4 size document, and the number of light-receiving elements is 8 pixels/mm.
It is possible to read originals at a resolution of In the figure, for convenience, each of these 1728 light receiving elements is
They are numbered sequentially as 2, E3, . . . , E1728. Then, the light reflected from the document surface and collected by the cylindrical lens array SLA16 enters each of these 1728 light receiving elements, and charges corresponding to the amount of light are accumulated.

[0014] Each light receiving element E1, E2, E3,..., E17
28 are transfer gates TR1, TR2...
connected to pixel charge line 26 via TR1728;
The charges accumulated in each light receiving element are sequentially outputted to the pixel charge line 26 by opening and closing the transfer gate.

[0015] Here, transfer gate TR1, T
R2, the gate terminal of TR1728 is the shift register 22
The opening and closing of each transfer gate is controlled by a control signal from this shift register. FIG. 2 shows a timing chart in this embodiment, and when the output control signal S1 (FIG. 2(a)) and the clock signal CLK (FIG. 2(b)) are input to this shift register 22, the shift register 22, each transfer gate TR1, T
R2...Generates a pulse signal to open and close TR1728. That is, in order to output the charge accumulated in the light receiving element E1 during the half period from the rise to the fall of the clock signal CLK, the gate terminal of the transfer gate TR1 of the light receiving element E1 is set to H to transfer the accumulated charge to the pixel charge line 26. Then, the transfer gate T of the light receiving element E2 outputs the charge accumulated in the light receiving element E2 during the half cycle from the next rising edge to the falling edge of the clock signal CLK.
The gate terminal of R2 is set to H and outputted to the pixel charge line 26. Similarly, 1 is synchronized with the clock signal CLK.
Accumulated charges are sequentially output from the 728 light receiving elements E1, E2, . . . , E1728 to the pixel charge line 26.

Further, the pixel charge line 26 is connected to a reference line 28 via a reset gate 24, and a reset signal from the shift register 22 causes the gate terminal of the reset gate 24 to become H, and the pixel charge line 26 to the reference voltage. Set.

Here, as shown in FIG. 2(e), the timing chart of the reset signal supplied from the shift register 22 becomes H during a half cycle from the falling edge of the clock signal CLK to the next rising edge. A pulse signal is output, and during this half period all reset gates 24 are opened, and both the pixel charge line 26 and the reference line 28 are set to the reference voltage.

The pixel charge line 26 and the reference line 28 are converted from high impedance to low impedance by a voltage conversion buffer 30 and then connected to an operational amplifier 3.
It is connected to the non-inverting input terminal of No.2. This operational amplifier 32
The analog electrical signal and reference amplified by each light receiving element are input to an operational amplifier 34, differentially amplified, and supplied to a sample and hold circuit 36, which is a characteristic configuration of this embodiment. The sample and hold circuit 36 of this embodiment has a hold gate 36a, a hold capacitor 36b, an operational amplifier 36c, an output control transistor 36d, and a reset transistor 36e, and is configured to charge and discharge the hold capacitor 36b. The structure is such that the analog electrical output from the light-receiving element is held for a half period of the clock signal by controlling it in synchronization with the clock signal CLK.

That is, as shown in FIG. 2(f), a hold signal H0 synchronized with the clock signal CLK is supplied to the hold gate 36a, and the hold capacitor 36b is charged by the analog electric signal from the light receiving element. Then, a reset signal is supplied to the gate terminal of the reset transistor 36e every cycle of the clock signal CLK to discharge the charge charged in the hold capacitor 36b during one cycle of the clock signal.

[0020] Then, an electric signal from the light receiving element whose value is held for a half period of the clock signal CLK is input to the non-inverting input terminal of the operational amplifier 36c. Furthermore, in the next cycle of the clock signal CLK, the analog electrical signal output from the next light receiving element is held for half a cycle of the clock signal CLK by charging and discharging the hold capacitor 36b.

Then, the analog electrical output represented by the voltage waveform (see V in FIG. 2(g)) before being input to the sample-and-hold circuit 36 is held for half the cycle of the clock signal as shown in FIG. 2(h). A pixel output is obtained, which is output from the output terminal OUT.

The electrical signal output from the sample and hold circuit 36 is further input to an A/D converter (not shown) and digitized, but in this embodiment, as described above, its value is held for half a cycle of the clock signal CLK. For example, by setting the sampling signal when sampling in an A/D converter to the falling edge of the clock signal CLK,
(see Figure 2(i)) can be easily digitized,
It becomes possible to correctly read the amount of charge accumulated in the light receiving element, that is, the information on the document.

[0023]

As explained above, according to the image sensor according to the present invention, the analog electrical signal output from the light receiving element array is held for a certain period of time by the sample hold circuit, thereby facilitating digitization and reading the original. This makes it possible to improve the rate.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of an image sensor according to the present invention.

FIG. 2 is a timing chart diagram of the same embodiment.

FIG. 3 is an overall configuration diagram of an image sensor.

FIG. 4 is a drive timing chart of a light receiving element array in a conventional image sensor.

[Explanation of symbols]

10 Light emitting element array 18 Photo-receiving element array 22 Shift register 26 Pixel charge line 28 Reference line 36 Sample and hold circuit

Claims (1)

[Claims] 1. An image sensor comprising a light-emitting element and a light-receiving element, which irradiates a document with light from the light-emitting element, receives the reflected light by the light-receiver, converts it into an electrical signal, and reads information on the document, An image sensor comprising a sample and hold circuit that holds an analog electrical signal from the light receiving element for a predetermined period of time.