JPH04222991A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the information reading time just after the information writing by separating the base electrode of a high polar transistor from common data paired lines with a switching element. CONSTITUTION:In a write-in cycle, MOSFETQ 10, Q11 are turned OFF with a switch control signal WS* from a NAND gate 23. Then the reading amplifier 30 is cut off from the common data paired lines 28 in a writing cycle. Thus the current amplification ratio of the bipolar transistors Q1,Q2 is not degraded and the load capacity of the common data paired lines is decreased. With both efficiencies the operation of the read-out amplifier 30 just after the write-in cycle, is not delayed and the read-out time is shortened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a technique for speeding up the read time therein, and relates to a technique that is effective when applied to, for example, a BiCMOS memory formed by combining a bipolar transistor and a MOSFET.

0002

2. Description of the Related Art FIG. 4 shows the main parts of a conventional BiCMOS memory.

In FIG. 4, D and D* (* means an inverted signal line or row active signal) are a data line pair, and WL is a word line.
Memory cell 1 is coupled to * and word line WL. A common data line pair 5 is coupled to the data line pair D, D* via column selection switches SW1, SW2 driven by a Y-system selection signal YD. A data write circuit 3 for the memory cell 1 is coupled to the common data line pair 5, and a read amplifier 7 for reading data from the memory cell 1 is coupled to the common data line pair 5. It is coupled to the readout circuit 4 via a common collector line pair 6. The read amplifier 7 includes a bipolar transistor to enable high-speed data read.

Data reading from memory cell 1 is performed as follows.

By driving the word line WL to the selection level, the data held in the memory cell 1 is transferred to the data line pair D,
It appears as a potential difference at D*. At this time, when the Y system selection signal is asserted to high level, the column selection switch S
W1, SW2 are turned on, thereby data line pair D,
The potential difference D* is transmitted to the common data line pair 5. The potential difference between the common data line pair 5 is amplified by the read amplifier 7 and then transmitted to the read circuit 4 via the common collector line pair 6, and the read circuit 4 enables external output of read data.

Data writing to memory cell 1 is performed as follows.

Word line WL is driven to a selection level, and Y
When the system selection signal is asserted to a high level, column selection switches SW1 and SW2 are turned on, thereby selecting memory cell 1 and connecting data line pair D and D* to common data line pair 5. At this time, the write circuit 3 is operated and one data line of the common data line pair 5 is set to GN.
The voltage is lowered to the D (ground) level, thereby making it possible to write predetermined data into the memory cell 1.

[0008] Examples of documents describing data write circuits and data read circuits in semiconductor memories include ISC, Digest Technical Papers, pages 186 to 18.
7 pages, 1988 (ISSCC, Digest of
Technical Papers, PP. 186
-187, 1988).

[0009]

[Problem to be Solved by the Invention] In a semiconductor memory device as shown in FIG. 4, when data is read out immediately after writing data into a memory cell 1, the operation of the read amplifier 7 is delayed, which causes data readout to be delayed. The inventor of the present invention has discovered that there is a problem of time delay, and this is considered to be the main factor that inhibits speeding up of data read in semiconductor memory devices. Such a problem arises because when writing information to the memory cell 1, one data line of the common data line pair 5 is forcibly pulled down to the GND level. This is due to the fact that the bipolar transistors Q1 and Q2 are reverse biased and the current amplification factor hfe of the input first stage element is reduced.
This was made clear through study by the inventor.

An object of the present invention is to provide a technique that can shorten the time required to read data immediately after writing data.

Another object of the present invention is to reduce the load capacitance of a common data line pair during information writing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0013]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, a write circuit for writing data into the memory cell and a write circuit for amplifying read data from the memory cell are connected to a common data line pair to which the bit lines of the memory cells are commonly connected via a column selection switch. When a semiconductor memory device is formed by combining a read amplifier with a read amplifier, a bipolar transistor that is in an off state during a write cycle is connected between the base electrode of a bipolar transistor serving as the first input stage of the read amplifier and the common data line pair. A controlled switching element is provided. At this time, a control circuit may be provided to control the switch element in synchronization with the write control signal. In a more specific embodiment, the switch element can be a MOSFET.

[0015]

[Operation] According to the above-described means, the switch element provided between the base electrode of the bipolar transistor and the common data line pair is turned off during a data write cycle to the memory cell, so that the base electrode of the bipolar transistor is turned off during the data write cycle to the memory cell. The electrode and the common data line pair are separated, and when one of the common data line pairs is pulled down to the ground level during data writing, the bipolar transistor is prevented from being reverse biased, and the current amplification factor of the bipolar transistor is reduced. to prevent This prevents a delay in the read time immediately after data writing and makes it possible to shorten the data read time. Furthermore, separating the base electrode of the bipolar transistor and the common data line pair as described above works to reduce the load capacitance of the common data line pair as a result.

[0016]

[Example] Figure 2 shows a BiCMO which is an example of the present invention.
S memory is shown.

The BiCMOS memory shown in FIG. 2 is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique, although it is not particularly limited.

In FIG. 2, D and D* are a representative data line pair, WL is a representative word line,
A representatively shown memory cell 20 is coupled to this data line pair D, D* and word line WL. memory cell 20
is a static type memory cell, although it is not particularly limited. Word line WL is driven to a selection level by X driver 16. In the front stage of this X driver 16,
A decoder 14 and an X address buffer 10 are arranged. The X address AX taken in via the X driver 16 is decoded by the X decoder 14, and a predetermined word line WL is driven to a selection level based on the decoded output. A Y driver 17 is coupled to the data line pair D, D*, and a column selection section 22 is driven by a Y system selection signal YS output from the Y driver 17. The column selection section 22 includes column selection switches SW1 and SW2 arranged corresponding to the data line pair D and D*, and an N-channel type MOSFET and a P-channel type MOSFET that constitute the column selection switches SW1 and SW2. It includes an inverter 27 that inverts the Y-system selection signal YS and transmits it to the P-channel MOSFET for interlocking. A Y decoder 15 and a Y address buffer 11 are arranged before the Y driver 18, and predetermined column selection switches SW1 and SW2 are selectively activated based on the decoded output of the Y address AY taken in via the Y address buffer 11. It is designed to be driven. By turning on the column selection switches SW1 and SW2, the corresponding data lines D and D* are coupled to the common data line pair 28. A write amplifier 18 is coupled to the common data line pair (CDL, CDL*) 28, and data Din input from the outside via the input buffer 12 can be written.

Reference numeral 30 denotes a read amplifier for reading data from the memory cell 20, and a read amplifier 30 is connected between the read amplifier 30 and the common data line pair 28 during a read cycle. A switch circuit 29 for disconnecting from the common data line pair 28 is provided.

Reference numeral 19 denotes a control circuit, and this control circuit 19 is supplied with internal control signals φr, φcs, etc. via an input buffer 13 arranged in the preceding stage. Control signal φcs is set to high level in response to the low level of chip select signal cs* and is used to activate internal circuits. The control signal φr is set to high level in response to the high level of the write enable signal WE*, and is used for activating data read related circuits. These control signals are subjected to predetermined timing or logic by a control circuit 19 to generate control signals for controlling each part of the memory of this embodiment. The switch control signal WS* shown as a representative is generated by this control circuit 19, and when the signal WS* is set to a high level during a write cycle, the switch circuit 29 is turned off, thereby turning off the read amplifier. 3
0 is disconnected from the common data line 28.

The output of the read amplifier 30 is transmitted to the sense amplifier 32 via the common collector line pair (CCL, CCL*) 31, and after being amplified by the sense amplifier 32, the output is transmitted to the sense amplifier 32 via the output buffer 33 at the subsequent stage. External output is possible.

FIG. 1 shows a detailed configuration of the main parts of the BiCMOS memory shown in FIG.

The switch circuit 29 is formed by two P-channel type MOSFETs Q10 and Q11 as switch elements. The MOSFET Q10 is arranged between one data line forming the common data line pair 28 and the base electrode of the bipolar transistor Q1 forming the read amplifier 30, and the MOSFET Q11 is
It is arranged between the other data line forming the common data line pair 28 and the base electrode of the bipolar transistor Q2 forming the read amplifier 30. The above MOSF
The gate electrodes of ETQ10 and Q11 are connected to the controller 19.
are connected in common to the controller 19, and are controlled to be turned on and off simultaneously by this controller 19.

The controller 19 has i (i is a positive integer)
It has a two-input NAND gate 23 that obtains NAND logic between the Y-th Y address signal AYi and the write enable signal WE*, and the output of this NAND gate 23 is set to high level during a write cycle, thereby causing MOSFETQ10,
Q11 is turned off at the same time.

The read amplifier 30 is constructed as follows.

Collector electrodes of bipolar transistors Q1 and Q2 are coupled to a high potential power supply Vcc, and emitter electrodes are coupled to base electrodes of bipolar transistors Q3 and Q4 via diodes D1 and D2, respectively. Collector electrodes of the bipolar transistors Q3 and Q4 serve as an output section of the read amplifier 30 and are coupled to a common collector line pair 31. Furthermore, the emitter electrodes of bipolar transistors Q3 and Q4 are N-channel MOSFETs.
It is coupled to the low potential side power supply Vss via ETQ5. A predetermined reference potential generated by the control circuit 19 is applied to the drain electrode of the MOSFET Q5, so that a predetermined bias current flows through the bipolar transistors Q1 to Q4. With this configuration, the potential difference between the common data line pair 28 transmitted via the switch circuit 29 is amplified by the bipolar transistors Q1 to Q4 and output to the common collector line pair 31.

FIG. 3 shows the operation timing of the main parts of the memory of this embodiment.

Data reading from memory cell 20 is performed as follows.

By driving the word line WL to a selection level based on the output of the X decoder 14, the data held in the memory cell 20 appears as a potential difference on the data line pair D, D*. At this time, based on the output of the Y decoder 15, Y
When the system selection signal YD is asserted to a high level, the column selection switches SW1 and SW2 are turned on, thereby changing the potential difference between the data line pairs D and D* to the common data line pair 28.
transmitted to. In the data read cycle, the internal control signals φcs and φr are set to high level, so the switch control signal WS* output from the control circuit 19
is set to low level, and MOSFETs Q10 and Q11 are turned on. Therefore, the potential difference between the common data line pair 28 is transmitted to the bipolar transistors Q1 and Q2 via MOSFETs Q10 and Q11, amplified by the read amplifier 30, and then transferred to the sense amplifier 32 and the output buffer 3.
3 in order and output to the outside.

Data writing to the memory cell 20 is performed as follows.

The word line WL is driven to the selection level based on the output of the X decoder 14, and the Y system selection signal YD is asserted to a high level based on the output of the Y decoder 15, so that the column selection switches SW1, SW2
is turned on, thereby selecting the memory cell 20 and connecting the data line pair D, D* to the common data line pair 28. At this time, the write amplifier 18 is enabled to operate under the control of the control circuit 19, and the common data line pair 28
One data line of is pulled down to the GND level. As a result, predetermined data is written into the memory cell 20. In this write cycle, the write enable signal WE* is set to a low level, so that the control signal φr is set to a low level, and thereby the switch control signal WS* output from the control circuit 19 is set to a high level. Q11 is turned off. Therefore, in this write cycle, read amplifier 30 is disconnected from common data line pair 28, and the base electrodes of bipolar transistors Q1 and Q2 are electrically released. As a result, in the write cycle, one data line of the common data line pair 28 is set to GN.
Even when the voltage is lowered to the D level, it does not affect the base electrodes of the bipolar transistors Q1 and Q2, and the bipolar transistors Q1 and Q2 are not reverse biased. In other words, the current amplification factors hfe of the bipolar transistors Q1 and Q2 do not need to be reduced in the write cycle. Therefore, in the read cycle immediately after the write cycle, the operation of the read amplifier 30 is not delayed, and the data read time immediately after data write can be shortened compared to the conventional memory shown in FIG.

According to the above embodiment, the following effects can be obtained.

(1) In the write cycle, the switch control signal WS* output from the control circuit 19 (NAND gate 23) is set to high level, so that the MOS
FETs Q10 and Q11 are turned off, thereby disconnecting read amplifier 30 from common data line pair 28. Therefore, even if one data line of the common data line pair 28 is pulled down to the GND level in a write cycle, bipolar transistors Q1 and Q2 do not need to be reverse biased, so that the current of bipolar transistors Q1 and Q2 in a write cycle amplification factor hfe
Therefore, the operation of the read amplifier 30 is not delayed in the read cycle immediately after the write cycle. As a result, the data reading time immediately after data writing is shortened, so that the data reading time according to the specifications of the BiCMOS memory can be shortened.

(2) As mentioned above, MOSFETQ10,
By turning off Q11, the read amplifier 30 is disconnected from the common data line pair 28, so the load capacitance of the common data line pair 28 is reduced accordingly.
This is extremely effective in speeding up the equalizing operation by the equalizing switch element arranged to short-circuit the common data line pair 28, especially in speeding up the equalizing immediately after data writing.

(3) MOSFETQ10, Q1 in synchronization with the write enable signal WE* as a write control signal.
Although the NAND gate 23 that controls MOSFET Q1 is a simple circuit, it
10 and Q11 can be appropriately controlled to turn off.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, instead of the P-channel MOSFETs Q10 and Q11 as switching elements, elements such as N-channel MOSFETs and bipolar transistors may be used.

[0038] In the above explanation, the invention made by the present inventor will be mainly explained in relation to the field of application, BiC, which is the background of the invention.
Although the case where the present invention is applied to an OS memory has been described, the present invention is not limited thereto, and can also be applied to semiconductor devices such as microcomputers and data processing devices that include the same.

The present invention can be applied to conditions including at least a read amplifier having a bipolar transistor.

[0040]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, by turning off the switch element provided between the base electrode of the bipolar transistor and the common data line pair during the data write cycle to the memory cell, the base electrode of the bipolar transistor and the common data line pair are turned off. When one of the common data line pairs is pulled down to the ground level during data writing, the bipolar transistor is prevented from being reverse biased, and the current amplification factor of the bipolar transistor is reduced. thwarted. This prevents a delay in read time immediately after data is written, and reduces data read time. In addition, by separating the base electrode of the bipolar transistor and the common data line pair as described above, the load capacitance of the common data line pair is reduced accordingly, which speeds up equalization of the common data line pair immediately after writing. can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of an embodiment of a BiCMOS memory according to the present invention.

FIG. 2 is an overall configuration block diagram of an embodiment of a BiCMOS memory according to the present invention.

FIG. 3 is an operation timing diagram of the memory of this embodiment.

FIG. 4 is a block diagram of the main parts of a conventional BiCMOS memory.

[Explanation of symbols]

19 Control circuit 20 Memory cell 23 NAND gate 24 Column selection switch 28 Common data line pair 29 Switch circuit 30 Read amplifier 31 Common collector line pair D, D* Data line pair Q1 Bipolar transistor Q2 Bipolar transistor Q10 P-channel type MOSFET Q11 P-channel type MOSFET SW1 Column selection switch SW2 Column selection switch WL Word line YD Y system selection signal

Claims (3)

[Claims] 1. A write circuit for writing data into the memory cell to a common data line pair to which the bit lines of the memory cell are commonly connected via a column selection switch;
In a semiconductor memory device coupled with a read amplifier for amplifying read data from a memory cell, between the base electrode of a bipolar transistor serving as the first input stage of the read amplifier and the common data line pair, A semiconductor memory device comprising a switch element that is controlled to be in an off state during a write cycle. 2. The semiconductor memory device according to claim 1, further comprising a control circuit that controls the switch element in synchronization with a write control signal. 3. The semiconductor memory device according to claim 1, wherein the switch element is a MOSFET.