JPH04220855A - Parallel test control system for multi-processor type electronic exchange - Google Patents

Abstract

PURPOSE:To realize the parallel test control system in the multiprocessor type electronic exchange in which a time required for a line test is reduced. CONSTITUTION:A test execution control section 4 of each call processor CPR 3 is started by a command of test start from a test control section 2 of a main processor MPR 1. Thus, the test execution control section 4 sends a command of execution start of a line test sequentially to plural line processors LPR 5 under its control. A test execution section 6 of each LPR 5 connects a line test equipment 7 to each subscriber circuit accommodated in a line concentrator by this command to execute a predetermined test sequentially. Thus, since the line test is executed almost simultaneously in the plural LPR 5, the test period is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel test processing method for a multiprocessor type electronic exchange, and more particularly to a method for parallel test control of a large number of subscriber circuits accommodated in the multiprocessor type electronic exchange.

[0002] An electronic exchange that accommodates a large number of subscribers uses a line processor (referred to as LPR) that performs processing to condense a certain number of subscriber circuits, and a switching network that processes incoming and outgoing calls. Call Processors
sor): A main processor (referred to as CPR) that manages multiple call processors.
essor (referred to as MPR), etc. In such multiprocessor type electronic exchanges, tests are conducted periodically to confirm the normality of each subscriber's circuit, and as the conventional method is time-consuming, improvements are desired.

0003

2. Description of the Related Art FIG. 4 is a diagram showing the configuration and processing flow of a conventional example, and FIG. 5 is an explanatory diagram of a conventional test method. A in Figure 4
．． shows the system configuration of a conventional multiprocessor electronic switching system. In the figure, the network (NW) accommodates a highway that connects to a large number of line concentrators (LC), and each LC accommodates a large number of subscriber circuits. has been done. Each line concentrator LC is provided with a line processor (LPR) for monitoring and processing each subscriber circuit.
A call processor (CPR) that processes calls for each subscriber and controls the network for these multiple LPRs is provided corresponding to each network, and a main processor (CPR) that manages and controls the multiple CPRs is provided for each network.
MPR) is connected to each CPR. Each NW (CPR
) is a line for testing the electrical characteristics (insulation, resistance, etc.) and functions (referred to as line tests) of the subscriber circuits in order to confirm the normality of the multiple subscriber circuits housed in the LC. Test equipment (LTE: Line Test Equ
ipment) is provided.

The conventional line test processing flow is shown in FIG. 4B.
．． is shown. The state of test execution according to this processing flow will be explained using FIG. 5. A in FIG. B. shows the operation for conducting the conventional test. is a timing chart. 50 in FIG. 5 is the main processor MPR, 5
1 is a test control unit in the MPR, 52 is a call processor C
PR, 53 is a test execution control unit in CPR, 54 is a line processor LPR, 55 is a test execution unit in LPR, 56
is a line test device that is provided for each CPR and is shared by each LPR.

[0005] When a command to start a test is first issued from the test control unit 51 of the MPR 50, the test execution control unit 53 of each CPR 52 is activated. Then, B. in FIG. The process shown in is started, and the test execution unit 55 of one LPR 54 is called. The test execution unit 55 of the LPR 54 called by the test execution control unit 53 of the CPR 52 executes the test execution unit 55 of the LPR 54 in accordance with B. As shown in the figure, a vacant LTE 56 in the CPR is captured (L
If there is only one TE, capture when that LTE is free)
.

[0006] Next, using the captured LTE 56, a predetermined test is performed for each subscriber circuit, and when the test is completed, the control returns to the test execution control section 53. The test execution control unit 53 controls the next L under the control of the same CPR 52.
The test execution unit 55 of the PR 54 is called to execute the test in the same manner as described above, and thereafter the test is executed in order for all LPRs 54 under the control of the same CPR 52. The timing chart of the above operation is shown in B of FIG. Shown below. As shown in this figure, multiple CPR1 to CPRi start up at the same time, each test starts from LPR1, and LPRj
It can be seen that the tests are executed sequentially until

[0007]

[Problems to be Solved by the Invention] According to the above-mentioned conventional subscriber circuit testing method in the multiprocessor type electronic exchange, the test was controlled in units of CPR.
As the processing power of the LPR accommodated in R improves,
The number of subscribers that can be accommodated in CPR has also increased significantly, and one L
A PR may accommodate 2000 subscribers. For this reason, the scale of equipment that directly accommodates subscribers has increased, and a single C
There is a problem in that the time required to test all subscriber circuits accommodated in the PR increases (see B in FIG. 5). Furthermore, if testing takes longer, the problem arises that the time required to discover and repair faults increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel test control method for a multiprocessor type electronic switching system that can shorten the time required for line tests.

[0009]

[Means for Solving the Problems] FIG. 1 is a basic configuration diagram of the present invention. In the figure, 1 is a main processor (MPR) that manages each call processor, 2 is a test control unit provided in MPR 1, and 3 is connected to a line processor that controls the network (not shown) and performs call processing. A call processor (CPR), 4 is a test execution control unit provided in the CPR 3, 5 is a line processor (LPR) that controls a line concentrator accommodating a plurality of subscribers and monitors and controls each subscriber circuit, 6 is a test execution unit provided in the LPR 5, and 7 is a line test equipment (LTE).

The present invention provides a line test device for a line concentrator that accommodates a large number of subscribers, and when a call processor instructs a plurality of line processors under its control to execute a test almost simultaneously, each line processor runs in parallel. In this system, the subscriber circuits in each line concentrator are tested by a line test device provided corresponding to the line processor.

[0011]

[Operation] When an instruction to start a test is sent from the test control unit 2 of the MPR 1 to each CPR 3, the test execution control unit 4 of each CPR 3 is activated. As a result, the test execution control unit 4 sends a command to sequentially start executing line tests to the plurality of LPRs 5 under their respective control. Upon receiving this command, the test execution unit 6 of each LPR 5 connects the line test device 7 installed in each line concentrator to each subscriber circuit housed in the same line concentrator, and sequentially executes the determined test. do. When each LPR 5 completes the line test for all the subscriber circuits accommodated therein, the line test device 7 is released. In this way, the line test is executed almost simultaneously on the plurality of LPRs 5, so that the test time can be shortened.

0012

Embodiment FIG. 2 is a hardware configuration diagram of a multiprocessor type electronic exchange according to an embodiment, and FIG. 3 is a processing flow and timing chart of the embodiment. In FIG. 2, 1 is the main processor MPR, 3 is the call processor CPR, 5 is the line processor LPR, and 7 is the line test device LTE provided corresponding to each line concentrator, which is the same as in FIG. 1 above. 8 is a line concentrator LC, 9 is a subscriber circuit, 10
represents the network NW.

Using the hardware configuration shown in FIG. 2, the test control method according to the present invention will be explained using the processing flow shown in FIG. 3. First, a command to start a line test is sent from the MPR 1 to each CPR 3 according to an instruction from the maintenance console or a program. Upon receiving this, each CPR 3 activates a test execution control unit configured with a program provided therein. The processing flow of the test execution control unit is shown in A of FIG. and when started, this C
A command is generated to call one of the test execution units in the LPR5 of a plurality of line concentrators 8 housed in the NW10 controlled by the PR3. This operation of calling the test execution unit is sequentially executed for each LPR5, and when executed for all LPR5s under the control of this CPR, this CPR3
The process ends.

On the other hand, each LPR 5 is equipped with a test execution section consisting of a program, which is activated when called from the CPR 3, and executes the test execution section shown in FIG. Free LTE in LC8 as shown in
Capture the data and perform a line test. This line test is
In the configuration shown in FIG. 2, the test is performed by turning on the switch connecting LTE7 and one subscriber circuit 9 to be tested, and when the test is completed for one subscriber circuit 9, the next subscriber circuit 9 is tested. Circuit 9 is selected and similarly LTE7
When the test is completed on all subscriber circuits 9 accommodated in the same LC8
The processing of the test execution unit in PR5 ends.

B. of FIG. The timing chart for the test of the above example is shown, and as shown in the figure,
The test operation in each CPR1 to CPRi is determined by the test time by LPR in each CPR, and is determined by the test time in B of FIG. 5 of the conventional example. It is clear that the test time is significantly reduced compared to

[0016]

[Effects of the Invention] According to the present invention, the time required for one test is determined by the number of test target devices accommodated in one line processor, and testing of thousands of devices can be performed in a short time, thereby improving the serviceability of electronic exchanges. and improved reliability can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a hardware configuration diagram of an embodiment of the present invention.

FIG. 3 is a processing flow diagram of the embodiment.

FIG. 4 is a diagram showing the configuration and processing flow of a conventional example.

FIG. 5 is an explanatory diagram of a conventional test method.

[Explanation of symbols]

1 Main processor (MPR) 2 Test control unit 3 Call processor (CPR) 4 Test execution control unit 5 Line processor (LPR) 6 Test execution unit 7 Line test equipment (LTE)

Claims (2)

[Claims] Claim 1. A multiprocessor type electronic switching system in which a plurality of call processors control corresponding networks, and a plurality of line processors controlled by each call processor each control a line concentrator accommodating a large number of subscriber circuits, comprising: A line test device is provided corresponding to each line concentrator, and each call processor instructs multiple line processors under its control to start a line test at the same time in response to an instruction to start a test. 1. A parallel test control method for a multiprocessor type electronic exchange, characterized in that the line test device is connected to each subscriber circuit housed in a line concentrator for testing. 2. A multiprocessor type electronic exchange according to claim 1, comprising a main processor that controls a plurality of call processors, and each processor instructs to start a line test according to an instruction from the main processor. Parallel test control method.