JPH0421961A - Medium speed change monitoring circuit - Google Patents

Abstract

PURPOSE:To obtain the medium speed change monitoring circuit to perform high-quality write by measuring the medium speed change of an entire data. CONSTITUTION:An interval T1 is measured by a first counter 19 and compared with a reference value 1 from a processor 18 by a first comparator part 21 so as to detect error. An interval T2 is measured by a second counter 22 and compared with a reference value 2 from the processor 18 by a second comparator part 24 so as to detect error. Thus, the medium speed change of a preamble part is checked by measuring the intervals T1 and T2. Intervals TD1 -TDn are measured by a third counter 25 and compared with a reference value 3 from the processor 18 by a third comparator part 28 so as to detect error according to compared results. Then, the medium speed check of a data part is checked by measuring the intervals TD1 -TDn. Therefore, the write can be performed with much higher quality.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a medium speed change monitoring circuit in a magnetic recording/reproducing device, and provides a medium speed change monitoring circuit that can perform higher quality writing by measuring the medium speed change of the entire data. a first counting means for counting the interval between the block detection signal and the demodulated okay signal; a first comparing means for comparing the output of the first counting means with a reference value; a second counting means for counting the interval of the data OK signal; a second comparing means for comparing the output of the second counting means with a reference value; The third counting means counts the interval between synchronization detection signals, and the third comparing means compares the output of the third counting means with a reference value.

[Industrial Field of Application] The present invention relates to a medium running speed change monitoring circuit in a magnetic recording/reproducing device.

In a magnetic recording/reproducing device, a motor rotates a media feed roller to move the media, and a write head writes data on the media. When running this medium,
Medium speed fluctuations may occur between the medium and the rollers, but these medium speed fluctuations are caused by slipping or the like and cannot be detected by the rotation of the motor.

In order to perform higher quality writing, it is necessary to detect media speed changes in all parts of the data.

[Prior Art] Examples of conventional media speed change monitoring systems include those shown in FIGS. 6 and 7.

In FIG. 6, 1 is a medium of a magnetic recording/reproducing device;
The medium 1 is driven by a medium feed roller 3 that is rotationally driven by a motor 2 . Arrow A indicates the rotation direction of the medium feed roller 3, and the medium 1 travels in the direction shown by arrow B due to the rotation of the medium feed roller 3.

4 is a write head, and data is written onto the medium 1 by the write head 4. 5 is a read head;
Data is read from the medium 1 by a read head 5 .

As shown in FIG. 7, the data on the medium 1 consists of a preamble part, a data part, and a postamble part, which constitute one block. An internal block gap (IBG) exists before and after the block.

In the conventional example, the medium speed was checked only at the beginning part of the write data, that is, the preamble part. That is, the check section is set only in the preamble portion, and in this check section it is checked whether the medium speed is within the standard centered around the reference speed, and if it is out of the standard, it is determined as an error.

[Problem to be Solved by the Invention] However, in such a conventional medium speed change monitoring method, since the medium speed is checked only in the preamble portion, the problems shown in b and c in FIG. 7 occur. Although it is possible to treat such media speed as an error, it is possible to detect media speed changes that are within the standard in the preamble part but exceed the standard in the parts that follow or before it, as shown by A and C in Figure 8. Even if this occurred, it could not be detected as an error. As a result, there was a problem in that writing with higher quality could not be performed.

The present invention has been made in view of such conventional problems, and provides a medium speed change monitoring circuit that can perform higher quality writing by measuring medium speed changes of the entire data. The purpose is to

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 19 is a first counting means for counting the interval between the block detection signal and the demodulated OK signal; 21 is a first comparing means for comparing the output of the first counting means 19 with a reference value;
2 is a second counting means for counting the interval between the demodulated OK signal and the data OK signal; 24 is a second comparison means for comparing the output of the second counting means 22 with a reference value; and 25 is a constant interval in the data section. Third counting means 28 counts the interval of the resynchronization detection signal for detecting the inserted resynchronization portion, and third comparison means compares the output of the third counting means 25 with a reference value.

[Operation] The interval between the block detection signal and the demodulated okay signal is counted by the first counting means, the counted count value is compared with a reference value by the first comparing means, and error detection is performed based on the comparison result.

The interval between the demodulated OK signal and the data OK signal is counted by the second counting means, the counted count value is compared with a reference value by the second comparing means, and error detection is performed based on the comparison result.

The interval of the resynchronization detection signal for detecting the resynchronization part inserted at regular intervals in the data section is counted by the third counting means, the counted count value is compared with the reference value by the third comparison means, and the comparison result is Error detection is performed by.

In this way, since the medium speed change is measured for the entire data, it is possible to perform writing with higher quality.

[Example] Embodiments of the present invention will be described below based on the drawings.

2 to 5 are diagrams showing an embodiment of the present invention.

First, to explain the configuration, in FIG. 3, 11 is a medium, and data on the medium 11- is read by a read head 12 and amplified by an amplifier 13.

Here, as shown in Fig. 4, the data is subdivided into a preamble part, a data part, and a postamble part, and the length of each data part is fixed to X bytes, and the R3YNC part is divided for every X bytes of data. It has been inserted. This R8Y
Since the NC part is a special data pattern indicating a resynchronization part, this part can be detected separately from the data part.

This R8YNC portion is detected by the R3YNC detection circuit 14, and an R,SYNC detection signal (resynchronization detection signal) is output.

In the preamble part, the block detection circuit 1-5 detects a block and outputs a block detection signal, and the data demodulation circuit 16 detects that data demodulation is OK and demodulates the block. An OK double signal is output, and furthermore, the data detection circuit 17 detects the actual data portion and outputs a data OK signal.

The processor 18 processes the input signal and also sets three reference values corresponding to each signal of the certain byte length]
Outputs 3.

The block detection signal and the demodulated OK double signal are input to the first counter (first counting means) 19 in FIG.

Further, a reference clock within the device is input to the clock terminal of the first counter 1-9, and this reference clock is exactly n times (for example, 1 time) the 1-byte length of the data. This first counter 9 has a block detection signal of “L”.
” level, it is reset and the block detection signal is “
When the level reaches "H", it starts counting.Then, the first counter 9 outputs "
Counting is stopped when the level changes from "L" to "H". This count value is sent to the first comparison section (first comparison means) 21 and compared with the reference value 1 from the processor 18, and if it is within the reference value 1. In this case, no error detection is performed.

The second counter (second counting means) 22 includes a reference clock,
Data OK via demodulation OK double signal and inverter 23
Signals are input respectively. Second counter 22 is demodulated OK
When the double signal reaches H” level, it starts counting and data O
The count when the K signal changes from the "■" level to the "H" level is stopped.

The count value counted by the second counter 22 is sent to a second comparison section (second comparison means) 24 and compared with the reference value 2 from the processor 18, and if it is within the reference value 2, no error detection is performed.

The reference clock and the output of the NOR circuit 26 are input to the third counter (third counting means) 25 . The NOR circuit 26 receives a signal obtained by inverting the data OK signal and the R3YNC detection signal, and when both are at the "L" level, the output of the NOR circuit 26 becomes the "H" level, and the third counter 25 performs counting. This count value is latched by the latch circuit 27 and then sent to the third comparator (third
The signal is sent to the comparison means 28 and compared with the reference value 3 from the processor 18, and if it is within the reference value 3, no error detection is performed.

Next, the operation will be explained.

FIG. 4 shows a time chart of this embodiment, where T1 is the interval between the block detection signal and the demodulated OK double signal, and T2 is the interval between the demodulated OK double signal data OK signal, TDI to TD. indicates the interval of R8YNC detection signals, respectively.

The interval T1 is measured by the first counter 19 and compared with the reference value 1 from the processor 18 by the first comparator 21. Error detection is performed based on the comparison result.

The interval T2 is measured by the second counter 22 and compared with the reference value 2 from the processor 18 by the second comparator 24. Error detection is performed based on the comparison result. in this way,
By measuring the distances T, . . . T2, a check is made for changes in the medium velocity in the preamble section.

Interval T. , ~TDn are measured by the third counter 25 and compared with the reference value 3 from the processor 18 by the third comparator 28. Error detection is performed based on the comparison result. Interval T. , .about.TDn is used to check for changes in medium velocity in the data portion.

In this way, it is possible to check for medium speed changes not only in the preamble portion but also in the entire data as shown in FIG.

Therefore, higher quality writing can be performed.

Note that in this embodiment, the reference value 1 from the processor is
~3 and the synchronization of the reference clock can change the accuracy of the measurement of media velocity changes.

[Effects of the Invention] As described above, according to the present invention, since the medium speed change is measured for the entire data, it is possible to perform writing with higher quality.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is an explanatory diagram of each signal, Fig. 4 is a time chart, and Fig. 5 is a medium speed check section. FIG. 6 is an explanatory diagram of conventional media running, FIG. 7 is an explanatory diagram of conventional media speed check, and FIG. 8 is an explanatory diagram of problems. In the figure, 11...Medium, 12...Reading head, 3...Amplifier, 4...R8YNC detection circuit, 5...Block detection circuit, 6...Data demodulation circuit, 7... Data detection circuit, 8... Processor, 9... First counter (first counting means), 0... Inverter, 1... First comparing section (first comparing means), 2... Second Counter (second counting means) 3... Inverter, 4... Second comparing section (second comparing means), Third counter (third counting means) 6... NOR circuit, 7... -Latch circuit, 8...Third comparison section (third comparison means).

Claims (1)

[Claims] a first counting means (19) for counting the interval between the block detection signal and the demodulation OK signal; a first comparison means (21) for comparing the output of the first counting means (19) with a reference value; The second one counts the interval between the signal and the data OK signal.
a counting means (22); a second comparison means (24) for comparing the output of the second counting means (22) with a reference value; and a resynchronization unit for detecting resynchronization parts inserted at regular intervals in the data section. A medium speed characterized by comprising: a third counting means (25) for counting the interval between detection signals; and a third comparing means (28) for comparing the output of the third counting means (25) with a reference value. Change monitoring circuit.