JPH04219014A - Low frequency delay circuit - Google Patents

Abstract

PURPOSE:To obtain a delay clock with a waveform having no disturbance and with a desired duty ratio by delaying an input clock by a desired time through the operation in a short time. CONSTITUTION:The low frequency delay circuit giving an optional delay to an inputted clock and outputting the delayed signal consists of a delay generating means comprising a 1st monostable multivibrator 14 outputting a lock whose pulse width depends on a time constant upon the receipt of the clock, a 1st capacitor being one factor of the time constant and a 1st variable resistor means 15 varying the said time constant by varying its resistance, and of a duty ratio correction means comprising a 2nd monostable multivibrator 19 receiving a delay clock whose pulse width depends on a time constant upon the receipt of the clock from the said 1st monostable multivibrator, a 2nd capacitor being one factor of the said time constant and a 2nd variable resistor 20 means varying the said time constant by varying its resistance.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to low frequency delay circuits.

ES (Engineering Samp)
When performing evaluation tests such as 1.e), input phase margin measurements such as setup and hold are performed. At this time, delay means such as buffers or delay lines are usually used to delay the input clock (low frequency). . However, since the operation of the delay means is troublesome, it may take more time than necessary, and the waveform of the output clock may be disturbed due to variations in the duty ratio.

[0003] Therefore, there is a need for a delay means that can delay the clock without such a problem occurring.

0004

2. Description of the Related Art Delay means necessary for performing input phase margin measurements as described in the field of industrial application will be explained with reference to FIGS. 6 to 8. FIG. 6 is a block diagram of a slide type delay line, FIG. 7 is a block diagram of a tap type delay line, and FIG. 8 is a block diagram of a tap type delay device.

The sliding delay line 1 shown in FIG. 6 is constructed by alternately connecting buffers 2 and variable resistors 3, and the number of connected buffers 2 and variable resistors 3 depends on the input clock CK. This is determined by the amount of delay. The variable resistor 3 is configured such that the resistance value can be varied by arbitrarily moving the slide portion 3a from the left end to the right end, thereby delaying the input clock CK. In other words, when measuring the input phase margin by delaying the input clock CK, this delay line 1
While looking at the waveform display section of a measuring device (not shown) in which the variable resistor 3 is incorporated, the slide section 3a of the variable resistor 3 is moved to obtain a desired waveform.

The tap type delay line 4 shown in FIG.
The buffer 5 and variable resistor 6 are configured by alternately connecting an arbitrary number of buffers 5 and variable resistors 6, respectively. Variable resistor 6
has a plurality of sets of opposing connection terminals 6a, 6b that can short-circuit the input side and output side by setting a tap, and the resistance value can be varied by short-circuiting any connection terminal 6a, 6b. It has become. Normally, when measuring the input phase margin by delaying the input clock CK, check the connection terminals 6a and 6 while looking at the waveform display.
b are successively shorted from the left end to the right end to obtain the desired waveform.

The tap type delay device 8 shown in FIG. 8 includes an arbitrary number of buffers 9 connected in series, and each buffer 9.
It is composed of connection terminals 10a and 10b connected to the connection line between them and the input/output line of the buffer 9 at both ends. The resistance value can be varied by short-circuiting any of the connection terminals 10a and 10b with a tap.Normally, when measuring the input phase margin by delaying the clock CK, while looking at the waveform display section, The connecting terminals 10a and 10b are short-circuited in sequence from the lower end to the upper end to obtain a desired waveform.

[0008]

[Problems to be Solved by the Invention] In each of the delay means described above, the lower the frequency of the clock, the more variable resistors 3, 6 are required to delay the clock.
and buffer 9 must be used. In this case, if you try to measure the input phase margin by delaying the clock, you will need to replace many taps in the case of a tap type, or you will need to adjust the slides of variable resistor 3 in many cases in the case of a slide type. Therefore, there is a problem that measurement takes time.

Furthermore, with the tap-type delay means, the delay time per tap is fixed, so the delay time cannot be finely adjusted, and the resistance value of each buffer 9 varies, so that it is not possible to accurately adjust the delay time. There is a problem in that it cannot be measured.

Furthermore, when the length of the delay line becomes long, the duty ratio of the output clock of the delay line fluctuates due to fluctuations in the resistance R and capacitance C, which distorts the measurement waveform and prevents accurate measurement. There are also some problems.

The present invention has been made in view of these points, and it is possible to delay an input clock by a desired amount of time with a short operation, and also to obtain a waveform with a desired duty ratio and no disturbance. It is an object of the present invention to provide a low frequency delay circuit that can obtain a delayed clock.

0012

[Means for Solving the Problems] FIG. 1 shows a diagram of the principle of the present invention. The low frequency delay circuit of the present invention shown in this figure is composed of a delay generation means 12 and a duty ratio correction means 13.

The delay generation means 12 arbitrarily delays the input clock CK and outputs it. When the clock CK is input, the delay generation means 12 generates a clock CK1 having a pulse width determined by a time constant.
It has a first monostable multivibrator 14 that outputs a value of It is composed of

The duty ratio correction means 13 arbitrarily sets the duty ratio of the output delayed clock CK2, and when the clock CK1 from the first monostable multivibrator 14 is inputted, the duty ratio correction means 13 sets a pulse determined by a time constant. a second monostable multivibrator 19 that outputs a delayed clock with a width of 100 seconds, a second capacitor 21 that is an element that determines its time constant, and a second variable resistance means 20 that changes the time constant by arbitrarily varying the resistance value. It is composed of:

Further, the first variable resistance means 15 can be constructed by connecting in series a variable resistor for coarsely adjusting the resistance and a variable resistor for finely adjusting the resistance. The variable resistance means can be configured by connecting in series a variable resistor for coarsely adjusting the resistance and a variable resistor for finely adjusting the resistance.

[0016]

[Operation] According to the present invention described above, when the clock CK is input to the delay generation means 12, the clock CK1 having a pulse width determined by the time constant is outputted.
is input to the duty ratio correcting means 13, and the delayed clock CK2 is output from the duty ratio correcting means 13. At this time, by arbitrarily varying the resistance value of the variable resistance means 20, the pulse width of the delayed clock CK2 can be set to a desired width, thereby making it possible to set the duty ratio of the delayed clock CK2 to a desired ratio.

Further, after setting this duty ratio, by arbitrarily varying the variable resistance means 15, the delay time of the delayed clock CK1 can be changed, thereby adjusting the delay time of the delayed clock CK2 to a desired value. can be done in time.

Therefore, according to such adjustment, it is possible to obtain a stable delayed clock without waveform disturbance, and furthermore, after adjusting the variable resistance means 20, the variable resistor 1
Since it is only necessary to adjust 5, it can be easily carried out in a short time.

Furthermore, if the variable resistance means 15 and 20 are constructed by connecting a variable resistor for coarse adjustment and a variable resistor for fine adjustment in series, the duty ratio and delay time of the delay clock CK2 can be adjusted. It is possible to set it with higher precision.

[0020] Furthermore, if the delayed clock output from such a low frequency delay circuit is applied to the input phase margin measurement of a circuit under test such as an LSI, since the clock is stable, it is possible to obtain an appropriate input phase margin. It is possible to easily obtain a stable delay clock in a short time.
The input phase margin measurement itself can also be performed in a short time.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing the configuration of a low frequency delay circuit according to an embodiment of the present invention.

The low frequency delay circuit 11 shown in this figure is composed of a delay generation circuit 12 and a duty correction circuit 13. In the delay generation circuit 12, 14 is a monostable multivibrator, which has a function of outputting a pulse with a constant time width determined by an external resistor 15 and a capacitor 18 when the clock CK is input to the clock input terminal 14a. have. The external resistor 15 is a variable resistor 16 for adjusting the delay of the clock CK, one end of which is fixed at +5V.
and a variable resistor 17 connected in series to the variable resistor 16 for finely adjusting the delay.

The duty correction circuit 13 is composed of a monostable multivibrator 19 similar to the monostable multivibrator 14, a variable resistor 20 for duty correction whose one end is fixed at +5V, and a capacitor 21. The clock input terminal 19a of the multivibrator 19
is connected to the signal inversion output terminal 14b of the multivibrator 14.

In the low frequency delay circuit 11 having such a configuration, the clock CK shown in FIG.
When the clock signal CK is input to the input terminal 14a of the clock CK, as shown in the figure, the clock signal CK1 is inverted and delayed by a desired time from the inverted output terminal 14b. This clock signal CK1 is input to the input terminal 19a of the multivibrator 19, and the delayed clock CK2 shown in the figure is output from the signal output terminal 19b.

As explained in the conventional example, this delayed clock CK2 is used when measuring the input phase margin, so it must have a stable waveform without any disturbance. It is necessary to adjust the "L" level pulse width T1 of the clock signal CK1 and the "H" level pulse width T2 of the delayed clock CK2 to desired widths. This adjustment is performed by variable resistors 16 and 17 and variable resistor 20. First, variable resistor 16
The pulse width T1 of the clock signal CK1 is adjusted while varying the resistance value of the clock signal CK1. At this time, if fine adjustment is necessary, it is adjusted using the variable resistor 17. And variable resistor 20
The width T2 of the delay clock CK2 is changed by varying the resistance value of the delay clock CK2.
Adjust. After this adjustment, the pulse width T2 of the delayed clock CK2 can be maintained at a desired width simply by adjusting the variable resistors 16 and 17.

As explained above, according to the low frequency delay circuit 11 of the present invention, the pulse width T2 of the delayed clock CK2 outputted from the circuit 11 can be maintained at a desired width, so that the duty ratio can be varied. This allows the delay clock CK2 to have a stable waveform.
can be obtained.

Next, a case will be described with reference to FIG. 4 in which input phase margin measurement for an ES evaluation test of an LSI is performed using a measuring device to which the low frequency delay circuit 11 is applied. FIG. 4 is a diagram showing the configuration of a measuring device that performs input phase margin measurement.

In this figure, 30 is an oscillator, which generates a pulse P of a desired frequency. A pattern generator 31 generates and outputs data D and a clock CK shown in FIG. 5 when the pulse P is input. 11 is Figure 2
This is the low frequency delay circuit shown in FIG.
2 delays the input clock CK by a desired time and outputs the clock CK1 shown in FIG. 5. Next, the duty correction circuit 13 adjusts the duty ratio and outputs the clock CK2 shown in FIG. 32 is an LSI to be measured, and by inputting the clock CK2 and data D, its input phase margin is measured. Further, the measurement result of the input phase margin can be obtained by a bit error rate measuring device (BER measuring device) 33 connected to the output side of the LSI 32.

[0029] With the measuring device having such a configuration, the LS
When measuring the input phase margin of I32, first adjust the pulse width T2 of the output clock CK2 using the variable resistor 20 of the duty correction circuit 13, and then adjust the pulse width T2 of the output clock CK2.
Set the duty ratio of 2 to 50%. Then, the variable resistors 16 and 17 of the delay generation circuit 12 generate the clock CK1.
By adjusting the pulse width T1 of clock CK
2 gradually approaches the changing point D1 of data D.

At this time, the data D input to the LSI 32
If the data D is triggered by the clock CK2, the BER measuring device 33 will not detect an error, but if the data D is no longer triggered, the BER measuring device 33 will detect a bit error. In other words, depending on the detection state of this error, the LS
The input phase margin of I32 can be known.

Also, the delay generation circuit 12 of the low frequency delay circuit 11 and the variable resistors 16, 1 of the duty correction circuit 13
7 and 20 and capacitors 18 and 21 are selected depending on the frequency of the input clock CK when performing input phase margin measurement.

Furthermore, according to the above-described low frequency delay circuit 11, the duty ratio can be freely varied, so that the allowable range of the duty ratio can also be measured.

[0033]

As explained above, according to the low frequency delay circuit of the present invention, the input clock can be delayed by a desired time with a short operation, and moreover, the input clock can be delayed at the desired duty ratio without any disturbance. This has the effect of being able to obtain a waveform delayed clock.

Furthermore, if the low frequency delay circuit is applied to a measuring device that measures the input phase margin of an ES evaluation test, it is possible to accurately measure the input phase margin of the circuit under test in a short time.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing the configuration of a low frequency delay circuit according to the present invention.

FIG. 2 is a diagram showing the configuration of a low frequency delay circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart of FIG. 2;

FIG. 4 is a diagram showing the configuration of an input phase margin measuring device to which the low frequency delay circuit shown in FIG. 2 is applied.

FIG. 5 is a timing chart of FIG. 4;

FIG. 6 is a configuration diagram of a conventional sliding delay line.

FIG. 7 is a configuration diagram of a conventional tap-type delay line.

FIG. 8 is a configuration diagram of a conventional tap-type delay device.

[Explanation of symbols]

12 Delay generation means 13 Duty ratio adjustment means 14 First monostable multivibrator 15 First variable resistance means 18 First capacitor 19 Second monostable multivibrator 20 Second variable resistance means 21 Second capacitor CK Input clock CK1 Delay generation means Clock CK2 output from
delay clock

Claims (2)

[Claims] Claim 1: A low-frequency delay circuit that arbitrarily delays and outputs an input clock (CK), which outputs a clock (CK1) with a pulse width determined by a time constant when the clock (CK) is input. a first monostable multivibrator (14), a first capacitor (18) serving as an element for determining the time constant, and a first variable resistance means (14) for varying the time constant by arbitrarily varying the resistance value. 15
) and a clock (CK1) from the first monostable multivibrator (14).
is input, the second monostable multivibrator (19) outputs a delayed clock (CK2) with a pulse width determined by the time constant, the second capacitor (21), which is an element that determines the time constant, and the resistor. 1. A low frequency delay circuit comprising: second variable resistance means (20) for varying the time constant by arbitrarily varying the value thereof; and duty ratio correction means (13) having duty ratio correction means (13). 2. The low frequency delay circuit according to claim 1, wherein the delayed clock (CK2) is used for measuring an input phase margin of a circuit under test.